1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <watchdog.h>
10
11 #include <mpc8xx.h>
12 #include <asm/cpm_8xx.h>
13 #include <asm/io.h>
14
15 /*
16 * Breath some life into the CPU...
17 *
18 * Set up the memory map,
19 * initialize a bunch of registers,
20 * initialize the UPM's
21 */
cpu_init_f(immap_t __iomem * immr)22 void cpu_init_f(immap_t __iomem *immr)
23 {
24 memctl8xx_t __iomem *memctl = &immr->im_memctl;
25 ulong reg;
26
27 /* SYPCR - contains watchdog control (11-9) */
28
29 #ifndef CONFIG_HW_WATCHDOG
30 /* deactivate watchdog if not enabled in config */
31 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
32 #endif
33
34 WATCHDOG_RESET();
35
36 /* SIUMCR - contains debug pin configuration (11-6) */
37 setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
38 /* initialize timebase status and control register (11-26) */
39 /* unlock TBSCRK */
40
41 out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
42 out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
43
44 /* Unlock timebase register */
45 out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
46
47 /* initialize the PIT (11-31) */
48
49 out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
50 out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
51
52 /* System integration timers. Don't change EBDF! (15-27) */
53
54 out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
55 clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
56 CONFIG_SYS_SCCR);
57
58 /*
59 * MPC866/885 ERRATA GLL2
60 * Description:
61 * In 1:2:1 mode, when HRESET is detected at the positive edge of
62 * EXTCLK, then there will be a loss of phase between
63 * EXTCLK and CLKOUT.
64 *
65 * Workaround:
66 * Reprogram the SCCR:
67 * 1. Write 1'b00 to SCCR[EBDF].
68 * 2. Write 1'b01 to SCCR[EBDF].
69 * 3. Rewrite the desired value to the PLPRCR register.
70 */
71 reg = in_be32(&immr->im_clkrst.car_sccr);
72 /* Are we in mode 1:2:1 ? */
73 if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
74 clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
75 setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
76 }
77
78 /* PLL (CPU clock) settings (15-30) */
79
80 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
81
82 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
83 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
84 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
85 * field value.
86 *
87 * For newer (starting MPC866) chips PLPRCR layout is different.
88 */
89 #ifdef CONFIG_SYS_PLPRCR
90 if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
91 out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
92 else /* isolate MF-related fields and reset control bits */
93 clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
94 CONFIG_SYS_PLPRCR);
95 #endif
96
97 /*
98 * Memory Controller:
99 */
100
101 /* Clear everything except Port Size bits & add the "Bank Valid" bit */
102 clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
103
104 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
105 * preliminary addresses - these have to be modified later
106 * when FLASH size has been determined
107 *
108 * Depending on the size of the memory region defined by
109 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
110 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
111 * map CONFIG_SYS_MONITOR_BASE.
112 *
113 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
114 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
115 *
116 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
117 * base address remains as 0x00000000. However, the address mask
118 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
119 * into the Bank0.
120 *
121 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
122 * CONFIG_SYS_BR0_PRELIM in advance.
123 *
124 * [Thanks to Michael Liao for this explanation.
125 * I owe him a free beer. - wd]
126 */
127
128 #if defined(CONFIG_SYS_OR0_REMAP)
129 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
130 #endif
131 #if defined(CONFIG_SYS_OR1_REMAP)
132 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
133 #endif
134 #if defined(CONFIG_SYS_OR5_REMAP)
135 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
136 #endif
137
138 /* now restrict to preliminary range */
139 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
140 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
141
142 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
143 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
144 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
145 #endif
146
147 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
148 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
149 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
150 #endif
151
152 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
153 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
154 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
155 #endif
156
157 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
158 out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
159 out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
160 #endif
161
162 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
163 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
164 out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
165 #endif
166
167 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
168 out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
169 out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
170 #endif
171
172 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
173 out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
174 out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
175 #endif
176
177 /*
178 * Reset CPM
179 */
180 out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
181 /* Spin until command processed */
182 while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
183 ;
184 }
185
186 /*
187 * initialize higher level parts of CPU like timers
188 */
cpu_init_r(void)189 int cpu_init_r(void)
190 {
191 return 0;
192 }
193