1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2017 Microsemi Corporation. 4 * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> 5 */ 6 7 #ifndef RISCV_CSR_ENCODING_H 8 #define RISCV_CSR_ENCODING_H 9 10 #include <asm/csr.h> 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 #if CONFIG_IS_ENABLED(RISCV_SMODE) 16 #define MODE_PREFIX(__suffix) s##__suffix 17 #else 18 #define MODE_PREFIX(__suffix) m##__suffix 19 #endif 20 21 #define MSTATUS_UIE 0x00000001 22 #define MSTATUS_SIE 0x00000002 23 #define MSTATUS_HIE 0x00000004 24 #define MSTATUS_MIE 0x00000008 25 #define MSTATUS_UPIE 0x00000010 26 #define MSTATUS_SPIE 0x00000020 27 #define MSTATUS_HPIE 0x00000040 28 #define MSTATUS_MPIE 0x00000080 29 #define MSTATUS_SPP 0x00000100 30 #define MSTATUS_HPP 0x00000600 31 #define MSTATUS_MPP 0x00001800 32 #define MSTATUS_FS 0x00006000 33 #define MSTATUS_XS 0x00018000 34 #define MSTATUS_MPRV 0x00020000 35 #define MSTATUS_PUM 0x00040000 36 #define MSTATUS_VM 0x1F000000 37 #define MSTATUS32_SD 0x80000000 38 #define MSTATUS64_SD 0x8000000000000000 39 40 #define MCAUSE32_CAUSE 0x7FFFFFFF 41 #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF 42 #define MCAUSE32_INT 0x80000000 43 #define MCAUSE64_INT 0x8000000000000000 44 45 #define SSTATUS_UIE 0x00000001 46 #define SSTATUS_SIE 0x00000002 47 #define SSTATUS_UPIE 0x00000010 48 #define SSTATUS_SPIE 0x00000020 49 #define SSTATUS_SPP 0x00000100 50 #define SSTATUS_FS 0x00006000 51 #define SSTATUS_XS 0x00018000 52 #define SSTATUS_PUM 0x00040000 53 #define SSTATUS32_SD 0x80000000 54 #define SSTATUS64_SD 0x8000000000000000 55 56 #define MIP_SSIP BIT(IRQ_S_SOFT) 57 #define MIP_MSIP BIT(IRQ_M_SOFT) 58 #define MIP_STIP BIT(IRQ_S_TIMER) 59 #define MIP_MTIP BIT(IRQ_M_TIMER) 60 #define MIP_SEIP BIT(IRQ_S_EXT) 61 #define MIP_MEIP BIT(IRQ_M_EXT) 62 63 #define SIP_SSIP MIP_SSIP 64 #define SIP_STIP MIP_STIP 65 66 #define PRV_U 0 67 #define PRV_S 1 68 #define PRV_H 2 69 #define PRV_M 3 70 71 #define VM_MBARE 0 72 #define VM_MBB 1 73 #define VM_MBBID 2 74 #define VM_SV32 8 75 #define VM_SV39 9 76 #define VM_SV48 10 77 78 #define CAUSE_MISALIGNED_FETCH 0 79 #define CAUSE_FETCH_ACCESS 1 80 #define CAUSE_ILLEGAL_INSTRUCTION 2 81 #define CAUSE_BREAKPOINT 3 82 #define CAUSE_MISALIGNED_LOAD 4 83 #define CAUSE_LOAD_ACCESS 5 84 #define CAUSE_MISALIGNED_STORE 6 85 #define CAUSE_STORE_ACCESS 7 86 #define CAUSE_USER_ECALL 8 87 #define CAUSE_SUPERVISOR_ECALL 9 88 #define CAUSE_MACHINE_ECALL 11 89 #define CAUSE_FETCH_PAGE_FAULT 12 90 #define CAUSE_LOAD_PAGE_FAULT 13 91 #define CAUSE_STORE_PAGE_FAULT 15 92 93 #define DEFAULT_RSTVEC 0x00001000 94 #define DEFAULT_NMIVEC 0x00001004 95 #define DEFAULT_MTVEC 0x00001010 96 #define CONFIG_STRING_ADDR 0x0000100C 97 #define EXT_IO_BASE 0x40000000 98 #define DRAM_BASE 0x80000000 99 100 // page table entry (PTE) fields 101 #define PTE_V 0x001 // Valid 102 #define PTE_TYPE 0x01E // Type 103 #define PTE_R 0x020 // Referenced 104 #define PTE_D 0x040 // Dirty 105 #define PTE_SOFT 0x380 // Reserved for Software 106 107 #define PTE_TYPE_TABLE 0x00 108 #define PTE_TYPE_TABLE_GLOBAL 0x02 109 #define PTE_TYPE_URX_SR 0x04 110 #define PTE_TYPE_URWX_SRW 0x06 111 #define PTE_TYPE_UR_SR 0x08 112 #define PTE_TYPE_URW_SRW 0x0A 113 #define PTE_TYPE_URX_SRX 0x0C 114 #define PTE_TYPE_URWX_SRWX0x0E 115 #define PTE_TYPE_SR 0x10 116 #define PTE_TYPE_SRW 0x12 117 #define PTE_TYPE_SRX 0x14 118 #define PTE_TYPE_SRWX 0x16 119 #define PTE_TYPE_SR_GLOBAL 0x18 120 #define PTE_TYPE_SRW_GLOBAL 0x1A 121 #define PTE_TYPE_SRX_GLOBAL 0x1C 122 #define PTE_TYPE_SRWX_GLOBAL 0x1E 123 124 #define PTE_PPN_SHIFT 10 125 126 #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) 127 #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) 128 #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) 129 #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) 130 #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) 131 #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) 132 #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) 133 134 #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ 135 typeof(_PTE) (PTE) = (_PTE); \ 136 typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ 137 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ 138 (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ 139 ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) 140 141 #ifdef __riscv 142 143 #ifdef CONFIG_64BIT 144 # define MSTATUS_SD MSTATUS64_SD 145 # define SSTATUS_SD SSTATUS64_SD 146 # define MCAUSE_INT MCAUSE64_INT 147 # define MCAUSE_CAUSE MCAUSE64_CAUSE 148 # define RISCV_PGLEVEL_BITS 9 149 #else 150 # define MSTATUS_SD MSTATUS32_SD 151 # define SSTATUS_SD SSTATUS32_SD 152 # define RISCV_PGLEVEL_BITS 10 153 # define MCAUSE_INT MCAUSE32_INT 154 # define MCAUSE_CAUSE MCAUSE32_CAUSE 155 #endif 156 157 #define RISCV_PGSHIFT 12 158 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) 159 160 #endif /* __riscv */ 161 162 #endif /* RISCV_CSR_ENCODING_H */ 163