1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2015 General Electric Company
4  */
5 
6 #ifndef __PPD_GPIO_H_
7 #define __PPD_GPIO_H_
8 
9 #include <asm/arch/iomux-mx53.h>
10 #include <asm/gpio.h>
11 
12 static const iomux_v3_cfg_t ppd_pads[] = {
13 	/* FEC */
14 	MX53_PAD_EIM_A22__GPIO2_16,
15 	/* Video */
16 	MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
17 	MX53_PAD_CSI0_VSYNC__GPIO5_21,	 /* UD_SCAN_CTRL */
18 	MX53_PAD_CSI0_DAT10__GPIO5_28,	 /* DATA_WIDTH_CTRL */
19 	MX53_PAD_CSI0_PIXCLK__GPIO5_18,	 /* HOST_CONTROLLED_RESET_TO_LCD_N */
20 	MX53_PAD_EIM_DA2__GPIO3_2,	 /* LVDS1_MUX_CTRL */
21 	MX53_PAD_EIM_DA3__GPIO3_3,	 /* LVDS0_MUX_CTRL */
22 	MX53_PAD_EIM_A21__GPIO2_17,	 /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
23 	MX53_PAD_CSI0_DAT11__GPIO5_29,	 /* BACKLIGHT_ENABLE */
24 	MX53_PAD_DISP0_DAT9__PWM2_PWMO,	 /* IMX535_PWM2_TO_LCD_CONNECTOR */
25 	/* I2C */
26 	MX53_PAD_EIM_A20__GPIO2_18,	 /* RESET_I2C1_BUS_SEGMENT_MUX_N */
27 
28 	/* SPI */
29 	MX53_PAD_DISP0_DAT23__GPIO5_17,
30 	MX53_PAD_KEY_COL2__GPIO4_10,
31 	MX53_PAD_KEY_ROW2__GPIO4_11,
32 	MX53_PAD_KEY_COL3__GPIO4_12,
33 
34 	MX53_PAD_PATA_DATA7__GPIO2_7,    /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */
35 };
36 
37 struct gpio_cfg {
38 	unsigned int gpio;
39 	int value;
40 };
41 
42 #define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
43 #define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
44 #define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
45 #define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
46 #define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
47 #define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
48 #define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
49 #define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
50 #define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
51 #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
52 #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
53 #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
54 #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
55 #define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
56 #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
57 #define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
58 #define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
59 #define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7)
60 
61 static const struct gpio_cfg ppd_gpios[] = {
62 	/* FEC */
63 	/* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
64 	/* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
65 	{ RESET_IMX535_ETHERNET_PHY_N, 0 },
66 	{ RESET_IMX535_ETHERNET_PHY_N, 1 },
67 	/* Video */
68 	{ UD_SCAN_CTRL, 0 },
69 	{ LR_SCAN_CTRL, 1 },
70 #ifdef PROPRIETARY_CHANGES
71 	{ LVDS0_MUX_CTRL, 1 },
72 #else
73 	{ LVDS0_MUX_CTRL, 0 },
74 #endif
75 	{ LVDS1_MUX_CTRL, 1 },
76 	{ HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
77 	{ DATA_WIDTH_CTRL, 0 },
78 	{ RESET_DP0_TRANSMITTER_N, 1 },
79 	{ RESET_DP1_TRANSMITTER_N, 1 },
80 	{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
81 	{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
82 	{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
83 	{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
84 	{ ECSPI1_CS0, 1 },
85 	{ ECSPI1_CS1, 1 },
86 	{ ECSPI1_CS2, 1 },
87 	{ ECSPI1_CS3, 1 },
88 	{ BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 },
89 };
90 
91 #endif /* __PPD_GPIO_H_ */
92