1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef __DDR3_TRAINING_H
7 #define __DDR3_TRAINING_H
8 
9 #include "ddr3_init.h"
10 
11 #ifdef MV88F78X60
12 #include "ddr3_axp.h"
13 #elif defined(MV88F67XX)
14 #include "ddr3_a370.h"
15 #elif defined(MV88F672X)
16 #include "ddr3_a375.h"
17 #endif
18 
19 /* The following is a list of Marvell status    */
20 #define MV_ERROR	(-1)
21 #define MV_OK		(0x00)	/* Operation succeeded                   */
22 #define MV_FAIL		(0x01)	/* Operation failed                      */
23 #define MV_BAD_VALUE	(0x02)	/* Illegal value (general)               */
24 #define MV_OUT_OF_RANGE	(0x03)	/* The value is out of range             */
25 #define MV_BAD_PARAM	(0x04)	/* Illegal parameter in function called  */
26 #define MV_BAD_PTR	(0x05)	/* Illegal pointer value                 */
27 #define MV_BAD_SIZE	(0x06)	/* Illegal size                          */
28 #define MV_BAD_STATE	(0x07)	/* Illegal state of state machine        */
29 #define MV_SET_ERROR	(0x08)	/* Set operation failed                  */
30 #define MV_GET_ERROR	(0x09)	/* Get operation failed                  */
31 #define MV_CREATE_ERROR	(0x0A)	/* Fail while creating an item           */
32 #define MV_NOT_FOUND	(0x0B)	/* Item not found                        */
33 #define MV_NO_MORE	(0x0C)	/* No more items found                   */
34 #define MV_NO_SUCH	(0x0D)	/* No such item                          */
35 #define MV_TIMEOUT	(0x0E)	/* Time Out                              */
36 #define MV_NO_CHANGE	(0x0F)	/* Parameter(s) is already in this value */
37 #define MV_NOT_SUPPORTED (0x10)	/* This request is not support           */
38 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
39 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized          */
40 #define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
41 #define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
42 #define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
43 #define MV_INIT_ERROR	(0x16)	/* Error occurred while INIT process      */
44 #define MV_HW_ERROR	(0x17)	/* Hardware error                        */
45 #define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
46 #define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
47 #define MV_NOT_READY	(0x1A)	/* The other side is not ready yet       */
48 #define MV_ALREADY_EXIST (0x1B)	/* Tried to create existing item         */
49 #define MV_OUT_OF_CPU_MEM   (0x1C) /* Cpu memory allocation failed.      */
50 #define MV_NOT_STARTED	(0x1D)	/* Not started yet                       */
51 #define MV_BUSY		(0x1E)	/* Item is busy.                         */
52 #define MV_TERMINATE	(0x1F)	/* Item terminates it's work.            */
53 #define MV_NOT_ALIGNED	(0x20)	/* Wrong alignment                       */
54 #define MV_NOT_ALLOWED	(0x21)	/* Operation NOT allowed                 */
55 #define MV_WRITE_PROTECT (0x22)	/* Write protected                       */
56 
57 #define MV_INVALID	(int)(-1)
58 
59 /*
60  * Debug (Enable/Disable modules) and Error report
61  */
62 
63 #ifdef BASIC_DEBUG
64 #define MV_DEBUG_WL
65 #define MV_DEBUG_RL
66 #define MV_DEBUG_DQS_RESULTS
67 #endif
68 
69 #ifdef FULL_DEBUG
70 #define MV_DEBUG_WL
71 #define MV_DEBUG_RL
72 #define MV_DEBUG_DQS
73 
74 #define MV_DEBUG_PBS
75 #define MV_DEBUG_DFS
76 #define MV_DEBUG_MAIN_FULL
77 #define MV_DEBUG_DFS_FULL
78 #define MV_DEBUG_DQS_FULL
79 #define MV_DEBUG_RL_FULL
80 #define MV_DEBUG_WL_FULL
81 #endif
82 
83 /*
84  * General Consts
85  */
86 
87 #define SDRAM_READ_WRITE_LEN_IN_WORDS           16
88 #define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS    8
89 #define CACHE_LINE_SIZE                         0x20
90 
91 #define SDRAM_CS_BASE                           0x0
92 
93 #define SRAM_BASE                               0x40000000
94 #define SRAM_SIZE                               0xFFF
95 
96 #define LEN_64BIT_STD_PATTERN                   16
97 #define LEN_64BIT_KILLER_PATTERN                128
98 #define LEN_64BIT_SPECIAL_PATTERN               128
99 #define LEN_64BIT_PBS_PATTERN                   16
100 #define LEN_WL_SUP_PATTERN		                32
101 
102 #define LEN_16BIT_STD_PATTERN                   4
103 #define LEN_16BIT_KILLER_PATTERN                128
104 #define LEN_16BIT_SPECIAL_PATTERN               128
105 #define LEN_16BIT_PBS_PATTERN                   4
106 
107 #define CMP_BYTE_SHIFT                          8
108 #define CMP_BYTE_MASK                           0xFF
109 #define PUP_SIZE                                8
110 
111 #define S 0
112 #define C 1
113 #define P 2
114 #define D 3
115 #define DQS 6
116 #define PS 2
117 #define DS 3
118 #define PE 4
119 #define DE 5
120 
121 #define CS0                                     0
122 #define MAX_DIMM_NUM                            2
123 #define MAX_DELAY                               0x1F
124 
125 /*
126  * Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
127  * Armada 370 & AXP Z1
128  */
129 #define MAX_DELAY_INV_LIMIT                     0x5
130 #define MIN_DELAY_PHASE_1_LIMIT                 0x10
131 
132 #define MAX_DELAY_INV                           (0x3F - MAX_DELAY_INV_LIMIT)
133 #define MIN_DELAY                               0
134 #define MAX_PUP_NUM                             9
135 #define ECC_PUP                                 8
136 #define DQ_NUM                                  8
137 #define DQS_DQ_NUM                              8
138 #define INIT_WL_DELAY                           13
139 #define INIT_RL_DELAY                           15
140 #define TWLMRD_DELAY                            20
141 #define TCLK_3_DELAY                            3
142 #define ECC_BIT                                 8
143 #define DMA_SIZE                                64
144 #define MV_DMA_0                                0
145 #define MAX_TRAINING_RETRY                      10
146 
147 #define PUP_RL_MODE                             0x2
148 #define PUP_WL_MODE                             0
149 #define PUP_PBS_TX                              0x10
150 #define PUP_PBS_TX_DM                           0x1A
151 #define PUP_PBS_RX                              0x30
152 #define PUP_DQS_WR                              0x1
153 #define PUP_DQS_RD                              0x3
154 #define PUP_BC                                  10
155 #define PUP_DELAY_MASK                          0x1F
156 #define PUP_PHASE_MASK                          0x7
157 #define PUP_NUM_64BIT                           8
158 #define PUP_NUM_32BIT                           4
159 #define PUP_NUM_16BIT                           2
160 
161 /* control PHY registers */
162 #define CNTRL_PUP_DESKEW                        0x10
163 
164 /* WL */
165 #define COUNT_WL_HI_FREQ                        2
166 #define COUNT_WL                                2
167 #define COUNT_WL_RFRS                           9
168 #define WL_HI_FREQ_SHIFT                        2
169 #define WL_HI_FREQ_STATE                        1
170 #define COUNT_HW_WL                             2
171 
172 /* RL */
173 /*
174  * RL_MODE - this define uses the RL mode SW RL instead of the functional
175  * window SW RL
176  */
177 #define RL_MODE
178 #define RL_WINDOW_WA
179 #define MAX_PHASE_1TO1                          2
180 #define MAX_PHASE_2TO1                          4
181 
182 #define MAX_PHASE_RL_UL_1TO1                    0
183 #define MAX_PHASE_RL_L_1TO1                     4
184 #define MAX_PHASE_RL_UL_2TO1                    3
185 #define MAX_PHASE_RL_L_2TO1                     7
186 
187 #define RL_UNLOCK_STATE                         0
188 #define RL_WINDOW_STATE                         1
189 #define RL_FINAL_STATE                          2
190 #define RL_RETRY_COUNT                          2
191 #define COUNT_HW_RL                             2
192 
193 /* PBS */
194 #define MAX_PBS                                 31
195 #define MIN_PBS                                 0
196 #define COUNT_PBS_PATTERN                       2
197 #define COUNT_PBS_STARTOVER                     2
198 #define COUNT_PBS_REPEAT                        3
199 #define COUNT_PBS_COMP_RETRY_NUM                2
200 #define PBS_DIFF_LIMIT                          31
201 #define PATTERN_PBS_TX_A                        0x55555555
202 #define PATTERN_PBS_TX_B                        0xAAAAAAAA
203 
204 /* DQS */
205 #define ADLL_ERROR                              0x55
206 #define ADLL_MAX                                31
207 #define ADLL_MIN                                0
208 #define MIN_WIN_SIZE                            4
209 #define VALID_WIN_THRS                          MIN_WIN_SIZE
210 
211 #define MODE_2TO1                               1
212 #define MODE_1TO1                               0
213 
214 /*
215  * Macros
216  */
217 #define IS_PUP_ACTIVE(_data_, _pup_)        (((_data_) >> (_pup_)) & 0x1)
218 
219 /*
220  * Internal ERROR codes
221  */
222 #define MV_DDR3_TRAINING_ERR_WR_LVL_HW              0xDD302001
223 #define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS          0xDD302002
224 #define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ         0xDD302003
225 #define MV_DDR3_TRAINING_ERR_DFS_H2L                0xDD302004
226 #define MV_DDR3_TRAINING_ERR_DRAM_COMPARE           0xDD302005
227 #define MV_DDR3_TRAINING_ERR_WIN_LIMITS             0xDD302006
228 #define MV_DDR3_TRAINING_ERR_PUP_RANGE              0xDD302025
229 #define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH   0xDD302007
230 #define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH  0xDD302008
231 #define MV_DDR3_TRAINING_ERR_DQS_PATTERN            0xDD302009
232 #define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE    0xDD302010
233 #define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL         0xDD302011
234 #define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT         0xDD302012
235 #define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT         0xDD302013
236 #define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL         0xDD302014
237 #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
238 #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL  0xDD302016
239 #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN      0xDD302017
240 #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK   0xDD302018
241 #define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK      0xDD302019
242 #define MV_DDR3_TRAINING_ERR_WR_LVL_SW              0xDD302020
243 #define MV_DDR3_TRAINING_ERR_PRBS_RX                0xDD302021
244 #define MV_DDR3_TRAINING_ERR_DQS_RX                 0xDD302022
245 #define MV_DDR3_TRAINING_ERR_PRBS_TX                0xDD302023
246 #define MV_DDR3_TRAINING_ERR_DQS_TX                 0xDD302024
247 
248 /*
249  * DRAM information structure
250  */
251 typedef struct dram_info {
252 	u32 num_cs;
253 	u32 cs_ena;
254 	u32 num_of_std_pups;	/* Q value = ddrWidth/8 - Without ECC!! */
255 	u32 num_of_total_pups;	/* numOfStdPups + eccEna */
256 	u32 target_frequency;	/* DDR Frequency */
257 	u32 ddr_width;		/* 32/64 Bit or 16/32 Bit */
258 	u32 ecc_ena;		/* 0/1 */
259 	u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
260 	u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
261 	u32 rl_max_phase;
262 	u32 rl_min_phase;
263 	u32 wl_max_phase;
264 	u32 wl_min_phase;
265 	u32 rd_smpl_dly;
266 	u32 rd_rdy_dly;
267 	u32 cl;
268 	u32 cwl;
269 	u32 mode_2t;
270 	int rl400_bug;
271 	int multi_cs_mr_support;
272 	int reg_dimm;
273 } MV_DRAM_INFO;
274 
275 enum training_modes  {
276 	DQS_WR_MODE,
277 	WL_MODE_,
278 	RL_MODE_,
279 	DQS_RD_MODE,
280 	PBS_TX_DM_MODE,
281 	PBS_TX_MODE,
282 	PBS_RX_MODE,
283 	MAX_TRAINING_MODE,
284 };
285 
286 typedef struct dram_training_init {
287 	u32 reg_addr;
288 	u32 reg_value;
289 } MV_DRAM_TRAINING_INIT;
290 
291 typedef struct dram_mv_init {
292 	u32 reg_addr;
293 	u32 reg_value;
294 } MV_DRAM_MC_INIT;
295 
296 /* Board/Soc revisions define */
297 enum board_rev {
298 	Z1,
299 	Z1_PCAC,
300 	Z1_RD_SLED,
301 	A0,
302 	A0_AMC
303 };
304 
305 typedef struct dram_modes {
306 	char *mode_name;
307 	u8 cpu_freq;
308 	u8 fab_freq;
309 	u8 chip_id;
310 	int chip_board_rev;
311 	MV_DRAM_MC_INIT *regs;
312 	MV_DRAM_TRAINING_INIT *vals;
313 } MV_DRAM_MODES;
314 
315 /*
316  * Function Declarations
317  */
318 
319 u32 cache_inv(u32 addr);
320 void flush_l1_v7(u32 line);
321 void flush_l1_v6(u32 line);
322 
323 u32 ddr3_cl_to_valid_cl(u32 cl);
324 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
325 
326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
328 
329 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
330 			   u32 pbs_pattern_idx, u32 pbs_curr_val,
331 			   u32 pbs_lock_val, u32 *skew_array,
332 			   u8 *unlock_pup_dq_array, u32 ecc);
333 
334 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
335 			   u32 *new_locked_pup, u32 *pattern,
336 			   u32 pattern_len, u32 sdram_offset, int write,
337 			   int mask, u32 *mask_pattern, int b_special_compare);
338 
339 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
340 		       u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
341 		       u32 sdram_offset, int write, int mask,
342 		       u32 *mask_pattern, int b_special_compare);
343 
344 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
345 			      u32 *new_locked_pup, u32 *pattern,
346 			      u32 pattern_len, u32 sdram_offset, int write,
347 			      int mask, u32 *mask_pattern);
348 
349 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
350 			  u32 *new_locked_pup, u32 *pattern,
351 			  u32 sdram_offset);
352 int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
353 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
354 
355 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
356 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
357 
358 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
359 int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
360 int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
361 int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
362 
363 int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
364 int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
365 
366 int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
367 int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
368 int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
369 
370 int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
371 int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
372 int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
373 
374 void ddr3_static_training_init(void);
375 
376 u8 ddr3_get_eprom_fabric(void);
377 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
378 int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
379 void ddr3_save_training(MV_DRAM_INFO *dram_info);
380 int ddr3_read_training_results(void);
381 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
382 int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
383 				       u32 *max, u32 *cs_max);
384 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
385 			      u32 cs);
386 int ddr3_odt_activate(int activate);
387 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
388 void ddr3_print_freq(u32 freq);
389 void ddr3_reset_phy_read_fifo(void);
390 
391 #endif /* __DDR3_TRAINING_H */
392