1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 */
7
8 #include <common.h>
9 #include <clock_legacy.h>
10 #include <asm/global_data.h>
11 #include <asm/processor.h>
12
13 #include <asm/immap.h>
14 #include <asm/io.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /*
19 * Low Power Divider specifications
20 */
21 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
22 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
23
24 #define CLOCK_PLL_FVCO_MAX 540000000
25 #define CLOCK_PLL_FVCO_MIN 300000000
26
27 #define CLOCK_PLL_FSYS_MAX 266666666
28 #define CLOCK_PLL_FSYS_MIN 100000000
29 #define MHZ 1000000
30
clock_enter_limp(int lpdiv)31 void clock_enter_limp(int lpdiv)
32 {
33 ccm_t *ccm = (ccm_t *)MMAP_CCM;
34 int i, j;
35
36 /* Check bounds of divider */
37 if (lpdiv < CLOCK_LPD_MIN)
38 lpdiv = CLOCK_LPD_MIN;
39 if (lpdiv > CLOCK_LPD_MAX)
40 lpdiv = CLOCK_LPD_MAX;
41
42 /* Round divider down to nearest power of two */
43 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
44
45 #ifdef CONFIG_MCF5445x
46 /* Apply the divider to the system clock */
47 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
48 #endif
49
50 /* Enable Limp Mode */
51 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
52 }
53
54 /*
55 * brief Exit Limp mode
56 * warning The PLL should be set and locked prior to exiting Limp mode
57 */
clock_exit_limp(void)58 void clock_exit_limp(void)
59 {
60 ccm_t *ccm = (ccm_t *)MMAP_CCM;
61 pll_t *pll = (pll_t *)MMAP_PLL;
62
63 /* Exit Limp mode */
64 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
65
66 /* Wait for the PLL to lock */
67 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
68 ;
69 }
70
71 #ifdef CONFIG_MCF5441x
setup_5441x_clocks(void)72 void setup_5441x_clocks(void)
73 {
74 ccm_t *ccm = (ccm_t *)MMAP_CCM;
75 pll_t *pll = (pll_t *)MMAP_PLL;
76 int temp, vco = 0, bootmod_ccr, pdr;
77
78 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
79
80 switch (bootmod_ccr) {
81 case 0:
82 out_be32(&pll->pcr, 0x00000013);
83 out_be32(&pll->pdr, 0x00e70c61);
84 clock_exit_limp();
85 break;
86 case 2:
87 break;
88 case 3:
89 break;
90 }
91
92 /*Change frequency for Modelo SER1 USB host*/
93 #ifdef CONFIG_LOW_MCFCLK
94 temp = in_be32(&pll->pcr);
95 temp &= ~0x3f;
96 temp |= 5;
97 out_be32(&pll->pcr, temp);
98
99 temp = in_be32(&pll->pdr);
100 temp &= ~0x001f0000;
101 temp |= 0x00040000;
102 out_be32(&pll->pdr, temp);
103 __asm__("tpf");
104 #endif
105
106 setbits_be16(&ccm->misccr2, 0x02);
107
108 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
109 CONFIG_SYS_INPUT_CLKSRC;
110 gd->arch.vco_clk = vco;
111
112 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
113
114 pdr = in_be32(&pll->pdr);
115 temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
116 gd->cpu_clk = vco / temp; /* cpu clock */
117 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
118 gd->arch.flb_clk >>= 1;
119 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
120 gd->arch.flb_clk >>= 1;
121
122 temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
123 gd->bus_clk = vco / temp; /* bus clock */
124
125 temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
126 gd->arch.sdhc_clk = vco / temp;
127 }
128 #endif
129
130 #ifdef CONFIG_MCF5445x
setup_5445x_clocks(void)131 void setup_5445x_clocks(void)
132 {
133 ccm_t *ccm = (ccm_t *)MMAP_CCM;
134 pll_t *pll = (pll_t *)MMAP_PLL;
135 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
136 int pllmult_pci[] = { 12, 6, 16, 8 };
137 int vco = 0, temp, fbtemp, pcrvalue;
138 int *pPllmult = NULL;
139 u16 fbpll_mask;
140 #ifdef CONFIG_PCI
141 int bPci;
142 #endif
143
144 #ifdef CONFIG_M54455EVB
145 u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
146 #endif
147 u8 bootmode;
148
149 /* To determine PCI is present or not */
150 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
151 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
152 pPllmult = &pllmult_pci[0];
153 fbpll_mask = 3; /* 11b */
154 #ifdef CONFIG_PCI
155 bPci = 1;
156 #endif
157 } else {
158 pPllmult = &pllmult_nopci[0];
159 fbpll_mask = 7; /* 111b */
160 #ifdef CONFIG_PCI
161 gd->pci_clk = 0;
162 bPci = 0;
163 #endif
164 }
165
166 #ifdef CONFIG_M54455EVB
167 bootmode = (in_8(cpld) & 0x03);
168
169 if (bootmode != 3) {
170 /* Temporary read from CCR- fixed fb issue, must be the same clock
171 as pci or input clock, causing cpld/fpga read inconsistancy */
172 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
173
174 /* Break down into small pieces, code still in flex bus */
175 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
176 temp = fbtemp - 1;
177 pcrvalue |= PLL_PCR_OUTDIV3(temp);
178
179 out_be32(&pll->pcr, pcrvalue);
180 }
181 #endif
182 #ifdef CONFIG_M54451EVB
183 /* No external logic to read the bootmode, hard coded from built */
184 #ifdef CONFIG_CF_SBF
185 bootmode = 3;
186 #else
187 bootmode = 2;
188
189 /* default value is 16 mul, set to 20 mul */
190 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
191 out_be32(&pll->pcr, pcrvalue);
192 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
193 ;
194 #endif
195 #endif
196
197 if (bootmode == 0) {
198 /* RCON mode */
199 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
200
201 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
202 /* invaild range, re-set in PCR */
203 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
204 int i, j, bus;
205
206 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
207 for (i = j; i < 0xFF; i++) {
208 vco = i * CONFIG_SYS_INPUT_CLKSRC;
209 if (vco >= CLOCK_PLL_FVCO_MIN) {
210 bus = vco / temp;
211 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
212 continue;
213 else
214 break;
215 }
216 }
217 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
218 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
219 pcrvalue |= ((i << 24) | fbtemp);
220
221 out_be32(&pll->pcr, pcrvalue);
222 }
223 gd->arch.vco_clk = vco; /* Vco clock */
224 } else if (bootmode == 2) {
225 /* Normal mode */
226 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
227 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
228 /* Default value */
229 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
230 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
231 out_be32(&pll->pcr, pcrvalue);
232 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
233 }
234 gd->arch.vco_clk = vco; /* Vco clock */
235 } else if (bootmode == 3) {
236 /* serial mode */
237 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
238 gd->arch.vco_clk = vco; /* Vco clock */
239 }
240
241 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
242 /* Limp mode */
243 } else {
244 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
245
246 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
247 gd->cpu_clk = vco / temp; /* cpu clock */
248
249 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
250 gd->bus_clk = vco / temp; /* bus clock */
251
252 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
253 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
254
255 #ifdef CONFIG_PCI
256 if (bPci) {
257 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
258 gd->pci_clk = vco / temp; /* PCI clock */
259 }
260 #endif
261 }
262
263 #ifdef CONFIG_SYS_I2C_FSL
264 gd->arch.i2c1_clk = gd->bus_clk;
265 #endif
266 }
267 #endif
268
269 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
get_clocks(void)270 int get_clocks(void)
271 {
272 #ifdef CONFIG_MCF5441x
273 setup_5441x_clocks();
274 #endif
275 #ifdef CONFIG_MCF5445x
276 setup_5445x_clocks();
277 #endif
278
279 #ifdef CONFIG_SYS_FSL_I2C
280 gd->arch.i2c1_clk = gd->bus_clk;
281 #endif
282
283 return (0);
284 }
285