1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <adc.h>
8 #include <log.h>
9 #include <net.h>
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <bootm.h>
16 #include <clk.h>
17 #include <config.h>
18 #include <dm.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
21 #include <env.h>
22 #include <env_internal.h>
23 #include <g_dnl.h>
24 #include <generic-phy.h>
25 #include <hang.h>
26 #include <i2c.h>
27 #include <i2c_eeprom.h>
28 #include <init.h>
29 #include <led.h>
30 #include <memalign.h>
31 #include <misc.h>
32 #include <mtd.h>
33 #include <mtd_node.h>
34 #include <netdev.h>
35 #include <phy.h>
36 #include <linux/bitops.h>
37 #include <linux/delay.h>
38 #include <power/regulator.h>
39 #include <remoteproc.h>
40 #include <reset.h>
41 #include <syscon.h>
42 #include <usb.h>
43 #include <usb/dwc2_udc.h>
44 #include <watchdog.h>
45 #include "../../st/common/stpmic1.h"
46
47 /* SYSCFG registers */
48 #define SYSCFG_BOOTR 0x00
49 #define SYSCFG_PMCSETR 0x04
50 #define SYSCFG_IOCTRLSETR 0x18
51 #define SYSCFG_ICNR 0x1C
52 #define SYSCFG_CMPCR 0x20
53 #define SYSCFG_CMPENSETR 0x24
54 #define SYSCFG_PMCCLRR 0x44
55
56 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
57 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
58
59 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
60 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
61 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
62 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
63 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
64
65 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
66 #define SYSCFG_CMPCR_READY BIT(8)
67
68 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
69
70 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
71 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
72
73 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
74
75 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
76 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
77 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
78 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
79
80 /*
81 * Get a global data pointer
82 */
83 DECLARE_GLOBAL_DATA_PTR;
84
85 #define KS_CCR 0x08
86 #define KS_CCR_EEPROM BIT(9)
87 #define KS_BE0 BIT(12)
88 #define KS_BE1 BIT(13)
89 #define KS_CIDER 0xC0
90 #define CIDER_ID 0x8870
91
setup_mac_address(void)92 int setup_mac_address(void)
93 {
94 unsigned char enetaddr[6];
95 bool skip_eth0 = false;
96 bool skip_eth1 = false;
97 struct udevice *dev;
98 int off, ret;
99
100 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
101 if (ret) /* ethaddr is already set */
102 skip_eth0 = true;
103
104 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
105 if (off < 0) {
106 /* ethernet1 is not present in the system */
107 skip_eth1 = true;
108 goto out_set_ethaddr;
109 }
110
111 ret = eth_env_get_enetaddr("eth1addr", enetaddr);
112 if (ret) {
113 /* eth1addr is already set */
114 skip_eth1 = true;
115 goto out_set_ethaddr;
116 }
117
118 ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
119 if (ret)
120 goto out_set_ethaddr;
121
122 /*
123 * KS8851 with EEPROM may use custom MAC from EEPROM, read
124 * out the KS8851 CCR register to determine whether EEPROM
125 * is present. If EEPROM is present, it must contain valid
126 * MAC address.
127 */
128 u32 reg, cider, ccr;
129 reg = fdt_get_base_address(gd->fdt_blob, off);
130 if (!reg)
131 goto out_set_ethaddr;
132
133 writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
134 cider = readw(reg);
135 if ((cider & 0xfff0) != CIDER_ID) {
136 skip_eth1 = true;
137 goto out_set_ethaddr;
138 }
139
140 writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
141 ccr = readw(reg);
142 if (ccr & KS_CCR_EEPROM) {
143 skip_eth1 = true;
144 goto out_set_ethaddr;
145 }
146
147 out_set_ethaddr:
148 if (skip_eth0 && skip_eth1)
149 return 0;
150
151 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
152 if (off < 0) {
153 printf("%s: No eeprom0 path offset\n", __func__);
154 return off;
155 }
156
157 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
158 if (ret) {
159 printf("Cannot find EEPROM!\n");
160 return ret;
161 }
162
163 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
164 if (ret) {
165 printf("Error reading configuration EEPROM!\n");
166 return ret;
167 }
168
169 if (is_valid_ethaddr(enetaddr)) {
170 if (!skip_eth0)
171 eth_env_set_enetaddr("ethaddr", enetaddr);
172
173 enetaddr[5]++;
174 if (!skip_eth1)
175 eth_env_set_enetaddr("eth1addr", enetaddr);
176 }
177
178 return 0;
179 }
180
checkboard(void)181 int checkboard(void)
182 {
183 char *mode;
184 const char *fdt_compat;
185 int fdt_compat_len;
186
187 if (IS_ENABLED(CONFIG_TFABOOT))
188 mode = "trusted";
189 else
190 mode = "basic";
191
192 printf("Board: stm32mp1 in %s mode", mode);
193 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
194 &fdt_compat_len);
195 if (fdt_compat && fdt_compat_len)
196 printf(" (%s)", fdt_compat);
197 puts("\n");
198
199 return 0;
200 }
201
202 #ifdef CONFIG_BOARD_EARLY_INIT_F
203 static u8 brdcode __section("data");
204 static u8 ddr3code __section("data");
205 static u8 somcode __section("data");
206 static u32 opp_voltage_mv __section(".data");
207
board_get_coding_straps(void)208 static void board_get_coding_straps(void)
209 {
210 struct gpio_desc gpio[4];
211 ofnode node;
212 int i, ret;
213
214 node = ofnode_path("/config");
215 if (!ofnode_valid(node)) {
216 printf("%s: no /config node?\n", __func__);
217 return;
218 }
219
220 brdcode = 0;
221 ddr3code = 0;
222 somcode = 0;
223
224 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
225 gpio, ARRAY_SIZE(gpio),
226 GPIOD_IS_IN);
227 for (i = 0; i < ret; i++)
228 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
229
230 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
231 gpio, ARRAY_SIZE(gpio),
232 GPIOD_IS_IN);
233 for (i = 0; i < ret; i++)
234 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
235
236 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
237 gpio, ARRAY_SIZE(gpio),
238 GPIOD_IS_IN);
239 for (i = 0; i < ret; i++)
240 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
241
242 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
243 somcode, ddr3code, brdcode);
244 }
245
board_stm32mp1_ddr_config_name_match(struct udevice * dev,const char * name)246 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
247 const char *name)
248 {
249 if (ddr3code == 1 &&
250 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
251 return 0;
252
253 if (ddr3code == 2 &&
254 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
255 return 0;
256
257 if (ddr3code == 3 &&
258 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
259 return 0;
260
261 return -EINVAL;
262 }
263
board_vddcore_init(u32 voltage_mv)264 void board_vddcore_init(u32 voltage_mv)
265 {
266 if (IS_ENABLED(CONFIG_SPL_BUILD))
267 opp_voltage_mv = voltage_mv;
268 }
269
board_early_init_f(void)270 int board_early_init_f(void)
271 {
272 if (IS_ENABLED(CONFIG_SPL_BUILD))
273 stpmic1_init(opp_voltage_mv);
274 board_get_coding_straps();
275
276 return 0;
277 }
278
279 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)280 int board_fit_config_name_match(const char *name)
281 {
282 const char *compat;
283 char test[128];
284
285 compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
286
287 snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
288 compat, somcode, brdcode);
289
290 if (!strcmp(name, test))
291 return 0;
292
293 return -EINVAL;
294 }
295 #endif
296 #endif
297
board_key_check(void)298 static void board_key_check(void)
299 {
300 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
301 ofnode node;
302 struct gpio_desc gpio;
303 enum forced_boot_mode boot_mode = BOOT_NORMAL;
304
305 node = ofnode_path("/config");
306 if (!ofnode_valid(node)) {
307 debug("%s: no /config node?\n", __func__);
308 return;
309 }
310 #ifdef CONFIG_FASTBOOT
311 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
312 &gpio, GPIOD_IS_IN)) {
313 debug("%s: could not find a /config/st,fastboot-gpios\n",
314 __func__);
315 } else {
316 if (dm_gpio_get_value(&gpio)) {
317 puts("Fastboot key pressed, ");
318 boot_mode = BOOT_FASTBOOT;
319 }
320
321 dm_gpio_free(NULL, &gpio);
322 }
323 #endif
324 #ifdef CONFIG_CMD_STM32PROG
325 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
326 &gpio, GPIOD_IS_IN)) {
327 debug("%s: could not find a /config/st,stm32prog-gpios\n",
328 __func__);
329 } else {
330 if (dm_gpio_get_value(&gpio)) {
331 puts("STM32Programmer key pressed, ");
332 boot_mode = BOOT_STM32PROG;
333 }
334 dm_gpio_free(NULL, &gpio);
335 }
336 #endif
337
338 if (boot_mode != BOOT_NORMAL) {
339 puts("entering download mode...\n");
340 clrsetbits_le32(TAMP_BOOT_CONTEXT,
341 TAMP_BOOT_FORCED_MASK,
342 boot_mode);
343 }
344 #endif
345 }
346
347 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
348
349 #include <usb/dwc2_udc.h>
g_dnl_board_usb_cable_connected(void)350 int g_dnl_board_usb_cable_connected(void)
351 {
352 struct udevice *dwc2_udc_otg;
353 int ret;
354
355 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
356 DM_DRIVER_GET(dwc2_udc_otg),
357 &dwc2_udc_otg);
358 if (!ret)
359 debug("dwc2_udc_otg init failed\n");
360
361 return dwc2_udc_B_session_valid(dwc2_udc_otg);
362 }
363
364 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
365 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
366
g_dnl_bind_fixup(struct usb_device_descriptor * dev,const char * name)367 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
368 {
369 if (!strcmp(name, "usb_dnl_dfu"))
370 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
371 else if (!strcmp(name, "usb_dnl_fastboot"))
372 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
373 &dev->idProduct);
374 else
375 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
376
377 return 0;
378 }
379
380 #endif /* CONFIG_USB_GADGET */
381
382 #ifdef CONFIG_LED
get_led(struct udevice ** dev,char * led_string)383 static int get_led(struct udevice **dev, char *led_string)
384 {
385 char *led_name;
386 int ret;
387
388 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
389 if (!led_name) {
390 pr_debug("%s: could not find %s config string\n",
391 __func__, led_string);
392 return -ENOENT;
393 }
394 ret = led_get_by_label(led_name, dev);
395 if (ret) {
396 debug("%s: get=%d\n", __func__, ret);
397 return ret;
398 }
399
400 return 0;
401 }
402
setup_led(enum led_state_t cmd)403 static int setup_led(enum led_state_t cmd)
404 {
405 struct udevice *dev;
406 int ret;
407
408 ret = get_led(&dev, "u-boot,boot-led");
409 if (ret)
410 return ret;
411
412 ret = led_set_state(dev, cmd);
413 return ret;
414 }
415 #endif
416
led_error_blink(u32 nb_blink)417 static void __maybe_unused led_error_blink(u32 nb_blink)
418 {
419 #ifdef CONFIG_LED
420 int ret;
421 struct udevice *led;
422 u32 i;
423 #endif
424
425 if (!nb_blink)
426 return;
427
428 #ifdef CONFIG_LED
429 ret = get_led(&led, "u-boot,error-led");
430 if (!ret) {
431 /* make u-boot,error-led blinking */
432 /* if U32_MAX and 125ms interval, for 17.02 years */
433 for (i = 0; i < 2 * nb_blink; i++) {
434 led_set_state(led, LEDST_TOGGLE);
435 mdelay(125);
436 WATCHDOG_RESET();
437 }
438 }
439 #endif
440
441 /* infinite: the boot process must be stopped */
442 if (nb_blink == U32_MAX)
443 hang();
444 }
445
sysconf_init(void)446 static void sysconf_init(void)
447 {
448 #ifndef CONFIG_TFABOOT
449 u8 *syscfg;
450 #ifdef CONFIG_DM_REGULATOR
451 struct udevice *pwr_dev;
452 struct udevice *pwr_reg;
453 struct udevice *dev;
454 int ret;
455 u32 otp = 0;
456 #endif
457 u32 bootr;
458
459 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
460
461 /* interconnect update : select master using the port 1 */
462 /* LTDC = AXI_M9 */
463 /* GPU = AXI_M8 */
464 /* today information is hardcoded in U-Boot */
465 writel(BIT(9), syscfg + SYSCFG_ICNR);
466
467 /* disable Pull-Down for boot pin connected to VDD */
468 bootr = readl(syscfg + SYSCFG_BOOTR);
469 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
470 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
471 writel(bootr, syscfg + SYSCFG_BOOTR);
472
473 #ifdef CONFIG_DM_REGULATOR
474 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
475 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
476 * The customer will have to disable this for low frequencies
477 * or if AFMUX is selected but the function not used, typically for
478 * TRACE. Otherwise, impact on power consumption.
479 *
480 * WARNING:
481 * enabling High Speed mode while VDD>2.7V
482 * with the OTP product_below_2v5 (OTP 18, BIT 13)
483 * erroneously set to 1 can damage the IC!
484 * => U-Boot set the register only if VDD < 2.7V (in DT)
485 * but this value need to be consistent with board design
486 */
487 ret = uclass_get_device_by_driver(UCLASS_PMIC,
488 DM_DRIVER_GET(stm32mp_pwr_pmic),
489 &pwr_dev);
490 if (!ret) {
491 ret = uclass_get_device_by_driver(UCLASS_MISC,
492 DM_DRIVER_GET(stm32mp_bsec),
493 &dev);
494 if (ret) {
495 pr_err("Can't find stm32mp_bsec driver\n");
496 return;
497 }
498
499 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
500 if (ret > 0)
501 otp = otp & BIT(13);
502
503 /* get VDD = vdd-supply */
504 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
505 &pwr_reg);
506
507 /* check if VDD is Low Voltage */
508 if (!ret) {
509 if (regulator_get_value(pwr_reg) < 2700000) {
510 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
511 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
512 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
513 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
514 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
515 syscfg + SYSCFG_IOCTRLSETR);
516
517 if (!otp)
518 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
519 } else {
520 if (otp)
521 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
522 }
523 } else {
524 debug("VDD unknown");
525 }
526 }
527 #endif
528
529 /* activate automatic I/O compensation
530 * warning: need to ensure CSI enabled and ready in clock driver
531 */
532 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
533
534 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
535 ;
536 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
537 #endif
538 }
539
board_init_fmc2(void)540 static void board_init_fmc2(void)
541 {
542 #define STM32_FMC2_BCR1 0x0
543 #define STM32_FMC2_BTR1 0x4
544 #define STM32_FMC2_BWTR1 0x104
545 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
546 #define STM32_FMC2_BCRx_FMCEN BIT(31)
547 #define STM32_FMC2_BCRx_WREN BIT(12)
548 #define STM32_FMC2_BCRx_RSVD BIT(7)
549 #define STM32_FMC2_BCRx_FACCEN BIT(6)
550 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
551 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
552 #define STM32_FMC2_BCRx_MUXEN BIT(1)
553 #define STM32_FMC2_BCRx_MBKEN BIT(0)
554 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
555 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
556 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
557 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
558 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
559 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
560
561 #define RCC_MP_AHB6RSTCLRR 0x218
562 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
563 #define RCC_MP_AHB6ENSETR 0x19c
564 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
565
566 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
567 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
568 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
569 STM32_FMC2_BCRx_MBKEN;
570 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
571 STM32_FMC2_BTRx_BUSTURN(2) |
572 STM32_FMC2_BTRx_DATAST(0x22) |
573 STM32_FMC2_BTRx_ADDHLD(2) |
574 STM32_FMC2_BTRx_ADDSET(2);
575
576 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
577 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
578 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
579
580 /* KS8851-16MLL -- Muxed mode */
581 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
582 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
583 /* AS7C34098 SRAM on X11 -- Muxed mode */
584 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
585 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
586
587 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
588 }
589
590 /* board dependent setup after realloc */
board_init(void)591 int board_init(void)
592 {
593 /* address of boot parameters */
594 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
595
596 if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
597 gpio_hog_probe_all();
598
599 board_key_check();
600
601 #ifdef CONFIG_DM_REGULATOR
602 regulators_enable_boot_on(_DEBUG);
603 #endif
604
605 sysconf_init();
606
607 board_init_fmc2();
608
609 if (CONFIG_IS_ENABLED(LED))
610 led_default_state();
611
612 return 0;
613 }
614
board_late_init(void)615 int board_late_init(void)
616 {
617 char *boot_device;
618 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
619 const void *fdt_compat;
620 int fdt_compat_len;
621
622 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
623 &fdt_compat_len);
624 if (fdt_compat && fdt_compat_len) {
625 if (strncmp(fdt_compat, "st,", 3) != 0)
626 env_set("board_name", fdt_compat);
627 else
628 env_set("board_name", fdt_compat + 3);
629 }
630 #endif
631
632 /* Check the boot-source to disable bootdelay */
633 boot_device = env_get("boot_device");
634 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
635 env_set("bootdelay", "0");
636
637 #ifdef CONFIG_BOARD_EARLY_INIT_F
638 env_set_ulong("dh_som_rev", somcode);
639 env_set_ulong("dh_board_rev", brdcode);
640 env_set_ulong("dh_ddr3_code", ddr3code);
641 #endif
642
643 return 0;
644 }
645
board_quiesce_devices(void)646 void board_quiesce_devices(void)
647 {
648 #ifdef CONFIG_LED
649 setup_led(LEDST_OFF);
650 #endif
651 }
652
653 /* eth init function : weak called in eqos driver */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)654 int board_interface_eth_init(struct udevice *dev,
655 phy_interface_t interface_type)
656 {
657 u8 *syscfg;
658 u32 value;
659 bool eth_clk_sel_reg = false;
660 bool eth_ref_clk_sel_reg = false;
661
662 /* Gigabit Ethernet 125MHz clock selection. */
663 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
664
665 /* Ethernet 50Mhz RMII clock selection */
666 eth_ref_clk_sel_reg =
667 dev_read_bool(dev, "st,eth_ref_clk_sel");
668
669 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
670
671 if (!syscfg)
672 return -ENODEV;
673
674 switch (interface_type) {
675 case PHY_INTERFACE_MODE_MII:
676 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
677 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
678 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
679 break;
680 case PHY_INTERFACE_MODE_GMII:
681 if (eth_clk_sel_reg)
682 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
683 SYSCFG_PMCSETR_ETH_CLK_SEL;
684 else
685 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
686 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
687 break;
688 case PHY_INTERFACE_MODE_RMII:
689 if (eth_ref_clk_sel_reg)
690 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
691 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
692 else
693 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
694 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
695 break;
696 case PHY_INTERFACE_MODE_RGMII:
697 case PHY_INTERFACE_MODE_RGMII_ID:
698 case PHY_INTERFACE_MODE_RGMII_RXID:
699 case PHY_INTERFACE_MODE_RGMII_TXID:
700 if (eth_clk_sel_reg)
701 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
702 SYSCFG_PMCSETR_ETH_CLK_SEL;
703 else
704 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
705 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
706 break;
707 default:
708 debug("%s: Do not manage %d interface\n",
709 __func__, interface_type);
710 /* Do not manage others interfaces */
711 return -EINVAL;
712 }
713
714 /* clear and set ETH configuration bits */
715 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
716 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
717 syscfg + SYSCFG_PMCCLRR);
718 writel(value, syscfg + SYSCFG_PMCSETR);
719
720 return 0;
721 }
722
723 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)724 int ft_board_setup(void *blob, struct bd_info *bd)
725 {
726 return 0;
727 }
728 #endif
729
board_copro_image_process(ulong fw_image,size_t fw_size)730 static void board_copro_image_process(ulong fw_image, size_t fw_size)
731 {
732 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
733
734 if (!rproc_is_initialized())
735 if (rproc_init()) {
736 printf("Remote Processor %d initialization failed\n",
737 id);
738 return;
739 }
740
741 ret = rproc_load(id, fw_image, fw_size);
742 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
743 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
744
745 if (!ret) {
746 rproc_start(id);
747 env_set("copro_state", "booted");
748 }
749 }
750
751 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
752