1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP
5 */
6
7 #include <common.h>
8 #include <log.h>
9 #include <net.h>
10 #include <asm/io.h>
11 #include <netdev.h>
12 #include <fdt_support.h>
13 #include <fm_eth.h>
14 #include <fsl_mdio.h>
15 #include <fsl_dtsec.h>
16 #include <linux/libfdt.h>
17 #include <malloc.h>
18 #include <asm/arch/fsl_serdes.h>
19
20 #include "../common/qixis.h"
21 #include "../common/fman.h"
22 #include "ls1043aqds_qixis.h"
23
24 #define EMI_NONE 0xFF
25 #define EMI1_RGMII1 0
26 #define EMI1_RGMII2 1
27 #define EMI1_SLOT1 2
28 #define EMI1_SLOT2 3
29 #define EMI1_SLOT3 4
30 #define EMI1_SLOT4 5
31 #define EMI2 6
32
33 static int mdio_mux[NUM_FM_PORTS];
34
35 static const char * const mdio_names[] = {
36 "LS1043AQDS_MDIO_RGMII1",
37 "LS1043AQDS_MDIO_RGMII2",
38 "LS1043AQDS_MDIO_SLOT1",
39 "LS1043AQDS_MDIO_SLOT2",
40 "LS1043AQDS_MDIO_SLOT3",
41 "LS1043AQDS_MDIO_SLOT4",
42 "NULL",
43 };
44
45 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
46 static u8 lane_to_slot[] = {1, 2, 3, 4};
47
ls1043aqds_mdio_name_for_muxval(u8 muxval)48 static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
49 {
50 return mdio_names[muxval];
51 }
52
mii_dev_for_muxval(u8 muxval)53 struct mii_dev *mii_dev_for_muxval(u8 muxval)
54 {
55 struct mii_dev *bus;
56 const char *name;
57
58 if (muxval > EMI2)
59 return NULL;
60
61 name = ls1043aqds_mdio_name_for_muxval(muxval);
62
63 if (!name) {
64 printf("No bus for muxval %x\n", muxval);
65 return NULL;
66 }
67
68 bus = miiphy_get_dev_by_name(name);
69
70 if (!bus) {
71 printf("No bus by name %s\n", name);
72 return NULL;
73 }
74
75 return bus;
76 }
77
78 struct ls1043aqds_mdio {
79 u8 muxval;
80 struct mii_dev *realbus;
81 };
82
ls1043aqds_mux_mdio(u8 muxval)83 static void ls1043aqds_mux_mdio(u8 muxval)
84 {
85 u8 brdcfg4;
86
87 if (muxval < 7) {
88 brdcfg4 = QIXIS_READ(brdcfg[4]);
89 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
90 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
91 QIXIS_WRITE(brdcfg[4], brdcfg4);
92 }
93 }
94
ls1043aqds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)95 static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
96 int regnum)
97 {
98 struct ls1043aqds_mdio *priv = bus->priv;
99
100 ls1043aqds_mux_mdio(priv->muxval);
101
102 return priv->realbus->read(priv->realbus, addr, devad, regnum);
103 }
104
ls1043aqds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)105 static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
106 int regnum, u16 value)
107 {
108 struct ls1043aqds_mdio *priv = bus->priv;
109
110 ls1043aqds_mux_mdio(priv->muxval);
111
112 return priv->realbus->write(priv->realbus, addr, devad,
113 regnum, value);
114 }
115
ls1043aqds_mdio_reset(struct mii_dev * bus)116 static int ls1043aqds_mdio_reset(struct mii_dev *bus)
117 {
118 struct ls1043aqds_mdio *priv = bus->priv;
119
120 return priv->realbus->reset(priv->realbus);
121 }
122
ls1043aqds_mdio_init(char * realbusname,u8 muxval)123 static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
124 {
125 struct ls1043aqds_mdio *pmdio;
126 struct mii_dev *bus = mdio_alloc();
127
128 if (!bus) {
129 printf("Failed to allocate ls1043aqds MDIO bus\n");
130 return -1;
131 }
132
133 pmdio = malloc(sizeof(*pmdio));
134 if (!pmdio) {
135 printf("Failed to allocate ls1043aqds private data\n");
136 free(bus);
137 return -1;
138 }
139
140 bus->read = ls1043aqds_mdio_read;
141 bus->write = ls1043aqds_mdio_write;
142 bus->reset = ls1043aqds_mdio_reset;
143 strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
144
145 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
146
147 if (!pmdio->realbus) {
148 printf("No bus with name %s\n", realbusname);
149 free(bus);
150 free(pmdio);
151 return -1;
152 }
153
154 pmdio->muxval = muxval;
155 bus->priv = pmdio;
156 return mdio_register(bus);
157 }
158
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)159 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
160 enum fm_port port, int offset)
161 {
162 struct fixed_link f_link;
163
164 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
165 if (port == FM1_DTSEC9) {
166 fdt_set_phy_handle(fdt, compat, addr,
167 "sgmii-riser-s1-p1");
168 } else if (port == FM1_DTSEC2) {
169 fdt_set_phy_handle(fdt, compat, addr,
170 "sgmii-riser-s2-p1");
171 } else if (port == FM1_DTSEC5) {
172 fdt_set_phy_handle(fdt, compat, addr,
173 "sgmii-riser-s3-p1");
174 } else if (port == FM1_DTSEC6) {
175 fdt_set_phy_handle(fdt, compat, addr,
176 "sgmii-riser-s4-p1");
177 }
178 } else if (fm_info_get_enet_if(port) ==
179 PHY_INTERFACE_MODE_SGMII_2500) {
180 /* 2.5G SGMII interface */
181 f_link.phy_id = cpu_to_fdt32(port);
182 f_link.duplex = cpu_to_fdt32(1);
183 f_link.link_speed = cpu_to_fdt32(1000);
184 f_link.pause = 0;
185 f_link.asym_pause = 0;
186 /* no PHY for 2.5G SGMII */
187 fdt_delprop(fdt, offset, "phy-handle");
188 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
189 fdt_setprop_string(fdt, offset, "phy-connection-type",
190 "sgmii-2500");
191 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
192 switch (mdio_mux[port]) {
193 case EMI1_SLOT1:
194 switch (port) {
195 case FM1_DTSEC1:
196 fdt_set_phy_handle(fdt, compat, addr,
197 "qsgmii-s1-p1");
198 break;
199 case FM1_DTSEC2:
200 fdt_set_phy_handle(fdt, compat, addr,
201 "qsgmii-s1-p2");
202 break;
203 case FM1_DTSEC5:
204 fdt_set_phy_handle(fdt, compat, addr,
205 "qsgmii-s1-p3");
206 break;
207 case FM1_DTSEC6:
208 fdt_set_phy_handle(fdt, compat, addr,
209 "qsgmii-s1-p4");
210 break;
211 default:
212 break;
213 }
214 break;
215 case EMI1_SLOT2:
216 switch (port) {
217 case FM1_DTSEC1:
218 fdt_set_phy_handle(fdt, compat, addr,
219 "qsgmii-s2-p1");
220 break;
221 case FM1_DTSEC2:
222 fdt_set_phy_handle(fdt, compat, addr,
223 "qsgmii-s2-p2");
224 break;
225 case FM1_DTSEC5:
226 fdt_set_phy_handle(fdt, compat, addr,
227 "qsgmii-s2-p3");
228 break;
229 case FM1_DTSEC6:
230 fdt_set_phy_handle(fdt, compat, addr,
231 "qsgmii-s2-p4");
232 break;
233 default:
234 break;
235 }
236 break;
237 default:
238 break;
239 }
240 fdt_delprop(fdt, offset, "phy-connection-type");
241 fdt_setprop_string(fdt, offset, "phy-connection-type",
242 "qsgmii");
243 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
244 port == FM1_10GEC1) {
245 /* XFI interface */
246 f_link.phy_id = cpu_to_fdt32(port);
247 f_link.duplex = cpu_to_fdt32(1);
248 f_link.link_speed = cpu_to_fdt32(10000);
249 f_link.pause = 0;
250 f_link.asym_pause = 0;
251 /* no PHY for XFI */
252 fdt_delprop(fdt, offset, "phy-handle");
253 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
254 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
255 }
256 }
257
fdt_fixup_board_enet(void * fdt)258 void fdt_fixup_board_enet(void *fdt)
259 {
260 int i;
261 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
262 u32 srds_s1;
263
264 srds_s1 = in_be32(&gur->rcwsr[4]) &
265 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
266 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
267
268 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
269 switch (fm_info_get_enet_if(i)) {
270 case PHY_INTERFACE_MODE_SGMII:
271 case PHY_INTERFACE_MODE_QSGMII:
272 switch (mdio_mux[i]) {
273 case EMI1_SLOT1:
274 fdt_status_okay_by_alias(fdt, "emi1-slot1");
275 break;
276 case EMI1_SLOT2:
277 fdt_status_okay_by_alias(fdt, "emi1-slot2");
278 break;
279 case EMI1_SLOT3:
280 fdt_status_okay_by_alias(fdt, "emi1-slot3");
281 break;
282 case EMI1_SLOT4:
283 fdt_status_okay_by_alias(fdt, "emi1-slot4");
284 break;
285 default:
286 break;
287 }
288 break;
289 case PHY_INTERFACE_MODE_XGMII:
290 break;
291 default:
292 break;
293 }
294 }
295 }
296
board_eth_init(struct bd_info * bis)297 int board_eth_init(struct bd_info *bis)
298 {
299 #ifdef CONFIG_FMAN_ENET
300 int i, idx, lane, slot, interface;
301 struct memac_mdio_info dtsec_mdio_info;
302 struct memac_mdio_info tgec_mdio_info;
303 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
304 u32 srds_s1;
305
306 srds_s1 = in_be32(&gur->rcwsr[4]) &
307 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
308 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
309
310 /* Initialize the mdio_mux array so we can recognize empty elements */
311 for (i = 0; i < NUM_FM_PORTS; i++)
312 mdio_mux[i] = EMI_NONE;
313
314 dtsec_mdio_info.regs =
315 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
316
317 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
318
319 /* Register the 1G MDIO bus */
320 fm_memac_mdio_init(bis, &dtsec_mdio_info);
321
322 tgec_mdio_info.regs =
323 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
324 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
325
326 /* Register the 10G MDIO bus */
327 fm_memac_mdio_init(bis, &tgec_mdio_info);
328
329 /* Register the muxing front-ends to the MDIO buses */
330 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
331 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
332 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
333 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
334 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
335 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
336 ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
337
338 /* Set the two on-board RGMII PHY address */
339 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
340 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
341
342 switch (srds_s1) {
343 case 0x2555:
344 /* 2.5G SGMII on lane A, MAC 9 */
345 fm_info_set_phy_address(FM1_DTSEC9, 9);
346 break;
347 case 0x4555:
348 case 0x4558:
349 /* QSGMII on lane A, MAC 1/2/5/6 */
350 fm_info_set_phy_address(FM1_DTSEC1,
351 QSGMII_CARD_PORT1_PHY_ADDR_S1);
352 fm_info_set_phy_address(FM1_DTSEC2,
353 QSGMII_CARD_PORT2_PHY_ADDR_S1);
354 fm_info_set_phy_address(FM1_DTSEC5,
355 QSGMII_CARD_PORT3_PHY_ADDR_S1);
356 fm_info_set_phy_address(FM1_DTSEC6,
357 QSGMII_CARD_PORT4_PHY_ADDR_S1);
358 break;
359 case 0x1355:
360 /* SGMII on lane B, MAC 2*/
361 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
362 break;
363 case 0x2355:
364 /* 2.5G SGMII on lane A, MAC 9 */
365 fm_info_set_phy_address(FM1_DTSEC9, 9);
366 /* SGMII on lane B, MAC 2*/
367 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
368 break;
369 case 0x3335:
370 /* SGMII on lane C, MAC 5 */
371 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
372 case 0x3355:
373 case 0x3358:
374 /* SGMII on lane B, MAC 2 */
375 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
376 case 0x3555:
377 case 0x3558:
378 /* SGMII on lane A, MAC 9 */
379 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
380 break;
381 case 0x1455:
382 /* QSGMII on lane B, MAC 1/2/5/6 */
383 fm_info_set_phy_address(FM1_DTSEC1,
384 QSGMII_CARD_PORT1_PHY_ADDR_S2);
385 fm_info_set_phy_address(FM1_DTSEC2,
386 QSGMII_CARD_PORT2_PHY_ADDR_S2);
387 fm_info_set_phy_address(FM1_DTSEC5,
388 QSGMII_CARD_PORT3_PHY_ADDR_S2);
389 fm_info_set_phy_address(FM1_DTSEC6,
390 QSGMII_CARD_PORT4_PHY_ADDR_S2);
391 break;
392 case 0x2455:
393 /* 2.5G SGMII on lane A, MAC 9 */
394 fm_info_set_phy_address(FM1_DTSEC9, 9);
395 /* QSGMII on lane B, MAC 1/2/5/6 */
396 fm_info_set_phy_address(FM1_DTSEC1,
397 QSGMII_CARD_PORT1_PHY_ADDR_S2);
398 fm_info_set_phy_address(FM1_DTSEC2,
399 QSGMII_CARD_PORT2_PHY_ADDR_S2);
400 fm_info_set_phy_address(FM1_DTSEC5,
401 QSGMII_CARD_PORT3_PHY_ADDR_S2);
402 fm_info_set_phy_address(FM1_DTSEC6,
403 QSGMII_CARD_PORT4_PHY_ADDR_S2);
404 break;
405 case 0x2255:
406 /* 2.5G SGMII on lane A, MAC 9 */
407 fm_info_set_phy_address(FM1_DTSEC9, 9);
408 /* 2.5G SGMII on lane B, MAC 2 */
409 fm_info_set_phy_address(FM1_DTSEC2, 2);
410 break;
411 case 0x3333:
412 /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
413 fm_info_set_phy_address(FM1_DTSEC9,
414 SGMII_CARD_PORT1_PHY_ADDR);
415 fm_info_set_phy_address(FM1_DTSEC2,
416 SGMII_CARD_PORT1_PHY_ADDR);
417 fm_info_set_phy_address(FM1_DTSEC5,
418 SGMII_CARD_PORT1_PHY_ADDR);
419 fm_info_set_phy_address(FM1_DTSEC6,
420 SGMII_CARD_PORT1_PHY_ADDR);
421 break;
422 default:
423 printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
424 srds_s1);
425 break;
426 }
427
428 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
429 idx = i - FM1_DTSEC1;
430 interface = fm_info_get_enet_if(i);
431 switch (interface) {
432 case PHY_INTERFACE_MODE_SGMII:
433 case PHY_INTERFACE_MODE_SGMII_2500:
434 case PHY_INTERFACE_MODE_QSGMII:
435 if (interface == PHY_INTERFACE_MODE_SGMII) {
436 lane = serdes_get_first_lane(FSL_SRDS_1,
437 SGMII_FM1_DTSEC1 + idx);
438 } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
439 lane = serdes_get_first_lane(FSL_SRDS_1,
440 SGMII_2500_FM1_DTSEC1 + idx);
441 } else {
442 lane = serdes_get_first_lane(FSL_SRDS_1,
443 QSGMII_FM1_A);
444 }
445
446 if (lane < 0)
447 break;
448
449 slot = lane_to_slot[lane];
450 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
451 idx + 1, slot);
452 if (QIXIS_READ(present2) & (1 << (slot - 1)))
453 fm_disable_port(i);
454
455 switch (slot) {
456 case 1:
457 mdio_mux[i] = EMI1_SLOT1;
458 fm_info_set_mdio(i, mii_dev_for_muxval(
459 mdio_mux[i]));
460 break;
461 case 2:
462 mdio_mux[i] = EMI1_SLOT2;
463 fm_info_set_mdio(i, mii_dev_for_muxval(
464 mdio_mux[i]));
465 break;
466 case 3:
467 mdio_mux[i] = EMI1_SLOT3;
468 fm_info_set_mdio(i, mii_dev_for_muxval(
469 mdio_mux[i]));
470 break;
471 case 4:
472 mdio_mux[i] = EMI1_SLOT4;
473 fm_info_set_mdio(i, mii_dev_for_muxval(
474 mdio_mux[i]));
475 break;
476 default:
477 break;
478 }
479 break;
480 case PHY_INTERFACE_MODE_RGMII:
481 case PHY_INTERFACE_MODE_RGMII_TXID:
482 case PHY_INTERFACE_MODE_RGMII_RXID:
483 case PHY_INTERFACE_MODE_RGMII_ID:
484 if (i == FM1_DTSEC3)
485 mdio_mux[i] = EMI1_RGMII1;
486 else if (i == FM1_DTSEC4)
487 mdio_mux[i] = EMI1_RGMII2;
488 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
489 break;
490 default:
491 break;
492 }
493 }
494
495 cpu_eth_init(bis);
496 #endif /* CONFIG_FMAN_ENET */
497
498 return pci_eth_init(bis);
499 }
500