1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Collabora Ltd.
4 *
5 * Based on board/ccv/xpress/xpress.c:
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
7 */
8
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/global_data.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <fsl_esdhc_imx.h>
18 #include <linux/bitops.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <usb.h>
22 #include <usb/ehci-ci.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
dram_init(void)26 int dram_init(void)
27 {
28 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
29
30 return 0;
31 }
32
33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
36 PAD_CTL_HYS)
37
38 static iomux_v3_cfg_t const uart1_pads[] = {
39 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
41 };
42
43 static iomux_v3_cfg_t const uart5_pads[] = {
44 MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
45 MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
46 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
47 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
48 };
49
setup_iomux_uart(void)50 static void setup_iomux_uart(void)
51 {
52 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
53 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
54 }
55
56 #ifdef CONFIG_NAND_MXS
57
58 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
59
60 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
61
62 #define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
63
64 static iomux_v3_cfg_t const gpmi_pads[] = {
65 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
66 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
67 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
68 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
69 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
70 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
71 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
72 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC,
79 };
80
setup_gpmi_nand(void)81 static void setup_gpmi_nand(void)
82 {
83 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
84
85 setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
86 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
87 }
88
89 #endif /* CONFIG_NAND_MXS */
90
91 #ifdef CONFIG_FEC_MXC
92
93 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
94
95 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
96 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
97 PAD_CTL_SRE_FAST)
98
99 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
100 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
101 PAD_CTL_ODE)
102
103 static iomux_v3_cfg_t const fec1_pads[] = {
104 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
105 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
110 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 };
115
116 static iomux_v3_cfg_t const fec2_pads[] = {
117 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
121 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 };
126
setup_iomux_fec(void)127 static void setup_iomux_fec(void)
128 {
129 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
130 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
131 }
132
setup_fec(void)133 static int setup_fec(void)
134 {
135 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
136 int ret;
137
138 /*
139 * Use 50M anatop loopback REF_CLK1 for ENET1,
140 * clear gpr1[13], set gpr1[17].
141 */
142 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
143 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
144
145 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
146 if (ret)
147 return ret;
148
149 /*
150 * Use 50M anatop loopback REF_CLK2 for ENET2,
151 * clear gpr1[14], set gpr1[18].
152 */
153 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
154 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
155
156 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
157 if (ret)
158 return ret;
159
160 enable_enet_clk(1);
161
162 return 0;
163 }
164
board_phy_config(struct phy_device * phydev)165 int board_phy_config(struct phy_device *phydev)
166 {
167 /*
168 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
169 * 50 MHz RMII clock mode.
170 */
171 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
172
173 if (phydev->drv->config)
174 phydev->drv->config(phydev);
175
176 return 0;
177 }
178 #endif /* CONFIG_FEC_MXC */
179
board_early_init_f(void)180 int board_early_init_f(void)
181 {
182 setup_iomux_uart();
183 #ifdef CONFIG_FEC_MXC
184 setup_iomux_fec();
185 #endif
186
187 return 0;
188 }
189
board_init(void)190 int board_init(void)
191 {
192 /* Address of boot parameters */
193 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
194
195 #ifdef CONFIG_NAND_MXS
196 setup_gpmi_nand();
197 #endif
198
199 #ifdef CONFIG_FEC_MXC
200 setup_fec();
201 #endif
202 return 0;
203 }
204
checkboard(void)205 int checkboard(void)
206 {
207 u32 cpurev = get_cpu_rev();
208
209 printf("Board: PHYTEC phyCORE-i.MX%s\n",
210 get_imx_type((cpurev & 0xFF000) >> 12));
211
212 return 0;
213 }
214