1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
3
4 #include <init.h>
5 #include <net.h>
6 #include <asm/arch/clock.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/mx7-pins.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/global_data.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/io.h>
15 #include <common.h>
16 #include <env.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/setup.h>
19 #include <asm/bootm.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
24 PAD_CTL_HYS)
25
dram_init(void)26 int dram_init(void)
27 {
28 gd->ram_size = PHYS_SDRAM_SIZE;
29
30 return 0;
31 }
32
33 static iomux_v3_cfg_t const wdog_pads[] = {
34 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
35 };
36
37 static iomux_v3_cfg_t const uart1_pads[] = {
38 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 };
41
setup_iomux_uart(void)42 static void setup_iomux_uart(void)
43 {
44 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
45 };
46
setup_fec(void)47 static int setup_fec(void)
48 {
49 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
50 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
51 int ret;
52
53 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
54 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
55 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
56 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
57
58 ret = set_clk_enet(ENET_125MHZ);
59 if (ret)
60 return ret;
61
62 return 0;
63 }
64
board_early_init_f(void)65 int board_early_init_f(void)
66 {
67 setup_iomux_uart();
68 setup_fec();
69 return 0;
70 }
71
board_init(void)72 int board_init(void)
73 {
74 /* address of boot parameters */
75 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
76
77 return 0;
78 }
79
board_late_init(void)80 int board_late_init(void)
81 {
82 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
83
84 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
85
86 set_wdog_reset(wdog);
87
88 /*
89 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
90 * since we use PMIC_PWRON to reset the board.
91 */
92 clrsetbits_le16(&wdog->wcr, 0, 0x10);
93
94 return 0;
95 }
96