README
1Introduction:
2-------------
3The J721e family of SoCs are part of K3 Multicore SoC architecture platform
4targeting automotive applications. They are designed as a low power, high
5performance and highly integrated device architecture, adding significant
6enhancement on processing power, graphics capability, video and imaging
7processing, virtualization and coherent memory support.
8
9The device is partitioned into three functional domains, each containing
10specific processing cores and peripherals:
111. Wake-up (WKUP) domain:
12 - Device Management and Security Controller (DMSC)
132. Microcontroller (MCU) domain:
14 - Dual Core ARM Cortex-R5F processor
153. MAIN domain:
16 - Dual core 64-bit ARM Cortex-A72
17 - 2 x Dual cortex ARM Cortex-R5 subsystem
18 - 2 x C66x Digital signal processor sub system
19 - C71x Digital signal processor sub-system with MMA.
20
21More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
22
23Boot Flow:
24----------
25Boot flow is similar to that of AM65x SoC and extending it with remoteproc
26support. Below is the pictorial representation of boot flow:
27
28+------------------------------------------------------------------------+-----------------------+
29| DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x |
30+------------------------------------------------------------------------+-----------------------+
31| +--------+ | | | |
32| | Reset | | | | |
33| +--------+ | | | |
34| : | | | |
35| +--------+ | +-----------+ | | |
36| | *ROM* |----------|-->| Reset rls | | | |
37| +--------+ | +-----------+ | | |
38| | | | : | | |
39| | ROM | | : | | |
40| |services| | : | | |
41| | | | +-------------+ | | |
42| | | | | *R5 ROM* | | | |
43| | | | +-------------+ | | |
44| | |<---------|---|Load and auth| | | |
45| | | | | tiboot3.bin | | | |
46| | | | +-------------+ | | |
47| | | | : | | |
48| | | | : | | |
49| | | | : | | |
50| | | | +-------------+ | | |
51| | | | | *R5 SPL* | | | |
52| | | | +-------------+ | | |
53| | | | | Load | | | |
54| | | | | sysfw.itb | | | |
55| | Start | | +-------------+ | | |
56| | System |<---------|---| Start | | | |
57| |Firmware| | | SYSFW | | | |
58| +--------+ | +-------------+ | | |
59| : | | | | | |
60| +---------+ | | Load | | | |
61| | *SYSFW* | | | system | | | |
62| +---------+ | | Config data | | | |
63| | |<--------|---| | | | |
64| | | | +-------------+ | | |
65| | | | | DDR | | | |
66| | | | | config | | | |
67| | | | +-------------+ | | |
68| | | | | Load | | | |
69| | | | | tispl.bin | | | |
70| | | | +-------------+ | | |
71| | | | | Load R5 | | | |
72| | | | | firmware | | | |
73| | | | +-------------+ | | |
74| | |<--------|---| Start A72 | | | |
75| | | | | and jump to | | | |
76| | | | | next image | | | |
77| | | | +-------------+ | | |
78| | | | | +-----------+ | |
79| | |---------|-----------------------|---->| Reset rls | | |
80| | | | | +-----------+ | |
81| | DMSC | | | : | |
82| |Services | | | +-----------+ | |
83| | |<--------|-----------------------|---->|*ATF/OPTEE*| | |
84| | | | | +-----------+ | |
85| | | | | : | |
86| | | | | +-----------+ | |
87| | |<--------|-----------------------|---->| *A72 SPL* | | |
88| | | | | +-----------+ | |
89| | | | | | Load | | |
90| | | | | | u-boot.img| | |
91| | | | | +-----------+ | |
92| | | | | : | |
93| | | | | +-----------+ | |
94| | |<--------|-----------------------|---->| *U-Boot* | | |
95| | | | | +-----------+ | |
96| | | | | | prompt | | |
97| | | | | +-----------+ | |
98| | | | | | Load R5 | | |
99| | | | | | Firmware | | |
100| | | | | +-----------+ | |
101| | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
102| | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
103| | | | | | Load C6 | | +-----------+ |
104| | | | | | Firmware | | |
105| | | | | +-----------+ | |
106| | |<--------|-----------------------|-----| Start C6 | | +-----------+ |
107| | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | |
108| | | | | | Load C7 | | +-----------+ |
109| | | | | | Firmware | | |
110| | | | | +-----------+ | |
111| | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
112| | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
113| +---------+ | | | +-----------+ |
114| | | | |
115+------------------------------------------------------------------------+-----------------------+
116
117- Here DMSC acts as master and provides all the critical services. R5/A72
118requests DMSC to get these services done as shown in the above diagram.
119
120Sources:
121--------
1221. SYSFW:
123 Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git
124 Branch: master
125
1262. ATF:
127 Tree: https://github.com/ARM-software/arm-trusted-firmware.git
128 Branch: master
129
1303. OPTEE:
131 Tree: https://github.com/OP-TEE/optee_os.git
132 Branch: master
133
1344. U-Boot:
135 Tree: https://source.denx.de/u-boot/u-boot
136 Branch: master
137
138Build procedure:
139----------------
1401. SYSFW:
141$ make CROSS_COMPILE=arm-linux-gnueabihf-
142
1432. ATF:
144$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
145
1463. OPTEE:
147$ make PLATFORM=k3-j721e CFG_ARM64_core=y
148
1494. U-Boot:
150
1514.1. R5:
152$ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
153$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
154
1554.2. A72:
156$ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
157$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
158
159Target Images
160--------------
161Copy the below images to an SD card and boot:
162- sysfw.itb from step 1
163- tiboot3.bin from step 4.1
164- tispl.bin, u-boot.img from 4.2
165
166Image formats:
167--------------
168
169- tiboot3.bin:
170 +-----------------------+
171 | X.509 |
172 | Certificate |
173 | +-------------------+ |
174 | | | |
175 | | R5 | |
176 | | u-boot-spl.bin | |
177 | | | |
178 | +-------------------+ |
179 | | | |
180 | | FIT header | |
181 | | +---------------+ | |
182 | | | | | |
183 | | | DTB 1...N | | |
184 | | +---------------+ | |
185 | +-------------------+ |
186 +-----------------------+
187
188- tispl.bin
189 +-----------------------+
190 | |
191 | FIT HEADER |
192 | +-------------------+ |
193 | | | |
194 | | A72 ATF | |
195 | +-------------------+ |
196 | | | |
197 | | A72 OPTEE | |
198 | +-------------------+ |
199 | | | |
200 | | A72 SPL | |
201 | +-------------------+ |
202 | | | |
203 | | SPL DTB 1...N | |
204 | +-------------------+ |
205 +-----------------------+
206
207- sysfw.itb
208 +-----------------------+
209 | |
210 | FIT HEADER |
211 | +-------------------+ |
212 | | | |
213 | | sysfw.bin | |
214 | +-------------------+ |
215 | | | |
216 | | board config | |
217 | +-------------------+ |
218 | | | |
219 | | PM config | |
220 | +-------------------+ |
221 | | | |
222 | | RM config | |
223 | +-------------------+ |
224 | | | |
225 | | Secure config | |
226 | +-------------------+ |
227 +-----------------------+
228
229OSPI:
230-----
231ROM supports booting from OSPI from offset 0x0.
232
233Flashing images to OSPI:
234
235Below commands can be used to download tiboot3.bin, tispl.bin, u-boot.img,
236and sysfw.itb over tftp and then flash those to OSPI at their respective
237addresses.
238
239=> sf probe
240=> tftp ${loadaddr} tiboot3.bin
241=> sf update $loadaddr 0x0 $filesize
242=> tftp ${loadaddr} tispl.bin
243=> sf update $loadaddr 0x80000 $filesize
244=> tftp ${loadaddr} u-boot.img
245=> sf update $loadaddr 0x280000 $filesize
246=> tftp ${loadaddr} sysfw.itb
247=> sf update $loadaddr 0x6C0000 $filesize
248
249Flash layout for OSPI:
250
251 0x0 +----------------------------+
252 | ospi.tiboot3(512K) |
253 | |
254 0x80000 +----------------------------+
255 | ospi.tispl(2M) |
256 | |
257 0x280000 +----------------------------+
258 | ospi.u-boot(4M) |
259 | |
260 0x680000 +----------------------------+
261 | ospi.env(128K) |
262 | |
263 0x6A0000 +----------------------------+
264 | ospi.env.backup (128K) |
265 | |
266 0x6C0000 +----------------------------+
267 | ospi.sysfw(1M) |
268 | |
269 0x7C0000 +----------------------------+
270 | padding (256k) |
271 0x800000 +----------------------------+
272 | ospi.rootfs(UBIFS) |
273 | |
274 +----------------------------+
275