1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Renesas RCar Gen3 CPG MSSR driver 4 * 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on the following driver from Linux kernel: 8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 9 * 10 * Copyright (C) 2016 Glider bvba 11 */ 12 13 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__ 14 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__ 15 16 #include <linux/bitops.h> 17 18 enum clk_reg_layout { 19 CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, 20 }; 21 22 struct cpg_mssr_info { 23 const struct cpg_core_clk *core_clk; 24 unsigned int core_clk_size; 25 enum clk_reg_layout reg_layout; 26 const struct mssr_mod_clk *mod_clk; 27 unsigned int mod_clk_size; 28 const struct mstp_stop_table *mstp_table; 29 unsigned int mstp_table_size; 30 const char *reset_node; 31 unsigned int reset_modemr_offset; 32 const char *extalr_node; 33 const char *extal_usb_node; 34 unsigned int mod_clk_base; 35 unsigned int clk_extal_id; 36 unsigned int clk_extalr_id; 37 unsigned int clk_extal_usb_id; 38 unsigned int pll0_div; 39 const void *(*get_pll_config)(const u32 cpg_mode); 40 const u16 *status_regs; 41 const u16 *control_regs; 42 const u16 *reset_regs; 43 const u16 *reset_clear_regs; 44 }; 45 46 /* 47 * Definitions of CPG Core Clocks 48 * 49 * These include: 50 * - Clock outputs exported to DT 51 * - External input clocks 52 * - Internal CPG clocks 53 */ 54 struct cpg_core_clk { 55 /* Common */ 56 const char *name; 57 unsigned int id; 58 unsigned int type; 59 /* Depending on type */ 60 unsigned int parent; /* Core Clocks only */ 61 unsigned int div; 62 unsigned int mult; 63 unsigned int offset; 64 }; 65 66 enum clk_types { 67 /* Generic */ 68 CLK_TYPE_IN, /* External Clock Input */ 69 CLK_TYPE_FF, /* Fixed Factor Clock */ 70 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ 71 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ 72 CLK_TYPE_FR, /* Fixed Rate Clock */ 73 74 /* Custom definitions start here */ 75 CLK_TYPE_CUSTOM, 76 }; 77 78 #define DEF_TYPE(_name, _id, _type...) \ 79 { .name = _name, .id = _id, .type = _type } 80 #define DEF_BASE(_name, _id, _type, _parent...) \ 81 DEF_TYPE(_name, _id, _type, .parent = _parent) 82 83 #define DEF_INPUT(_name, _id) \ 84 DEF_TYPE(_name, _id, CLK_TYPE_IN) 85 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ 86 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 87 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ 88 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) 89 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ 90 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) 91 #define DEF_RATE(_name, _id, _rate) \ 92 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate) 93 94 /* 95 * Definitions of Module Clocks 96 */ 97 struct mssr_mod_clk { 98 const char *name; 99 unsigned int id; 100 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ 101 }; 102 103 /* Convert from sparse base-100 to packed index space */ 104 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) 105 106 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) 107 108 #define DEF_MOD(_name, _mod, _parent...) \ 109 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } 110 111 struct mstp_stop_table { 112 u32 sdis; 113 u32 sen; 114 u32 rdis; 115 u32 ren; 116 }; 117 118 #define TSTR0 0x04 119 #define TSTR0_STR0 BIT(0) 120 121 bool renesas_clk_is_mod(struct clk *clk); 122 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info, 123 const struct mssr_mod_clk **mssr); 124 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info, 125 const struct cpg_core_clk **core); 126 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info, 127 struct clk *parent); 128 int renesas_clk_endisable(struct clk *clk, void __iomem *base, 129 struct cpg_mssr_info *info, bool enable); 130 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info); 131 132 /* 133 * Module Standby and Software Reset register offets. 134 * 135 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 136 * R-Car Gen2, R-Car Gen3, and RZ/G1. 137 * These are NOT valid for R-Car Gen1 and RZ/A1! 138 */ 139 140 /* 141 * Module Stop Status Register offsets 142 */ 143 144 static const u16 mstpsr[] = { 145 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 146 0x9A0, 0x9A4, 0x9A8, 0x9AC, 147 }; 148 149 /* 150 * System Module Stop Control Register offsets 151 */ 152 153 static const u16 smstpcr[] = { 154 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 155 0x990, 0x994, 0x998, 0x99C, 156 }; 157 158 /* 159 * Software Reset Register offsets 160 */ 161 162 static const u16 srcr[] = { 163 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 164 0x920, 0x924, 0x928, 0x92C, 165 }; 166 167 /* Realtime Module Stop Control Register offsets */ 168 #define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10) 169 170 /* Modem Module Stop Control Register offsets (r8a73a4) */ 171 #define MMSTPCR(i) (smstpcr[i] + 0x20) 172 173 /* Software Reset Clearing Register offsets */ 174 175 static const u16 srstclr[] = { 176 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, 177 0x960, 0x964, 0x968, 0x96C, 178 }; 179 180 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */ 181