1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #include <linux/stringify.h> 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_FSL_SATA_V2 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 25 26 #ifdef CONFIG_RAMBOOT_PBL 27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 28 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_PAD_TO 0x40000 31 #define CONFIG_SPL_MAX_SIZE 0x28000 32 #define RESET_VECTOR_OFFSET 0x27FFC 33 #define BOOT_PAGE_OFFSET 0x27000 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #endif 39 40 #ifdef CONFIG_MTD_RAW_NAND 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 46 #endif 47 48 #ifdef CONFIG_SPIFLASH 49 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 50 #define CONFIG_SPL_SPI_FLASH_MINIMAL 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 55 #ifndef CONFIG_SPL_BUILD 56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 57 #endif 58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 59 #endif 60 61 #ifdef CONFIG_SDCARD 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 63 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 65 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 66 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 67 #ifndef CONFIG_SPL_BUILD 68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #endif 70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 71 #endif 72 73 #endif /* CONFIG_RAMBOOT_PBL */ 74 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 77 /* Set 1M boot space */ 78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 82 #endif 83 84 #ifndef CONFIG_RESET_VECTOR_ADDRESS 85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 86 #endif 87 88 /* 89 * These can be toggled for performance analysis, otherwise use default. 90 */ 91 #define CONFIG_SYS_CACHE_STASHING 92 #define CONFIG_BTB /* toggle branch predition */ 93 #define CONFIG_DDR_ECC 94 #ifdef CONFIG_DDR_ECC 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 97 #endif 98 99 #ifndef __ASSEMBLY__ 100 unsigned long get_board_sys_clk(void); 101 unsigned long get_board_ddr_clk(void); 102 #endif 103 104 #define CONFIG_SYS_CLK_FREQ 66660000 105 #define CONFIG_DDR_CLK_FREQ 133330000 106 107 /* 108 * Config the L3 Cache as L3 SRAM 109 */ 110 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 111 #define CONFIG_SYS_L3_SIZE (512 << 10) 112 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 113 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 114 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 115 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 116 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 117 118 #define CONFIG_SYS_DCSRBAR 0xf0000000 119 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 120 121 /* EEPROM */ 122 #define CONFIG_ID_EEPROM 123 #define CONFIG_SYS_I2C_EEPROM_NXID 124 #define CONFIG_SYS_EEPROM_BUS_NUM 0 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_VERY_BIG_RAM 132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 135 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 136 #define CONFIG_DDR_SPD 137 #define CONFIG_SYS_SPD_BUS_NUM 0 138 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 139 #define SPD_EEPROM_ADDRESS1 0x51 140 #define SPD_EEPROM_ADDRESS2 0x52 141 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 142 #define CTRL_INTLV_PREFERED cacheline 143 144 /* 145 * IFC Definitions 146 */ 147 #define CONFIG_SYS_FLASH_BASE 0xe8000000 148 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 149 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 150 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 151 CSPR_PORT_SIZE_16 | \ 152 CSPR_MSEL_NOR | \ 153 CSPR_V) 154 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 155 156 /* NOR Flash Timing Params */ 157 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 158 159 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 160 FTIM0_NOR_TEADC(0x5) | \ 161 FTIM0_NOR_TEAHC(0x5)) 162 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 163 FTIM1_NOR_TRAD_NOR(0x1A) |\ 164 FTIM1_NOR_TSEQRAD_NOR(0x13)) 165 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 166 FTIM2_NOR_TCH(0x4) | \ 167 FTIM2_NOR_TWPH(0x0E) | \ 168 FTIM2_NOR_TWP(0x1c)) 169 #define CONFIG_SYS_NOR_FTIM3 0x0 170 171 #define CONFIG_SYS_FLASH_QUIET_TEST 172 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 173 174 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 175 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 178 #define CONFIG_SYS_FLASH_EMPTY_INFO 179 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 180 181 /* CPLD on IFC */ 182 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 183 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 184 #define CONFIG_SYS_CSPR2_EXT (0xf) 185 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 186 | CSPR_PORT_SIZE_8 \ 187 | CSPR_MSEL_GPCM \ 188 | CSPR_V) 189 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 190 #define CONFIG_SYS_CSOR2 0x0 191 192 /* CPLD Timing parameters for IFC CS2 */ 193 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 194 FTIM0_GPCM_TEADC(0x0e) | \ 195 FTIM0_GPCM_TEAHC(0x0e)) 196 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 197 FTIM1_GPCM_TRAD(0x1f)) 198 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 199 FTIM2_GPCM_TCH(0x8) | \ 200 FTIM2_GPCM_TWP(0x1f)) 201 #define CONFIG_SYS_CS2_FTIM3 0x0 202 203 /* NAND Flash on IFC */ 204 #define CONFIG_NAND_FSL_IFC 205 #define CONFIG_SYS_NAND_BASE 0xff800000 206 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 207 208 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 209 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 210 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 211 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 212 | CSPR_V) 213 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 214 215 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 216 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 217 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 218 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 219 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 220 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 221 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 222 223 #define CONFIG_SYS_NAND_ONFI_DETECTION 224 225 /* ONFI NAND Flash mode0 Timing Params */ 226 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 227 FTIM0_NAND_TWP(0x18) | \ 228 FTIM0_NAND_TWCHT(0x07) | \ 229 FTIM0_NAND_TWH(0x0a)) 230 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 231 FTIM1_NAND_TWBE(0x39) | \ 232 FTIM1_NAND_TRR(0x0e) | \ 233 FTIM1_NAND_TRP(0x18)) 234 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 235 FTIM2_NAND_TREH(0x0a) | \ 236 FTIM2_NAND_TWHRE(0x1e)) 237 #define CONFIG_SYS_NAND_FTIM3 0x0 238 239 #define CONFIG_SYS_NAND_DDR_LAW 11 240 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 241 #define CONFIG_SYS_MAX_NAND_DEVICE 1 242 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 243 244 #if defined(CONFIG_MTD_RAW_NAND) 245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 247 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 248 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 249 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 250 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 251 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 252 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 253 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 254 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 255 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 256 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 257 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 258 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 259 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 260 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 261 #else 262 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 263 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 264 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 265 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 266 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 267 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 268 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 269 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 270 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 271 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 272 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 273 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 274 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 275 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 276 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 277 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 278 #endif 279 280 #if defined(CONFIG_RAMBOOT_PBL) 281 #define CONFIG_SYS_RAMBOOT 282 #endif 283 284 #ifdef CONFIG_SPL_BUILD 285 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 286 #else 287 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 288 #endif 289 290 #define CONFIG_HWCONFIG 291 292 /* define to use L1 as initial stack */ 293 #define CONFIG_L1_INIT_RAM 294 #define CONFIG_SYS_INIT_RAM_LOCK 295 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 298 /* The assembler doesn't like typecast */ 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 300 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 301 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 303 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 304 GENERATED_GBL_DATA_SIZE) 305 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 306 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 307 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 308 309 /* 310 * Serial Port 311 */ 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 315 #define CONFIG_SYS_BAUDRATE_TABLE \ 316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 317 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 319 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 320 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 321 322 /* 323 * I2C 324 */ 325 #if !CONFIG_IS_ENABLED(DM_I2C) 326 #define CONFIG_SYS_I2C 327 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 328 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 329 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 330 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 331 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 332 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 333 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 334 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 335 #define CONFIG_SYS_FSL_I2C_SPEED 100000 336 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 337 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 338 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 339 #else 340 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 341 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 342 #endif 343 344 #define CONFIG_SYS_I2C_FSL 345 346 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 347 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 348 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 349 #define I2C_MUX_CH_DEFAULT 0x8 350 351 #define I2C_MUX_CH_VOL_MONITOR 0xa 352 353 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 354 #ifndef CONFIG_SPL_BUILD 355 #define CONFIG_VID 356 #endif 357 #define CONFIG_VOL_MONITOR_IR36021_SET 358 #define CONFIG_VOL_MONITOR_IR36021_READ 359 /* The lowest and highest voltage allowed for T208xRDB */ 360 #define VDD_MV_MIN 819 361 #define VDD_MV_MAX 1212 362 363 /* 364 * RapidIO 365 */ 366 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 367 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 368 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 369 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 370 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 371 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 372 /* 373 * for slave u-boot IMAGE instored in master memory space, 374 * PHYS must be aligned based on the SIZE 375 */ 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 378 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 379 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 380 /* 381 * for slave UCODE and ENV instored in master memory space, 382 * PHYS must be aligned based on the SIZE 383 */ 384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 385 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 386 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 387 388 /* slave core release by master*/ 389 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 390 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 391 392 /* 393 * SRIO_PCIE_BOOT - SLAVE 394 */ 395 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 396 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 397 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 398 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 399 #endif 400 401 /* 402 * eSPI - Enhanced SPI 403 */ 404 405 /* 406 * General PCI 407 * Memory space is mapped 1-1, but I/O space must start from 0. 408 */ 409 #define CONFIG_PCIE1 /* PCIE controller 1 */ 410 #define CONFIG_PCIE2 /* PCIE controller 2 */ 411 #define CONFIG_PCIE3 /* PCIE controller 3 */ 412 #define CONFIG_PCIE4 /* PCIE controller 4 */ 413 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 414 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 415 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 416 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 417 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 419 420 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 421 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 424 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 425 426 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 427 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 428 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 429 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 430 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 431 432 /* controller 4, Base address 203000 */ 433 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 434 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 435 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 436 437 #ifdef CONFIG_PCI 438 #if !defined(CONFIG_DM_PCI) 439 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 441 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 443 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 446 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 447 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 450 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 451 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 452 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 454 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 455 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 456 #define CONFIG_PCI_INDIRECT_BRIDGE 457 #endif 458 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 459 #endif 460 461 /* Qman/Bman */ 462 #ifndef CONFIG_NOBQFMAN 463 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 464 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 465 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 466 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 467 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 468 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 469 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 470 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 471 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 472 CONFIG_SYS_BMAN_CENA_SIZE) 473 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 474 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 475 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 476 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 477 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 478 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 479 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 480 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 481 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 482 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 483 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 484 CONFIG_SYS_QMAN_CENA_SIZE) 485 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 486 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 487 488 #define CONFIG_SYS_DPAA_FMAN 489 #define CONFIG_SYS_DPAA_PME 490 #define CONFIG_SYS_PMAN 491 #define CONFIG_SYS_DPAA_DCE 492 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 493 #define CONFIG_SYS_INTERLAKEN 494 495 /* Default address of microcode for the Linux Fman driver */ 496 #if defined(CONFIG_SPIFLASH) 497 /* 498 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 499 * env, so we got 0x110000. 500 */ 501 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 502 #define CONFIG_CORTINA_FW_ADDR 0x120000 503 504 #elif defined(CONFIG_SDCARD) 505 /* 506 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 507 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 508 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 509 */ 510 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 511 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 512 513 #elif defined(CONFIG_MTD_RAW_NAND) 514 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 515 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 516 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 517 /* 518 * Slave has no ucode locally, it can fetch this from remote. When implementing 519 * in two corenet boards, slave's ucode could be stored in master's memory 520 * space, the address can be mapped from slave TLB->slave LAW-> 521 * slave SRIO or PCIE outbound window->master inbound window-> 522 * master LAW->the ucode address in master's memory space. 523 */ 524 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 525 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 526 #else 527 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 528 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 529 #endif 530 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 531 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 532 #endif /* CONFIG_NOBQFMAN */ 533 534 #ifdef CONFIG_SYS_DPAA_FMAN 535 #define CONFIG_CORTINA_FW_LENGTH 0x40000 536 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 537 #define RGMII_PHY2_ADDR 0x02 538 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 539 #define CORTINA_PHY_ADDR2 0x0d 540 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */ 541 #define FM1_10GEC3_PHY_ADDR 0x00 542 #define FM1_10GEC4_PHY_ADDR 0x01 543 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */ 544 #define AQR113C_PHY_ADDR1 0x00 545 #define AQR113C_PHY_ADDR2 0x08 546 #endif 547 548 #ifdef CONFIG_FMAN_ENET 549 #define CONFIG_ETHPRIME "FM1@DTSEC3" 550 #endif 551 552 /* 553 * SATA 554 */ 555 #ifdef CONFIG_FSL_SATA_V2 556 #define CONFIG_SYS_SATA_MAX_DEVICE 2 557 #define CONFIG_SATA1 558 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 559 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 560 #define CONFIG_SATA2 561 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 562 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 563 #define CONFIG_LBA48 564 #endif 565 566 /* 567 * USB 568 */ 569 #ifdef CONFIG_USB_EHCI_HCD 570 #define CONFIG_USB_EHCI_FSL 571 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 572 #define CONFIG_HAS_FSL_DR_USB 573 #endif 574 575 /* 576 * SDHC 577 */ 578 #ifdef CONFIG_MMC 579 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 580 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 581 #endif 582 583 /* 584 * Dynamic MTD Partition support with mtdparts 585 */ 586 587 /* 588 * Environment 589 */ 590 591 /* 592 * Miscellaneous configurable options 593 */ 594 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 595 596 /* 597 * For booting Linux, the board info and command line data 598 * have to be in the first 64 MB of memory, since this is 599 * the maximum mapped by the Linux kernel during initialization. 600 */ 601 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 602 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 603 604 #ifdef CONFIG_CMD_KGDB 605 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 606 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 607 #endif 608 609 /* 610 * Environment Configuration 611 */ 612 #define CONFIG_ROOTPATH "/opt/nfsroot" 613 #define CONFIG_BOOTFILE "uImage" 614 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 615 616 /* default location for tftp and bootm */ 617 #define CONFIG_LOADADDR 1000000 618 #define __USB_PHY_TYPE utmi 619 620 #define CONFIG_EXTRA_ENV_SETTINGS \ 621 "hwconfig=fsl_ddr:" \ 622 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 623 "bank_intlv=auto;" \ 624 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 625 "netdev=eth0\0" \ 626 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 627 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 628 "tftpflash=tftpboot $loadaddr $uboot && " \ 629 "protect off $ubootaddr +$filesize && " \ 630 "erase $ubootaddr +$filesize && " \ 631 "cp.b $loadaddr $ubootaddr $filesize && " \ 632 "protect on $ubootaddr +$filesize && " \ 633 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 634 "consoledev=ttyS0\0" \ 635 "ramdiskaddr=2000000\0" \ 636 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 637 "fdtaddr=1e00000\0" \ 638 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 639 "bdev=sda3\0" 640 641 /* 642 * For emulation this causes u-boot to jump to the start of the 643 * proof point app code automatically 644 */ 645 #define CONFIG_PROOF_POINTS \ 646 "setenv bootargs root=/dev/$bdev rw " \ 647 "console=$consoledev,$baudrate $othbootargs;" \ 648 "cpu 1 release 0x29000000 - - -;" \ 649 "cpu 2 release 0x29000000 - - -;" \ 650 "cpu 3 release 0x29000000 - - -;" \ 651 "cpu 4 release 0x29000000 - - -;" \ 652 "cpu 5 release 0x29000000 - - -;" \ 653 "cpu 6 release 0x29000000 - - -;" \ 654 "cpu 7 release 0x29000000 - - -;" \ 655 "go 0x29000000" 656 657 #define CONFIG_HVBOOT \ 658 "setenv bootargs config-addr=0x60000000; " \ 659 "bootm 0x01000000 - 0x00f00000" 660 661 #define CONFIG_ALU \ 662 "setenv bootargs root=/dev/$bdev rw " \ 663 "console=$consoledev,$baudrate $othbootargs;" \ 664 "cpu 1 release 0x01000000 - - -;" \ 665 "cpu 2 release 0x01000000 - - -;" \ 666 "cpu 3 release 0x01000000 - - -;" \ 667 "cpu 4 release 0x01000000 - - -;" \ 668 "cpu 5 release 0x01000000 - - -;" \ 669 "cpu 6 release 0x01000000 - - -;" \ 670 "cpu 7 release 0x01000000 - - -;" \ 671 "go 0x01000000" 672 673 #define CONFIG_LINUX \ 674 "setenv bootargs root=/dev/ram rw " \ 675 "console=$consoledev,$baudrate $othbootargs;" \ 676 "setenv ramdiskaddr 0x02000000;" \ 677 "setenv fdtaddr 0x00c00000;" \ 678 "setenv loadaddr 0x1000000;" \ 679 "bootm $loadaddr $ramdiskaddr $fdtaddr" 680 681 #define CONFIG_HDBOOT \ 682 "setenv bootargs root=/dev/$bdev rw " \ 683 "console=$consoledev,$baudrate $othbootargs;" \ 684 "tftp $loadaddr $bootfile;" \ 685 "tftp $fdtaddr $fdtfile;" \ 686 "bootm $loadaddr - $fdtaddr" 687 688 #define CONFIG_NFSBOOTCOMMAND \ 689 "setenv bootargs root=/dev/nfs rw " \ 690 "nfsroot=$serverip:$rootpath " \ 691 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 692 "console=$consoledev,$baudrate $othbootargs;" \ 693 "tftp $loadaddr $bootfile;" \ 694 "tftp $fdtaddr $fdtfile;" \ 695 "bootm $loadaddr - $fdtaddr" 696 697 #define CONFIG_RAMBOOTCOMMAND \ 698 "setenv bootargs root=/dev/ram rw " \ 699 "console=$consoledev,$baudrate $othbootargs;" \ 700 "tftp $ramdiskaddr $ramdiskfile;" \ 701 "tftp $loadaddr $bootfile;" \ 702 "tftp $fdtaddr $fdtfile;" \ 703 "bootm $loadaddr $ramdiskaddr $fdtaddr" 704 705 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 706 707 #include <asm/fsl_secure_boot.h> 708 709 #endif /* __T2080RDB_H */ 710