1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx AXI Bridge for PCI Express Driver
4 *
5 * Copyright (C) 2016 Imagination Technologies
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <pci.h>
11 #include <asm/global_data.h>
12 #include <linux/bitops.h>
13
14 #include <asm/io.h>
15
16 /**
17 * struct xilinx_pcie - Xilinx PCIe controller state
18 * @cfg_base: The base address of memory mapped configuration space
19 */
20 struct xilinx_pcie {
21 void *cfg_base;
22 };
23
24 /* Register definitions */
25 #define XILINX_PCIE_REG_PSCR 0x144
26 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
27
28 /**
29 * pcie_xilinx_link_up() - Check whether the PCIe link is up
30 * @pcie: Pointer to the PCI controller state
31 *
32 * Checks whether the PCIe link for the given device is up or down.
33 *
34 * Return: true if the link is up, else false
35 */
pcie_xilinx_link_up(struct xilinx_pcie * pcie)36 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
37 {
38 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
39
40 return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
41 }
42
43 /**
44 * pcie_xilinx_config_address() - Calculate the address of a config access
45 * @udev: Pointer to the PCI bus
46 * @bdf: Identifies the PCIe device to access
47 * @offset: The offset into the device's configuration space
48 * @paddress: Pointer to the pointer to write the calculates address to
49 *
50 * Calculates the address that should be accessed to perform a PCIe
51 * configuration space access for a given device identified by the PCIe
52 * controller device @pcie and the bus, device & function numbers in @bdf. If
53 * access to the device is not valid then the function will return an error
54 * code. Otherwise the address to access will be written to the pointer pointed
55 * to by @paddress.
56 *
57 * Return: 0 on success, else -ENODEV
58 */
pcie_xilinx_config_address(const struct udevice * udev,pci_dev_t bdf,uint offset,void ** paddress)59 static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
60 uint offset, void **paddress)
61 {
62 struct xilinx_pcie *pcie = dev_get_priv(udev);
63 unsigned int bus = PCI_BUS(bdf);
64 unsigned int dev = PCI_DEV(bdf);
65 unsigned int func = PCI_FUNC(bdf);
66 void *addr;
67
68 if ((bus > 0) && !pcie_xilinx_link_up(pcie))
69 return -ENODEV;
70
71 /*
72 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
73 * limited to a single device each.
74 */
75 if ((bus < 2) && (dev > 0))
76 return -ENODEV;
77
78 addr = pcie->cfg_base;
79 addr += bus << 20;
80 addr += dev << 15;
81 addr += func << 12;
82 addr += offset;
83 *paddress = addr;
84
85 return 0;
86 }
87
88 /**
89 * pcie_xilinx_read_config() - Read from configuration space
90 * @bus: Pointer to the PCI bus
91 * @bdf: Identifies the PCIe device to access
92 * @offset: The offset into the device's configuration space
93 * @valuep: A pointer at which to store the read value
94 * @size: Indicates the size of access to perform
95 *
96 * Read a value of size @size from offset @offset within the configuration
97 * space of the device identified by the bus, device & function numbers in @bdf
98 * on the PCI bus @bus.
99 *
100 * Return: 0 on success, else -ENODEV or -EINVAL
101 */
pcie_xilinx_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)102 static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
103 uint offset, ulong *valuep,
104 enum pci_size_t size)
105 {
106 return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
107 bdf, offset, valuep, size);
108 }
109
110 /**
111 * pcie_xilinx_write_config() - Write to configuration space
112 * @bus: Pointer to the PCI bus
113 * @bdf: Identifies the PCIe device to access
114 * @offset: The offset into the device's configuration space
115 * @value: The value to write
116 * @size: Indicates the size of access to perform
117 *
118 * Write the value @value of size @size from offset @offset within the
119 * configuration space of the device identified by the bus, device & function
120 * numbers in @bdf on the PCI bus @bus.
121 *
122 * Return: 0 on success, else -ENODEV or -EINVAL
123 */
pcie_xilinx_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)124 static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
125 uint offset, ulong value,
126 enum pci_size_t size)
127 {
128 return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
129 bdf, offset, value, size);
130 }
131
132 /**
133 * pcie_xilinx_of_to_plat() - Translate from DT to device state
134 * @dev: A pointer to the device being operated on
135 *
136 * Translate relevant data from the device tree pertaining to device @dev into
137 * state that the driver will later make use of. This state is stored in the
138 * device's private data structure.
139 *
140 * Return: 0 on success, else -EINVAL
141 */
pcie_xilinx_of_to_plat(struct udevice * dev)142 static int pcie_xilinx_of_to_plat(struct udevice *dev)
143 {
144 struct xilinx_pcie *pcie = dev_get_priv(dev);
145 struct fdt_resource reg_res;
146 DECLARE_GLOBAL_DATA_PTR;
147 int err;
148
149 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
150 0, ®_res);
151 if (err < 0) {
152 pr_err("\"reg\" resource not found\n");
153 return err;
154 }
155
156 pcie->cfg_base = map_physmem(reg_res.start,
157 fdt_resource_size(®_res),
158 MAP_NOCACHE);
159
160 return 0;
161 }
162
163 static const struct dm_pci_ops pcie_xilinx_ops = {
164 .read_config = pcie_xilinx_read_config,
165 .write_config = pcie_xilinx_write_config,
166 };
167
168 static const struct udevice_id pcie_xilinx_ids[] = {
169 { .compatible = "xlnx,axi-pcie-host-1.00.a" },
170 { }
171 };
172
173 U_BOOT_DRIVER(pcie_xilinx) = {
174 .name = "pcie_xilinx",
175 .id = UCLASS_PCI,
176 .of_match = pcie_xilinx_ids,
177 .ops = &pcie_xilinx_ops,
178 .of_to_plat = pcie_xilinx_of_to_plat,
179 .priv_auto = sizeof(struct xilinx_pcie),
180 };
181