1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License version 2 as published
6  * by the Free Software Foundation.
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #include <linux/stringify.h>
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_E300		1	/* E300 family */
18 
19 /*
20  * System IO Config
21  */
22 #define CONFIG_SYS_SICRL		0x00000000
23 
24 /*
25  * DDR Setup
26  */
27 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
28 
29 #undef CONFIG_SPD_EEPROM
30 #if defined(CONFIG_SPD_EEPROM)
31 /* Determine DDR configuration from I2C interface
32  */
33 #define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
34 #else
35 /* Manually set up DDR parameters
36  */
37 #define CONFIG_SYS_DDR_SIZE	64	/* MB */
38 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
39 				| CSCONFIG_ROW_BIT_13 \
40 				| CSCONFIG_COL_BIT_9)
41 				/* 0x80010101 */
42 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
43 				| (0 << TIMING_CFG0_WRT_SHIFT) \
44 				| (0 << TIMING_CFG0_RRT_SHIFT) \
45 				| (0 << TIMING_CFG0_WWT_SHIFT) \
46 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
47 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
48 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
49 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
50 				/* 0x00220802 */
51 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
52 				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
53 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
54 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
55 				| (3 << TIMING_CFG1_REFREC_SHIFT) \
56 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
57 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
58 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
59 				/* 0x26253222 */
60 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
61 				| (31 << TIMING_CFG2_CPO_SHIFT) \
62 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
63 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
64 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
65 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
66 				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
67 				/* 0x1f9048c7 */
68 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
69 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
70 				/* 0x02000000 */
71 #define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
72 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
73 				/* 0x44480232 */
74 #define CONFIG_SYS_DDR_MODE2	0x8000c000
75 #define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
76 				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
77 				/* 0x03200064 */
78 #define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
79 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
80 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
81 				| SDRAM_CFG_32_BE)
82 				/* 0x43080000 */
83 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
84 #endif
85 
86 /*
87  * Memory test
88  */
89 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
90 
91 /*
92  * The reserved memory
93  */
94 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
95 
96 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
97 #define CONFIG_SYS_RAMBOOT
98 #else
99 #undef  CONFIG_SYS_RAMBOOT
100 #endif
101 
102 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
103 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
104 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
105 
106 /*
107  * Initial RAM Base Address Setup
108  */
109 #define CONFIG_SYS_INIT_RAM_LOCK	1
110 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
111 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
112 #define CONFIG_SYS_GBL_DATA_OFFSET	\
113 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114 
115 /*
116  * FLASH on the Local Bus
117  */
118 #define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
119 #define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
120 
121 
122 
123 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
124 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
125 
126 #undef CONFIG_SYS_FLASH_CHECKSUM
127 
128 /*
129  * Serial Port
130  */
131 #define CONFIG_SYS_NS16550_SERIAL
132 #define CONFIG_SYS_NS16550_REG_SIZE	1
133 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
134 
135 #define CONFIG_SYS_BAUDRATE_TABLE  \
136 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
137 
138 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
139 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
140 
141 /* I2C */
142 #define CONFIG_SYS_I2C
143 #define CONFIG_SYS_I2C_FSL
144 #define CONFIG_SYS_FSL_I2C_SPEED	400000
145 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
146 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
147 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
148 
149 /*
150  * Config on-board EEPROM
151  */
152 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
156 
157 /*
158  * General PCI
159  * Addresses are mapped 1-1.
160  */
161 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
162 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
163 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
164 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
165 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
166 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
167 #define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
168 #define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
169 #define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
170 
171 #ifdef CONFIG_PCI
172 #define CONFIG_PCI_INDIRECT_BRIDGE
173 #define CONFIG_PCI_SKIP_HOST_BRIDGE
174 
175 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
176 #define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
177 
178 #endif	/* CONFIG_PCI */
179 
180 /*
181  * QE UEC ethernet configuration
182  */
183 #define CONFIG_UEC_ETH
184 #define CONFIG_ETHPRIME		"UEC0"
185 
186 #define CONFIG_UEC_ETH1		/* ETH3 */
187 
188 #ifdef CONFIG_UEC_ETH1
189 #define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
190 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
191 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
192 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
193 #define CONFIG_SYS_UEC1_PHY_ADDR	4
194 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
195 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
196 #endif
197 
198 #define CONFIG_UEC_ETH2		/* ETH4 */
199 
200 #ifdef CONFIG_UEC_ETH2
201 #define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
202 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
203 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
204 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
205 #define CONFIG_SYS_UEC2_PHY_ADDR	0
206 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
207 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
208 #endif
209 
210 /*
211  * Environment
212  */
213 
214 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
215 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
216 
217 /*
218  * BOOTP options
219  */
220 #define CONFIG_BOOTP_BOOTFILESIZE
221 
222 #undef CONFIG_WATCHDOG		/* watchdog disabled */
223 
224 /*
225  * Miscellaneous configurable options
226  */
227 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
228 
229 /*
230  * For booting Linux, the board info and command line data
231  * have to be in the first 256 MB of memory, since this is
232  * the maximum mapped by the Linux kernel during initialization.
233  */
234 					/* Initial Memory map for Linux */
235 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
236 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
237 
238 #if (CONFIG_CMD_KGDB)
239 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
240 #endif
241 
242 /*
243  * Environment Configuration
244  */
245 
246 #define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
247 #define CONFIG_HAS_ETH1		/* add support for "eth1addr" */
248 
249 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
250  * (see CONFIG_SYS_I2C_EEPROM) */
251 					/* MAC address offset in I2C EEPROM */
252 #define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
253 
254 #define CONFIG_NETDEV		"eth1"
255 
256 #define CONFIG_HOSTNAME		"mpc8323erdb"
257 #define CONFIG_ROOTPATH		"/nfsroot"
258 #define CONFIG_BOOTFILE		"uImage"
259 				/* U-Boot image on TFTP server */
260 #define CONFIG_UBOOTPATH	"u-boot.bin"
261 #define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
262 #define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
263 
264 				/* default location for tftp and bootm */
265 #define CONFIG_LOADADDR		800000
266 
267 #define CONFIG_EXTRA_ENV_SETTINGS \
268 	"netdev=" CONFIG_NETDEV "\0"					\
269 	"uboot=" CONFIG_UBOOTPATH "\0"					\
270 	"tftpflash=tftp $loadaddr $uboot;"				\
271 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
272 			" +$filesize; "	\
273 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
274 			" +$filesize; "	\
275 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
276 			" $filesize; "	\
277 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
278 			" +$filesize; "	\
279 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
280 			" $filesize\0"	\
281 	"fdtaddr=780000\0"						\
282 	"fdtfile=" CONFIG_FDTFILE "\0"					\
283 	"ramdiskaddr=1000000\0"						\
284 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
285 	"console=ttyS0\0"						\
286 	"setbootargs=setenv bootargs "					\
287 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
288 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
289 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
290 								"$netdev:off "\
291 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
292 
293 #define CONFIG_NFSBOOTCOMMAND						\
294 	"setenv rootdev /dev/nfs;"					\
295 	"run setbootargs;"						\
296 	"run setipargs;"						\
297 	"tftp $loadaddr $bootfile;"					\
298 	"tftp $fdtaddr $fdtfile;"					\
299 	"bootm $loadaddr - $fdtaddr"
300 
301 #define CONFIG_RAMBOOTCOMMAND						\
302 	"setenv rootdev /dev/ram;"					\
303 	"run setbootargs;"						\
304 	"tftp $ramdiskaddr $ramdiskfile;"				\
305 	"tftp $loadaddr $bootfile;"					\
306 	"tftp $fdtaddr $fdtfile;"					\
307 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
308 
309 #endif	/* __CONFIG_H */
310