1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * U-Boot Marvell 37xx SoC pinctrl driver
4 *
5 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
6 *
7 * This driver is based on the Linux driver version, which is:
8 * Copyright (C) 2017 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 *
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
12 * which is:
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
15 * Copyright (C) 2016 Endless Mobile, Inc.
16 * https://spdx.org/licenses
17 */
18
19 #include <common.h>
20 #include <config.h>
21 #include <dm.h>
22 #include <malloc.h>
23 #include <asm/global_data.h>
24 #include <dm/device-internal.h>
25 #include <dm/device_compat.h>
26 #include <dm/devres.h>
27 #include <dm/lists.h>
28 #include <dm/pinctrl.h>
29 #include <dm/root.h>
30 #include <errno.h>
31 #include <fdtdec.h>
32 #include <regmap.h>
33 #include <asm/gpio.h>
34 #include <asm/system.h>
35 #include <asm/io.h>
36 #include <linux/bitops.h>
37 #include <linux/libfdt.h>
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #define OUTPUT_EN 0x0
42 #define INPUT_VAL 0x10
43 #define OUTPUT_VAL 0x18
44 #define OUTPUT_CTL 0x20
45 #define SELECTION 0x30
46
47 #define IRQ_EN 0x0
48 #define IRQ_POL 0x08
49 #define IRQ_STATUS 0x10
50 #define IRQ_WKUP 0x18
51
52 #define NB_FUNCS 3
53 #define GPIO_PER_REG 32
54
55 /**
56 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
57 * The pins of a pinmux groups are composed of one or two groups of contiguous
58 * pins.
59 * @name: Name of the pin group, used to lookup the group.
60 * @start_pins: Index of the first pin of the main range of pins belonging to
61 * the group
62 * @npins: Number of pins included in the first range
63 * @reg_mask: Bit mask matching the group in the selection register
64 * @extra_pins: Index of the first pin of the optional second range of pins
65 * belonging to the group
66 * @npins: Number of pins included in the second optional range
67 * @funcs: A list of pinmux functions that can be selected for this group.
68 * @pins: List of the pins included in the group
69 */
70 struct armada_37xx_pin_group {
71 const char *name;
72 unsigned int start_pin;
73 unsigned int npins;
74 u32 reg_mask;
75 u32 val[NB_FUNCS];
76 unsigned int extra_pin;
77 unsigned int extra_npins;
78 const char *funcs[NB_FUNCS];
79 unsigned int *pins;
80 };
81
82 struct armada_37xx_pin_data {
83 u8 nr_pins;
84 char *name;
85 struct armada_37xx_pin_group *groups;
86 int ngroups;
87 };
88
89 struct armada_37xx_pmx_func {
90 const char *name;
91 const char **groups;
92 unsigned int ngroups;
93 };
94
95 struct armada_37xx_pinctrl {
96 void __iomem *base;
97 const struct armada_37xx_pin_data *data;
98 struct udevice *dev;
99 struct pinctrl_dev *pctl_dev;
100 struct armada_37xx_pin_group *groups;
101 unsigned int ngroups;
102 struct armada_37xx_pmx_func *funcs;
103 unsigned int nfuncs;
104 };
105
106 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
107 { \
108 .name = _name, \
109 .start_pin = _start, \
110 .npins = _nr, \
111 .reg_mask = _mask, \
112 .val = {0, _mask}, \
113 .funcs = {_func1, _func2} \
114 }
115
116 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
117 { \
118 .name = _name, \
119 .start_pin = _start, \
120 .npins = _nr, \
121 .reg_mask = _mask, \
122 .val = {0, _mask}, \
123 .funcs = {_func1, "gpio"} \
124 }
125
126 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
127 { \
128 .name = _name, \
129 .start_pin = _start, \
130 .npins = _nr, \
131 .reg_mask = _mask, \
132 .val = {_val1, _val2}, \
133 .funcs = {_func1, "gpio"} \
134 }
135
136 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
137 { \
138 .name = _name, \
139 .start_pin = _start, \
140 .npins = _nr, \
141 .reg_mask = _mask, \
142 .val = {_v1, _v2, _v3}, \
143 .funcs = {_f1, _f2, "gpio"} \
144 }
145
146 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
147 _f1, _f2) \
148 { \
149 .name = _name, \
150 .start_pin = _start, \
151 .npins = _nr, \
152 .reg_mask = _mask, \
153 .val = {_v1, _v2}, \
154 .extra_pin = _start2, \
155 .extra_npins = _nr2, \
156 .funcs = {_f1, _f2} \
157 }
158
159 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
160 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
161 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
162 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
163 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
164 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
165 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
166 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
167 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
168 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
169 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
170 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
171 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
172 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
173 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
174 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
175 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
176 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
177 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
178 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
179 18, 2, "gpio", "uart"),
180 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
181 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
182 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
183 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
184
185 };
186
187 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
188 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
189 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
190 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
191 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
192 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
193 PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
194 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
195 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
196 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
197 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
198 "mii", "mii_err"),
199 };
200
201 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
202 .nr_pins = 36,
203 .name = "GPIO1",
204 .groups = armada_37xx_nb_groups,
205 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
206 };
207
208 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
209 .nr_pins = 30,
210 .name = "GPIO2",
211 .groups = armada_37xx_sb_groups,
212 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
213 };
214
armada_37xx_update_reg(unsigned int * reg,unsigned int * offset)215 static inline void armada_37xx_update_reg(unsigned int *reg,
216 unsigned int *offset)
217 {
218 /* We never have more than 2 registers */
219 if (*offset >= GPIO_PER_REG) {
220 *offset -= GPIO_PER_REG;
221 *reg += sizeof(u32);
222 }
223 }
224
armada_37xx_get_func_reg(struct armada_37xx_pin_group * grp,const char * func)225 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
226 const char *func)
227 {
228 int f;
229
230 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
231 if (!strcmp(grp->funcs[f], func))
232 return f;
233
234 return -ENOTSUPP;
235 }
236
armada_37xx_pmx_get_groups_count(struct udevice * dev)237 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
238 {
239 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
240
241 return info->ngroups;
242 }
243
244 static const char *armada_37xx_pmx_dummy_name = "_dummy";
245
armada_37xx_pmx_get_group_name(struct udevice * dev,unsigned selector)246 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
247 unsigned selector)
248 {
249 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
250
251 if (!info->groups[selector].name)
252 return armada_37xx_pmx_dummy_name;
253
254 return info->groups[selector].name;
255 }
256
armada_37xx_pmx_get_funcs_count(struct udevice * dev)257 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
258 {
259 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
260
261 return info->nfuncs;
262 }
263
armada_37xx_pmx_get_func_name(struct udevice * dev,unsigned selector)264 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
265 unsigned selector)
266 {
267 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
268
269 return info->funcs[selector].name;
270 }
271
armada_37xx_pmx_set_by_name(struct udevice * dev,const char * name,struct armada_37xx_pin_group * grp)272 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
273 const char *name,
274 struct armada_37xx_pin_group *grp)
275 {
276 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
277 unsigned int reg = SELECTION;
278 unsigned int mask = grp->reg_mask;
279 int func, val;
280
281 dev_dbg(info->dev, "enable function %s group %s\n",
282 name, grp->name);
283
284 func = armada_37xx_get_func_reg(grp, name);
285
286 if (func < 0)
287 return func;
288
289 val = grp->val[func];
290
291 clrsetbits_le32(info->base + reg, mask, val);
292
293 return 0;
294 }
295
armada_37xx_pmx_group_set(struct udevice * dev,unsigned group_selector,unsigned func_selector)296 static int armada_37xx_pmx_group_set(struct udevice *dev,
297 unsigned group_selector,
298 unsigned func_selector)
299 {
300 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
301 struct armada_37xx_pin_group *grp = &info->groups[group_selector];
302 const char *name = info->funcs[func_selector].name;
303
304 return armada_37xx_pmx_set_by_name(dev, name, grp);
305 }
306
307 /**
308 * armada_37xx_add_function() - Add a new function to the list
309 * @funcs: array of function to add the new one
310 * @funcsize: size of the remaining space for the function
311 * @name: name of the function to add
312 *
313 * If it is a new function then create it by adding its name else
314 * increment the number of group associated to this function.
315 */
armada_37xx_add_function(struct armada_37xx_pmx_func * funcs,int * funcsize,const char * name)316 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
317 int *funcsize, const char *name)
318 {
319 int i = 0;
320
321 if (*funcsize <= 0)
322 return -EOVERFLOW;
323
324 while (funcs->ngroups) {
325 /* function already there */
326 if (strcmp(funcs->name, name) == 0) {
327 funcs->ngroups++;
328
329 return -EEXIST;
330 }
331 funcs++;
332 i++;
333 }
334
335 /* append new unique function */
336 funcs->name = name;
337 funcs->ngroups = 1;
338 (*funcsize)--;
339
340 return 0;
341 }
342
343 /**
344 * armada_37xx_fill_group() - complete the group array
345 * @info: info driver instance
346 *
347 * Based on the data available from the armada_37xx_pin_group array
348 * completes the last member of the struct for each function: the list
349 * of the groups associated to this function.
350 *
351 */
armada_37xx_fill_group(struct armada_37xx_pinctrl * info)352 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
353 {
354 int n, num = 0, funcsize = info->data->nr_pins;
355
356 for (n = 0; n < info->ngroups; n++) {
357 struct armada_37xx_pin_group *grp = &info->groups[n];
358 int i, j, f;
359
360 grp->pins = devm_kzalloc(info->dev,
361 (grp->npins + grp->extra_npins) *
362 sizeof(*grp->pins), GFP_KERNEL);
363 if (!grp->pins)
364 return -ENOMEM;
365
366 for (i = 0; i < grp->npins; i++)
367 grp->pins[i] = grp->start_pin + i;
368
369 for (j = 0; j < grp->extra_npins; j++)
370 grp->pins[i+j] = grp->extra_pin + j;
371
372 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
373 int ret;
374 /* check for unique functions and count groups */
375 ret = armada_37xx_add_function(info->funcs, &funcsize,
376 grp->funcs[f]);
377 if (ret == -EOVERFLOW)
378 dev_err(info->dev,
379 "More functions than pins(%d)\n",
380 info->data->nr_pins);
381 if (ret < 0)
382 continue;
383 num++;
384 }
385 }
386
387 info->nfuncs = num;
388
389 return 0;
390 }
391
392 /**
393 * armada_37xx_fill_funcs() - complete the funcs array
394 * @info: info driver instance
395 *
396 * Based on the data available from the armada_37xx_pin_group array
397 * completes the last two member of the struct for each group:
398 * - the list of the pins included in the group
399 * - the list of pinmux functions that can be selected for this group
400 *
401 */
armada_37xx_fill_func(struct armada_37xx_pinctrl * info)402 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
403 {
404 struct armada_37xx_pmx_func *funcs = info->funcs;
405 int n;
406
407 for (n = 0; n < info->nfuncs; n++) {
408 const char *name = funcs[n].name;
409 const char **groups;
410 int g;
411
412 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
413 sizeof(*(funcs[n].groups)),
414 GFP_KERNEL);
415 if (!funcs[n].groups)
416 return -ENOMEM;
417
418 groups = funcs[n].groups;
419
420 for (g = 0; g < info->ngroups; g++) {
421 struct armada_37xx_pin_group *gp = &info->groups[g];
422 int f;
423
424 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
425 if (strcmp(gp->funcs[f], name) == 0) {
426 *groups = gp->name;
427 groups++;
428 }
429 }
430 }
431 }
432 return 0;
433 }
434
armada_37xx_gpio_get(struct udevice * dev,unsigned int offset)435 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
436 {
437 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
438 unsigned int reg = INPUT_VAL;
439 unsigned int val, mask;
440
441 armada_37xx_update_reg(®, &offset);
442 mask = BIT(offset);
443
444 val = readl(info->base + reg);
445
446 return (val & mask) != 0;
447 }
448
armada_37xx_gpio_set(struct udevice * dev,unsigned int offset,int value)449 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
450 int value)
451 {
452 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
453 unsigned int reg = OUTPUT_VAL;
454 unsigned int mask, val;
455
456 armada_37xx_update_reg(®, &offset);
457 mask = BIT(offset);
458 val = value ? mask : 0;
459
460 clrsetbits_le32(info->base + reg, mask, val);
461
462 return 0;
463 }
464
armada_37xx_gpio_get_direction(struct udevice * dev,unsigned int offset)465 static int armada_37xx_gpio_get_direction(struct udevice *dev,
466 unsigned int offset)
467 {
468 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
469 unsigned int reg = OUTPUT_EN;
470 unsigned int val, mask;
471
472 armada_37xx_update_reg(®, &offset);
473 mask = BIT(offset);
474 val = readl(info->base + reg);
475
476 if (val & mask)
477 return GPIOF_OUTPUT;
478 else
479 return GPIOF_INPUT;
480 }
481
armada_37xx_gpio_direction_input(struct udevice * dev,unsigned int offset)482 static int armada_37xx_gpio_direction_input(struct udevice *dev,
483 unsigned int offset)
484 {
485 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
486 unsigned int reg = OUTPUT_EN;
487 unsigned int mask;
488
489 armada_37xx_update_reg(®, &offset);
490 mask = BIT(offset);
491
492 clrbits_le32(info->base + reg, mask);
493
494 return 0;
495 }
496
armada_37xx_gpio_direction_output(struct udevice * dev,unsigned int offset,int value)497 static int armada_37xx_gpio_direction_output(struct udevice *dev,
498 unsigned int offset, int value)
499 {
500 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
501 unsigned int reg = OUTPUT_EN;
502 unsigned int mask;
503
504 armada_37xx_update_reg(®, &offset);
505 mask = BIT(offset);
506
507 setbits_le32(info->base + reg, mask);
508
509 /* And set the requested value */
510 return armada_37xx_gpio_set(dev, offset, value);
511 }
512
armada_37xx_gpio_probe(struct udevice * dev)513 static int armada_37xx_gpio_probe(struct udevice *dev)
514 {
515 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
516 struct gpio_dev_priv *uc_priv;
517
518 uc_priv = dev_get_uclass_priv(dev);
519 uc_priv->bank_name = info->data->name;
520 uc_priv->gpio_count = info->data->nr_pins;
521
522 return 0;
523 }
524
525 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
526 .set_value = armada_37xx_gpio_set,
527 .get_value = armada_37xx_gpio_get,
528 .get_function = armada_37xx_gpio_get_direction,
529 .direction_input = armada_37xx_gpio_direction_input,
530 .direction_output = armada_37xx_gpio_direction_output,
531 };
532
533 static struct driver armada_37xx_gpio_driver = {
534 .name = "armada-37xx-gpio",
535 .id = UCLASS_GPIO,
536 .probe = armada_37xx_gpio_probe,
537 .ops = &armada_37xx_gpio_ops,
538 };
539
armada_37xx_gpiochip_register(struct udevice * parent,struct armada_37xx_pinctrl * info)540 static int armada_37xx_gpiochip_register(struct udevice *parent,
541 struct armada_37xx_pinctrl *info)
542 {
543 const void *blob = gd->fdt_blob;
544 int node = dev_of_offset(parent);
545 struct uclass_driver *drv;
546 struct udevice *dev;
547 int ret = -ENODEV;
548 int subnode;
549 char *name;
550
551 /* FIXME: Should not need to lookup GPIO uclass */
552 drv = lists_uclass_lookup(UCLASS_GPIO);
553 if (!drv) {
554 puts("Cannot find GPIO driver\n");
555 return -ENOENT;
556 }
557
558 /* FIXME: Use livtree and check the result of device_bind() below */
559 fdt_for_each_subnode(subnode, blob, node) {
560 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
561 ret = 0;
562 break;
563 }
564 };
565 if (ret)
566 return ret;
567
568 name = calloc(1, 32);
569 sprintf(name, "armada-37xx-gpio");
570
571 /* Create child device UCLASS_GPIO and bind it */
572 device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
573 offset_to_ofnode(subnode), &dev);
574
575 return 0;
576 }
577
578 const struct pinctrl_ops armada_37xx_pinctrl_ops = {
579 .get_groups_count = armada_37xx_pmx_get_groups_count,
580 .get_group_name = armada_37xx_pmx_get_group_name,
581 .get_functions_count = armada_37xx_pmx_get_funcs_count,
582 .get_function_name = armada_37xx_pmx_get_func_name,
583 .pinmux_group_set = armada_37xx_pmx_group_set,
584 .set_state = pinctrl_generic_set_state,
585 };
586
armada_37xx_pinctrl_probe(struct udevice * dev)587 int armada_37xx_pinctrl_probe(struct udevice *dev)
588 {
589 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
590 const struct armada_37xx_pin_data *pin_data;
591 int ret;
592
593 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
594 pin_data = info->data;
595
596 info->base = dev_read_addr_ptr(dev);
597 if (!info->base) {
598 pr_err("unable to find regmap\n");
599 return -ENODEV;
600 }
601
602 info->groups = pin_data->groups;
603 info->ngroups = pin_data->ngroups;
604
605 /*
606 * we allocate functions for number of pins and hope there are
607 * fewer unique functions than pins available
608 */
609 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
610 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
611 if (!info->funcs)
612 return -ENOMEM;
613
614
615 ret = armada_37xx_fill_group(info);
616 if (ret)
617 return ret;
618
619 ret = armada_37xx_fill_func(info);
620 if (ret)
621 return ret;
622
623 ret = armada_37xx_gpiochip_register(dev, info);
624 if (ret)
625 return ret;
626
627 return 0;
628 }
629
630 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
631 {
632 .compatible = "marvell,armada3710-sb-pinctrl",
633 .data = (ulong)&armada_37xx_pin_sb,
634 },
635 {
636 .compatible = "marvell,armada3710-nb-pinctrl",
637 .data = (ulong)&armada_37xx_pin_nb,
638 },
639 { /* sentinel */ }
640 };
641
642 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
643 .name = "armada-37xx-pinctrl",
644 .id = UCLASS_PINCTRL,
645 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
646 .probe = armada_37xx_pinctrl_probe,
647 .priv_auto = sizeof(struct armada_37xx_pinctrl),
648 .ops = &armada_37xx_pinctrl_ops,
649 };
650