1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon pko. 7 */ 8 9 #ifndef __CVMX_PKO_DEFS_H__ 10 #define __CVMX_PKO_DEFS_H__ 11 12 #define CVMX_PKO_CHANNEL_LEVEL (0x00015400000800F0ull) 13 #define CVMX_PKO_DPFI_ENA (0x0001540000C00018ull) 14 #define CVMX_PKO_DPFI_FLUSH (0x0001540000C00008ull) 15 #define CVMX_PKO_DPFI_FPA_AURA (0x0001540000C00010ull) 16 #define CVMX_PKO_DPFI_STATUS (0x0001540000C00000ull) 17 #define CVMX_PKO_DQX_BYTES(offset) (0x00015400000000D8ull + ((offset) & 1023) * 512) 18 #define CVMX_PKO_DQX_CIR(offset) (0x0001540000280018ull + ((offset) & 1023) * 512) 19 #define CVMX_PKO_DQX_DROPPED_BYTES(offset) (0x00015400000000C8ull + ((offset) & 1023) * 512) 20 #define CVMX_PKO_DQX_DROPPED_PACKETS(offset) (0x00015400000000C0ull + ((offset) & 1023) * 512) 21 #define CVMX_PKO_DQX_FIFO(offset) (0x0001540000300078ull + ((offset) & 1023) * 512) 22 #define CVMX_PKO_DQX_PACKETS(offset) (0x00015400000000D0ull + ((offset) & 1023) * 512) 23 #define CVMX_PKO_DQX_PICK(offset) (0x0001540000300070ull + ((offset) & 1023) * 512) 24 #define CVMX_PKO_DQX_PIR(offset) (0x0001540000280020ull + ((offset) & 1023) * 512) 25 #define CVMX_PKO_DQX_POINTERS(offset) (0x0001540000280078ull + ((offset) & 1023) * 512) 26 #define CVMX_PKO_DQX_SCHEDULE(offset) (0x0001540000280008ull + ((offset) & 1023) * 512) 27 #define CVMX_PKO_DQX_SCHED_STATE(offset) (0x0001540000280028ull + ((offset) & 1023) * 512) 28 #define CVMX_PKO_DQX_SHAPE(offset) (0x0001540000280010ull + ((offset) & 1023) * 512) 29 #define CVMX_PKO_DQX_SHAPE_STATE(offset) (0x0001540000280030ull + ((offset) & 1023) * 512) 30 #define CVMX_PKO_DQX_SW_XOFF(offset) (0x00015400002800E0ull + ((offset) & 1023) * 512) 31 #define CVMX_PKO_DQX_TOPOLOGY(offset) (0x0001540000300000ull + ((offset) & 1023) * 512) 32 #define CVMX_PKO_DQX_WM_BUF_CNT(offset) (0x00015400008000E8ull + ((offset) & 1023) * 512) 33 #define CVMX_PKO_DQX_WM_BUF_CTL(offset) (0x00015400008000F0ull + ((offset) & 1023) * 512) 34 #define CVMX_PKO_DQX_WM_BUF_CTL_W1C(offset) (0x00015400008000F8ull + ((offset) & 1023) * 512) 35 #define CVMX_PKO_DQX_WM_CNT(offset) (0x0001540000000050ull + ((offset) & 1023) * 512) 36 #define CVMX_PKO_DQX_WM_CTL(offset) (0x0001540000000040ull + ((offset) & 1023) * 512) 37 #define CVMX_PKO_DQX_WM_CTL_W1C(offset) (0x0001540000000048ull + ((offset) & 1023) * 512) 38 #define CVMX_PKO_DQ_CSR_BUS_DEBUG (0x00015400003001F8ull) 39 #define CVMX_PKO_DQ_DEBUG (0x0001540000300128ull) 40 #define CVMX_PKO_DRAIN_IRQ (0x0001540000000140ull) 41 #define CVMX_PKO_ENABLE (0x0001540000D00008ull) 42 #define CVMX_PKO_FORMATX_CTL(offset) (0x0001540000900800ull + ((offset) & 127) * 8) 43 #define CVMX_PKO_L1_SQA_DEBUG (0x0001540000080128ull) 44 #define CVMX_PKO_L1_SQB_DEBUG (0x0001540000080130ull) 45 #define CVMX_PKO_L1_SQX_CIR(offset) (0x0001540000000018ull + ((offset) & 31) * 512) 46 #define CVMX_PKO_L1_SQX_DROPPED_BYTES(offset) (0x0001540000000088ull + ((offset) & 31) * 512) 47 #define CVMX_PKO_L1_SQX_DROPPED_PACKETS(offset) (0x0001540000000080ull + ((offset) & 31) * 512) 48 #define CVMX_PKO_L1_SQX_GREEN(offset) (0x0001540000080058ull + ((offset) & 31) * 512) 49 #define CVMX_PKO_L1_SQX_GREEN_BYTES(offset) (0x00015400000000B8ull + ((offset) & 31) * 512) 50 #define CVMX_PKO_L1_SQX_GREEN_PACKETS(offset) (0x00015400000000B0ull + ((offset) & 31) * 512) 51 #define CVMX_PKO_L1_SQX_LINK(offset) (0x0001540000000038ull + ((offset) & 31) * 512) 52 #define CVMX_PKO_L1_SQX_PICK(offset) (0x0001540000080070ull + ((offset) & 31) * 512) 53 #define CVMX_PKO_L1_SQX_RED(offset) (0x0001540000080068ull + ((offset) & 31) * 512) 54 #define CVMX_PKO_L1_SQX_RED_BYTES(offset) (0x0001540000000098ull + ((offset) & 31) * 512) 55 #define CVMX_PKO_L1_SQX_RED_PACKETS(offset) (0x0001540000000090ull + ((offset) & 31) * 512) 56 #define CVMX_PKO_L1_SQX_SCHEDULE(offset) (0x0001540000000008ull + ((offset) & 31) * 512) 57 #define CVMX_PKO_L1_SQX_SHAPE(offset) (0x0001540000000010ull + ((offset) & 31) * 512) 58 #define CVMX_PKO_L1_SQX_SHAPE_STATE(offset) (0x0001540000000030ull + ((offset) & 31) * 512) 59 #define CVMX_PKO_L1_SQX_SW_XOFF(offset) (0x00015400000000E0ull + ((offset) & 31) * 512) 60 #define CVMX_PKO_L1_SQX_TOPOLOGY(offset) (0x0001540000080000ull + ((offset) & 31) * 512) 61 #define CVMX_PKO_L1_SQX_YELLOW(offset) (0x0001540000080060ull + ((offset) & 31) * 512) 62 #define CVMX_PKO_L1_SQX_YELLOW_BYTES(offset) (0x00015400000000A8ull + ((offset) & 31) * 512) 63 #define CVMX_PKO_L1_SQX_YELLOW_PACKETS(offset) (0x00015400000000A0ull + ((offset) & 31) * 512) 64 #define CVMX_PKO_L1_SQ_CSR_BUS_DEBUG (0x00015400000801F8ull) 65 #define CVMX_PKO_L2_SQA_DEBUG (0x0001540000100128ull) 66 #define CVMX_PKO_L2_SQB_DEBUG (0x0001540000100130ull) 67 #define CVMX_PKO_L2_SQX_CIR(offset) (0x0001540000080018ull + ((offset) & 511) * 512) 68 #define CVMX_PKO_L2_SQX_GREEN(offset) (0x0001540000100058ull + ((offset) & 511) * 512) 69 #define CVMX_PKO_L2_SQX_PICK(offset) (0x0001540000100070ull + ((offset) & 511) * 512) 70 #define CVMX_PKO_L2_SQX_PIR(offset) (0x0001540000080020ull + ((offset) & 511) * 512) 71 #define CVMX_PKO_L2_SQX_POINTERS(offset) (0x0001540000080078ull + ((offset) & 511) * 512) 72 #define CVMX_PKO_L2_SQX_RED(offset) (0x0001540000100068ull + ((offset) & 511) * 512) 73 #define CVMX_PKO_L2_SQX_SCHEDULE(offset) (0x0001540000080008ull + ((offset) & 511) * 512) 74 #define CVMX_PKO_L2_SQX_SCHED_STATE(offset) (0x0001540000080028ull + ((offset) & 511) * 512) 75 #define CVMX_PKO_L2_SQX_SHAPE(offset) (0x0001540000080010ull + ((offset) & 511) * 512) 76 #define CVMX_PKO_L2_SQX_SHAPE_STATE(offset) (0x0001540000080030ull + ((offset) & 511) * 512) 77 #define CVMX_PKO_L2_SQX_SW_XOFF(offset) (0x00015400000800E0ull + ((offset) & 511) * 512) 78 #define CVMX_PKO_L2_SQX_TOPOLOGY(offset) (0x0001540000100000ull + ((offset) & 511) * 512) 79 #define CVMX_PKO_L2_SQX_YELLOW(offset) (0x0001540000100060ull + ((offset) & 511) * 512) 80 #define CVMX_PKO_L2_SQ_CSR_BUS_DEBUG (0x00015400001001F8ull) 81 #define CVMX_PKO_L3_L2_SQX_CHANNEL(offset) (0x0001540000080038ull + ((offset) & 511) * 512) 82 #define CVMX_PKO_L3_SQA_DEBUG (0x0001540000180128ull) 83 #define CVMX_PKO_L3_SQB_DEBUG (0x0001540000180130ull) 84 #define CVMX_PKO_L3_SQX_CIR(offset) (0x0001540000100018ull + ((offset) & 511) * 512) 85 #define CVMX_PKO_L3_SQX_GREEN(offset) (0x0001540000180058ull + ((offset) & 511) * 512) 86 #define CVMX_PKO_L3_SQX_PICK(offset) (0x0001540000180070ull + ((offset) & 511) * 512) 87 #define CVMX_PKO_L3_SQX_PIR(offset) (0x0001540000100020ull + ((offset) & 511) * 512) 88 #define CVMX_PKO_L3_SQX_POINTERS(offset) (0x0001540000100078ull + ((offset) & 511) * 512) 89 #define CVMX_PKO_L3_SQX_RED(offset) (0x0001540000180068ull + ((offset) & 511) * 512) 90 #define CVMX_PKO_L3_SQX_SCHEDULE(offset) (0x0001540000100008ull + ((offset) & 511) * 512) 91 #define CVMX_PKO_L3_SQX_SCHED_STATE(offset) (0x0001540000100028ull + ((offset) & 511) * 512) 92 #define CVMX_PKO_L3_SQX_SHAPE(offset) (0x0001540000100010ull + ((offset) & 511) * 512) 93 #define CVMX_PKO_L3_SQX_SHAPE_STATE(offset) (0x0001540000100030ull + ((offset) & 511) * 512) 94 #define CVMX_PKO_L3_SQX_SW_XOFF(offset) (0x00015400001000E0ull + ((offset) & 511) * 512) 95 #define CVMX_PKO_L3_SQX_TOPOLOGY(offset) (0x0001540000180000ull + ((offset) & 511) * 512) 96 #define CVMX_PKO_L3_SQX_YELLOW(offset) (0x0001540000180060ull + ((offset) & 511) * 512) 97 #define CVMX_PKO_L3_SQ_CSR_BUS_DEBUG (0x00015400001801F8ull) 98 #define CVMX_PKO_L4_SQA_DEBUG (0x0001540000200128ull) 99 #define CVMX_PKO_L4_SQB_DEBUG (0x0001540000200130ull) 100 #define CVMX_PKO_L4_SQX_CIR(offset) (0x0001540000180018ull + ((offset) & 1023) * 512) 101 #define CVMX_PKO_L4_SQX_GREEN(offset) (0x0001540000200058ull + ((offset) & 1023) * 512) 102 #define CVMX_PKO_L4_SQX_PICK(offset) (0x0001540000200070ull + ((offset) & 1023) * 512) 103 #define CVMX_PKO_L4_SQX_PIR(offset) (0x0001540000180020ull + ((offset) & 1023) * 512) 104 #define CVMX_PKO_L4_SQX_POINTERS(offset) (0x0001540000180078ull + ((offset) & 1023) * 512) 105 #define CVMX_PKO_L4_SQX_RED(offset) (0x0001540000200068ull + ((offset) & 1023) * 512) 106 #define CVMX_PKO_L4_SQX_SCHEDULE(offset) (0x0001540000180008ull + ((offset) & 1023) * 512) 107 #define CVMX_PKO_L4_SQX_SCHED_STATE(offset) (0x0001540000180028ull + ((offset) & 511) * 512) 108 #define CVMX_PKO_L4_SQX_SHAPE(offset) (0x0001540000180010ull + ((offset) & 1023) * 512) 109 #define CVMX_PKO_L4_SQX_SHAPE_STATE(offset) (0x0001540000180030ull + ((offset) & 1023) * 512) 110 #define CVMX_PKO_L4_SQX_SW_XOFF(offset) (0x00015400001800E0ull + ((offset) & 1023) * 512) 111 #define CVMX_PKO_L4_SQX_TOPOLOGY(offset) (0x0001540000200000ull + ((offset) & 1023) * 512) 112 #define CVMX_PKO_L4_SQX_YELLOW(offset) (0x0001540000200060ull + ((offset) & 1023) * 512) 113 #define CVMX_PKO_L4_SQ_CSR_BUS_DEBUG (0x00015400002001F8ull) 114 #define CVMX_PKO_L5_SQA_DEBUG (0x0001540000280128ull) 115 #define CVMX_PKO_L5_SQB_DEBUG (0x0001540000280130ull) 116 #define CVMX_PKO_L5_SQX_CIR(offset) (0x0001540000200018ull + ((offset) & 1023) * 512) 117 #define CVMX_PKO_L5_SQX_GREEN(offset) (0x0001540000280058ull + ((offset) & 1023) * 512) 118 #define CVMX_PKO_L5_SQX_PICK(offset) (0x0001540000280070ull + ((offset) & 1023) * 512) 119 #define CVMX_PKO_L5_SQX_PIR(offset) (0x0001540000200020ull + ((offset) & 1023) * 512) 120 #define CVMX_PKO_L5_SQX_POINTERS(offset) (0x0001540000200078ull + ((offset) & 1023) * 512) 121 #define CVMX_PKO_L5_SQX_RED(offset) (0x0001540000280068ull + ((offset) & 1023) * 512) 122 #define CVMX_PKO_L5_SQX_SCHEDULE(offset) (0x0001540000200008ull + ((offset) & 1023) * 512) 123 #define CVMX_PKO_L5_SQX_SCHED_STATE(offset) (0x0001540000200028ull + ((offset) & 1023) * 512) 124 #define CVMX_PKO_L5_SQX_SHAPE(offset) (0x0001540000200010ull + ((offset) & 1023) * 512) 125 #define CVMX_PKO_L5_SQX_SHAPE_STATE(offset) (0x0001540000200030ull + ((offset) & 1023) * 512) 126 #define CVMX_PKO_L5_SQX_SW_XOFF(offset) (0x00015400002000E0ull + ((offset) & 1023) * 512) 127 #define CVMX_PKO_L5_SQX_TOPOLOGY(offset) (0x0001540000280000ull + ((offset) & 1023) * 512) 128 #define CVMX_PKO_L5_SQX_YELLOW(offset) (0x0001540000280060ull + ((offset) & 1023) * 512) 129 #define CVMX_PKO_L5_SQ_CSR_BUS_DEBUG (0x00015400002801F8ull) 130 #define CVMX_PKO_LUTX(offset) (0x0001540000B00000ull + ((offset) & 1023) * 8) 131 #define CVMX_PKO_LUT_BIST_STATUS (0x0001540000B02018ull) 132 #define CVMX_PKO_LUT_ECC_CTL0 (0x0001540000BFFFD0ull) 133 #define CVMX_PKO_LUT_ECC_DBE_STS0 (0x0001540000BFFFF0ull) 134 #define CVMX_PKO_LUT_ECC_DBE_STS_CMB0 (0x0001540000BFFFD8ull) 135 #define CVMX_PKO_LUT_ECC_SBE_STS0 (0x0001540000BFFFF8ull) 136 #define CVMX_PKO_LUT_ECC_SBE_STS_CMB0 (0x0001540000BFFFE8ull) 137 #define CVMX_PKO_MACX_CFG(offset) (0x0001540000900000ull + ((offset) & 31) * 8) 138 #define CVMX_PKO_MCI0_CRED_CNTX(offset) (0x0001540000A40000ull + ((offset) & 31) * 8) 139 #define CVMX_PKO_MCI0_MAX_CREDX(offset) (0x0001540000A00000ull + ((offset) & 31) * 8) 140 #define CVMX_PKO_MCI1_CRED_CNTX(offset) (0x0001540000A80100ull + ((offset) & 31) * 8) 141 #define CVMX_PKO_MCI1_MAX_CREDX(offset) (0x0001540000A80000ull + ((offset) & 31) * 8) 142 #define CVMX_PKO_MEM_COUNT0 (0x0001180050001080ull) 143 #define CVMX_PKO_MEM_COUNT1 (0x0001180050001088ull) 144 #define CVMX_PKO_MEM_DEBUG0 (0x0001180050001100ull) 145 #define CVMX_PKO_MEM_DEBUG1 (0x0001180050001108ull) 146 #define CVMX_PKO_MEM_DEBUG10 (0x0001180050001150ull) 147 #define CVMX_PKO_MEM_DEBUG11 (0x0001180050001158ull) 148 #define CVMX_PKO_MEM_DEBUG12 (0x0001180050001160ull) 149 #define CVMX_PKO_MEM_DEBUG13 (0x0001180050001168ull) 150 #define CVMX_PKO_MEM_DEBUG14 (0x0001180050001170ull) 151 #define CVMX_PKO_MEM_DEBUG2 (0x0001180050001110ull) 152 #define CVMX_PKO_MEM_DEBUG3 (0x0001180050001118ull) 153 #define CVMX_PKO_MEM_DEBUG4 (0x0001180050001120ull) 154 #define CVMX_PKO_MEM_DEBUG5 (0x0001180050001128ull) 155 #define CVMX_PKO_MEM_DEBUG6 (0x0001180050001130ull) 156 #define CVMX_PKO_MEM_DEBUG7 (0x0001180050001138ull) 157 #define CVMX_PKO_MEM_DEBUG8 (0x0001180050001140ull) 158 #define CVMX_PKO_MEM_DEBUG9 (0x0001180050001148ull) 159 #define CVMX_PKO_MEM_IPORT_PTRS (0x0001180050001030ull) 160 #define CVMX_PKO_MEM_IPORT_QOS (0x0001180050001038ull) 161 #define CVMX_PKO_MEM_IQUEUE_PTRS (0x0001180050001040ull) 162 #define CVMX_PKO_MEM_IQUEUE_QOS (0x0001180050001048ull) 163 #define CVMX_PKO_MEM_PORT_PTRS (0x0001180050001010ull) 164 #define CVMX_PKO_MEM_PORT_QOS (0x0001180050001018ull) 165 #define CVMX_PKO_MEM_PORT_RATE0 (0x0001180050001020ull) 166 #define CVMX_PKO_MEM_PORT_RATE1 (0x0001180050001028ull) 167 #define CVMX_PKO_MEM_QUEUE_PTRS (0x0001180050001000ull) 168 #define CVMX_PKO_MEM_QUEUE_QOS (0x0001180050001008ull) 169 #define CVMX_PKO_MEM_THROTTLE_INT (0x0001180050001058ull) 170 #define CVMX_PKO_MEM_THROTTLE_PIPE (0x0001180050001050ull) 171 #define CVMX_PKO_NCB_BIST_STATUS (0x0001540000EFFF00ull) 172 #define CVMX_PKO_NCB_ECC_CTL0 (0x0001540000EFFFD0ull) 173 #define CVMX_PKO_NCB_ECC_DBE_STS0 (0x0001540000EFFFF0ull) 174 #define CVMX_PKO_NCB_ECC_DBE_STS_CMB0 (0x0001540000EFFFD8ull) 175 #define CVMX_PKO_NCB_ECC_SBE_STS0 (0x0001540000EFFFF8ull) 176 #define CVMX_PKO_NCB_ECC_SBE_STS_CMB0 (0x0001540000EFFFE8ull) 177 #define CVMX_PKO_NCB_INT (0x0001540000E00010ull) 178 #define CVMX_PKO_NCB_TX_ERR_INFO (0x0001540000E00008ull) 179 #define CVMX_PKO_NCB_TX_ERR_WORD (0x0001540000E00000ull) 180 #define CVMX_PKO_PDM_BIST_STATUS (0x00015400008FFF00ull) 181 #define CVMX_PKO_PDM_CFG (0x0001540000800000ull) 182 #define CVMX_PKO_PDM_CFG_DBG (0x0001540000800FF8ull) 183 #define CVMX_PKO_PDM_CP_DBG (0x0001540000800190ull) 184 #define CVMX_PKO_PDM_DQX_MINPAD(offset) (0x00015400008F0000ull + ((offset) & 1023) * 8) 185 #define CVMX_PKO_PDM_DRPBUF_DBG (0x00015400008000B0ull) 186 #define CVMX_PKO_PDM_DWPBUF_DBG (0x00015400008000A8ull) 187 #define CVMX_PKO_PDM_ECC_CTL0 (0x00015400008FFFD0ull) 188 #define CVMX_PKO_PDM_ECC_CTL1 (0x00015400008FFFD8ull) 189 #define CVMX_PKO_PDM_ECC_DBE_STS0 (0x00015400008FFFF0ull) 190 #define CVMX_PKO_PDM_ECC_DBE_STS_CMB0 (0x00015400008FFFE0ull) 191 #define CVMX_PKO_PDM_ECC_SBE_STS0 (0x00015400008FFFF8ull) 192 #define CVMX_PKO_PDM_ECC_SBE_STS_CMB0 (0x00015400008FFFE8ull) 193 #define CVMX_PKO_PDM_FILLB_DBG0 (0x00015400008002A0ull) 194 #define CVMX_PKO_PDM_FILLB_DBG1 (0x00015400008002A8ull) 195 #define CVMX_PKO_PDM_FILLB_DBG2 (0x00015400008002B0ull) 196 #define CVMX_PKO_PDM_FLSHB_DBG0 (0x00015400008002B8ull) 197 #define CVMX_PKO_PDM_FLSHB_DBG1 (0x00015400008002C0ull) 198 #define CVMX_PKO_PDM_INTF_DBG_RD (0x0001540000900F20ull) 199 #define CVMX_PKO_PDM_ISRD_DBG (0x0001540000800090ull) 200 #define CVMX_PKO_PDM_ISRD_DBG_DQ (0x0001540000800290ull) 201 #define CVMX_PKO_PDM_ISRM_DBG (0x0001540000800098ull) 202 #define CVMX_PKO_PDM_ISRM_DBG_DQ (0x0001540000800298ull) 203 #define CVMX_PKO_PDM_MEM_ADDR (0x0001540000800018ull) 204 #define CVMX_PKO_PDM_MEM_DATA (0x0001540000800010ull) 205 #define CVMX_PKO_PDM_MEM_RW_CTL (0x0001540000800020ull) 206 #define CVMX_PKO_PDM_MEM_RW_STS (0x0001540000800028ull) 207 #define CVMX_PKO_PDM_MWPBUF_DBG (0x00015400008000A0ull) 208 #define CVMX_PKO_PDM_STS (0x0001540000800008ull) 209 #define CVMX_PKO_PEB_BIST_STATUS (0x0001540000900D00ull) 210 #define CVMX_PKO_PEB_ECC_CTL0 (0x00015400009FFFD0ull) 211 #define CVMX_PKO_PEB_ECC_CTL1 (0x00015400009FFFA8ull) 212 #define CVMX_PKO_PEB_ECC_DBE_STS0 (0x00015400009FFFF0ull) 213 #define CVMX_PKO_PEB_ECC_DBE_STS_CMB0 (0x00015400009FFFD8ull) 214 #define CVMX_PKO_PEB_ECC_SBE_STS0 (0x00015400009FFFF8ull) 215 #define CVMX_PKO_PEB_ECC_SBE_STS_CMB0 (0x00015400009FFFE8ull) 216 #define CVMX_PKO_PEB_ECO (0x0001540000901000ull) 217 #define CVMX_PKO_PEB_ERR_INT (0x0001540000900C00ull) 218 #define CVMX_PKO_PEB_EXT_HDR_DEF_ERR_INFO (0x0001540000900C08ull) 219 #define CVMX_PKO_PEB_FCS_SOP_ERR_INFO (0x0001540000900C18ull) 220 #define CVMX_PKO_PEB_JUMP_DEF_ERR_INFO (0x0001540000900C10ull) 221 #define CVMX_PKO_PEB_MACX_CFG_WR_ERR_INFO (0x0001540000900C50ull) 222 #define CVMX_PKO_PEB_MAX_LINK_ERR_INFO (0x0001540000900C48ull) 223 #define CVMX_PKO_PEB_NCB_CFG (0x0001540000900308ull) 224 #define CVMX_PKO_PEB_PAD_ERR_INFO (0x0001540000900C28ull) 225 #define CVMX_PKO_PEB_PSE_FIFO_ERR_INFO (0x0001540000900C20ull) 226 #define CVMX_PKO_PEB_SUBD_ADDR_ERR_INFO (0x0001540000900C38ull) 227 #define CVMX_PKO_PEB_SUBD_SIZE_ERR_INFO (0x0001540000900C40ull) 228 #define CVMX_PKO_PEB_TRUNC_ERR_INFO (0x0001540000900C30ull) 229 #define CVMX_PKO_PEB_TSO_CFG (0x0001540000900310ull) 230 #define CVMX_PKO_PQA_DEBUG (0x0001540000000128ull) 231 #define CVMX_PKO_PQB_DEBUG (0x0001540000000130ull) 232 #define CVMX_PKO_PQ_CSR_BUS_DEBUG (0x00015400000001F8ull) 233 #define CVMX_PKO_PQ_DEBUG_GREEN (0x0001540000000058ull) 234 #define CVMX_PKO_PQ_DEBUG_LINKS (0x0001540000000068ull) 235 #define CVMX_PKO_PQ_DEBUG_YELLOW (0x0001540000000060ull) 236 #define CVMX_PKO_PSE_DQ_BIST_STATUS (0x0001540000300138ull) 237 #define CVMX_PKO_PSE_DQ_ECC_CTL0 (0x0001540000300100ull) 238 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS0 (0x0001540000300118ull) 239 #define CVMX_PKO_PSE_DQ_ECC_DBE_STS_CMB0 (0x0001540000300120ull) 240 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS0 (0x0001540000300108ull) 241 #define CVMX_PKO_PSE_DQ_ECC_SBE_STS_CMB0 (0x0001540000300110ull) 242 #define CVMX_PKO_PSE_PQ_BIST_STATUS (0x0001540000000138ull) 243 #define CVMX_PKO_PSE_PQ_ECC_CTL0 (0x0001540000000100ull) 244 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS0 (0x0001540000000118ull) 245 #define CVMX_PKO_PSE_PQ_ECC_DBE_STS_CMB0 (0x0001540000000120ull) 246 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS0 (0x0001540000000108ull) 247 #define CVMX_PKO_PSE_PQ_ECC_SBE_STS_CMB0 (0x0001540000000110ull) 248 #define CVMX_PKO_PSE_SQ1_BIST_STATUS (0x0001540000080138ull) 249 #define CVMX_PKO_PSE_SQ1_ECC_CTL0 (0x0001540000080100ull) 250 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS0 (0x0001540000080118ull) 251 #define CVMX_PKO_PSE_SQ1_ECC_DBE_STS_CMB0 (0x0001540000080120ull) 252 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS0 (0x0001540000080108ull) 253 #define CVMX_PKO_PSE_SQ1_ECC_SBE_STS_CMB0 (0x0001540000080110ull) 254 #define CVMX_PKO_PSE_SQ2_BIST_STATUS (0x0001540000100138ull) 255 #define CVMX_PKO_PSE_SQ2_ECC_CTL0 (0x0001540000100100ull) 256 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS0 (0x0001540000100118ull) 257 #define CVMX_PKO_PSE_SQ2_ECC_DBE_STS_CMB0 (0x0001540000100120ull) 258 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS0 (0x0001540000100108ull) 259 #define CVMX_PKO_PSE_SQ2_ECC_SBE_STS_CMB0 (0x0001540000100110ull) 260 #define CVMX_PKO_PSE_SQ3_BIST_STATUS (0x0001540000180138ull) 261 #define CVMX_PKO_PSE_SQ3_ECC_CTL0 (0x0001540000180100ull) 262 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS0 (0x0001540000180118ull) 263 #define CVMX_PKO_PSE_SQ3_ECC_DBE_STS_CMB0 (0x0001540000180120ull) 264 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS0 (0x0001540000180108ull) 265 #define CVMX_PKO_PSE_SQ3_ECC_SBE_STS_CMB0 (0x0001540000180110ull) 266 #define CVMX_PKO_PSE_SQ4_BIST_STATUS (0x0001540000200138ull) 267 #define CVMX_PKO_PSE_SQ4_ECC_CTL0 (0x0001540000200100ull) 268 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS0 (0x0001540000200118ull) 269 #define CVMX_PKO_PSE_SQ4_ECC_DBE_STS_CMB0 (0x0001540000200120ull) 270 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS0 (0x0001540000200108ull) 271 #define CVMX_PKO_PSE_SQ4_ECC_SBE_STS_CMB0 (0x0001540000200110ull) 272 #define CVMX_PKO_PSE_SQ5_BIST_STATUS (0x0001540000280138ull) 273 #define CVMX_PKO_PSE_SQ5_ECC_CTL0 (0x0001540000280100ull) 274 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS0 (0x0001540000280118ull) 275 #define CVMX_PKO_PSE_SQ5_ECC_DBE_STS_CMB0 (0x0001540000280120ull) 276 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS0 (0x0001540000280108ull) 277 #define CVMX_PKO_PSE_SQ5_ECC_SBE_STS_CMB0 (0x0001540000280110ull) 278 #define CVMX_PKO_PTFX_STATUS(offset) (0x0001540000900100ull + ((offset) & 31) * 8) 279 #define CVMX_PKO_PTF_IOBP_CFG (0x0001540000900300ull) 280 #define CVMX_PKO_PTGFX_CFG(offset) (0x0001540000900200ull + ((offset) & 7) * 8) 281 #define CVMX_PKO_REG_BIST_RESULT (0x0001180050000080ull) 282 #define CVMX_PKO_REG_CMD_BUF (0x0001180050000010ull) 283 #define CVMX_PKO_REG_CRC_CTLX(offset) (0x0001180050000028ull + ((offset) & 1) * 8) 284 #define CVMX_PKO_REG_CRC_ENABLE (0x0001180050000020ull) 285 #define CVMX_PKO_REG_CRC_IVX(offset) (0x0001180050000038ull + ((offset) & 1) * 8) 286 #define CVMX_PKO_REG_DEBUG0 (0x0001180050000098ull) 287 #define CVMX_PKO_REG_DEBUG1 (0x00011800500000A0ull) 288 #define CVMX_PKO_REG_DEBUG2 (0x00011800500000A8ull) 289 #define CVMX_PKO_REG_DEBUG3 (0x00011800500000B0ull) 290 #define CVMX_PKO_REG_DEBUG4 (0x00011800500000B8ull) 291 #define CVMX_PKO_REG_ENGINE_INFLIGHT (0x0001180050000050ull) 292 #define CVMX_PKO_REG_ENGINE_INFLIGHT1 (0x0001180050000318ull) 293 #define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (0x0001180050000300ull + ((offset) & 1) * 8) 294 #define CVMX_PKO_REG_ENGINE_THRESH (0x0001180050000058ull) 295 #define CVMX_PKO_REG_ERROR (0x0001180050000088ull) 296 #define CVMX_PKO_REG_FLAGS (0x0001180050000000ull) 297 #define CVMX_PKO_REG_GMX_PORT_MODE (0x0001180050000018ull) 298 #define CVMX_PKO_REG_INT_MASK (0x0001180050000090ull) 299 #define CVMX_PKO_REG_LOOPBACK_BPID (0x0001180050000118ull) 300 #define CVMX_PKO_REG_LOOPBACK_PKIND (0x0001180050000068ull) 301 #define CVMX_PKO_REG_MIN_PKT (0x0001180050000070ull) 302 #define CVMX_PKO_REG_PREEMPT (0x0001180050000110ull) 303 #define CVMX_PKO_REG_QUEUE_MODE (0x0001180050000048ull) 304 #define CVMX_PKO_REG_QUEUE_PREEMPT (0x0001180050000108ull) 305 #define CVMX_PKO_REG_QUEUE_PTRS1 (0x0001180050000100ull) 306 #define CVMX_PKO_REG_READ_IDX (0x0001180050000008ull) 307 #define CVMX_PKO_REG_THROTTLE (0x0001180050000078ull) 308 #define CVMX_PKO_REG_TIMESTAMP (0x0001180050000060ull) 309 #define CVMX_PKO_SHAPER_CFG (0x00015400000800F8ull) 310 #define CVMX_PKO_STATE_UID_IN_USEX_RD(offset) (0x0001540000900F00ull + ((offset) & 3) * 8) 311 #define CVMX_PKO_STATUS (0x0001540000D00000ull) 312 #define CVMX_PKO_TXFX_PKT_CNT_RD(offset) (0x0001540000900E00ull + ((offset) & 31) * 8) 313 314 /** 315 * cvmx_pko_channel_level 316 */ 317 union cvmx_pko_channel_level { 318 u64 u64; 319 struct cvmx_pko_channel_level_s { 320 u64 reserved_1_63 : 63; 321 u64 cc_level : 1; 322 } s; 323 struct cvmx_pko_channel_level_s cn73xx; 324 struct cvmx_pko_channel_level_s cn78xx; 325 struct cvmx_pko_channel_level_s cn78xxp1; 326 struct cvmx_pko_channel_level_s cnf75xx; 327 }; 328 329 typedef union cvmx_pko_channel_level cvmx_pko_channel_level_t; 330 331 /** 332 * cvmx_pko_dpfi_ena 333 */ 334 union cvmx_pko_dpfi_ena { 335 u64 u64; 336 struct cvmx_pko_dpfi_ena_s { 337 u64 reserved_1_63 : 63; 338 u64 enable : 1; 339 } s; 340 struct cvmx_pko_dpfi_ena_s cn73xx; 341 struct cvmx_pko_dpfi_ena_s cn78xx; 342 struct cvmx_pko_dpfi_ena_s cn78xxp1; 343 struct cvmx_pko_dpfi_ena_s cnf75xx; 344 }; 345 346 typedef union cvmx_pko_dpfi_ena cvmx_pko_dpfi_ena_t; 347 348 /** 349 * cvmx_pko_dpfi_flush 350 */ 351 union cvmx_pko_dpfi_flush { 352 u64 u64; 353 struct cvmx_pko_dpfi_flush_s { 354 u64 reserved_1_63 : 63; 355 u64 flush_en : 1; 356 } s; 357 struct cvmx_pko_dpfi_flush_s cn73xx; 358 struct cvmx_pko_dpfi_flush_s cn78xx; 359 struct cvmx_pko_dpfi_flush_s cn78xxp1; 360 struct cvmx_pko_dpfi_flush_s cnf75xx; 361 }; 362 363 typedef union cvmx_pko_dpfi_flush cvmx_pko_dpfi_flush_t; 364 365 /** 366 * cvmx_pko_dpfi_fpa_aura 367 */ 368 union cvmx_pko_dpfi_fpa_aura { 369 u64 u64; 370 struct cvmx_pko_dpfi_fpa_aura_s { 371 u64 reserved_12_63 : 52; 372 u64 node : 2; 373 u64 laura : 10; 374 } s; 375 struct cvmx_pko_dpfi_fpa_aura_s cn73xx; 376 struct cvmx_pko_dpfi_fpa_aura_s cn78xx; 377 struct cvmx_pko_dpfi_fpa_aura_s cn78xxp1; 378 struct cvmx_pko_dpfi_fpa_aura_s cnf75xx; 379 }; 380 381 typedef union cvmx_pko_dpfi_fpa_aura cvmx_pko_dpfi_fpa_aura_t; 382 383 /** 384 * cvmx_pko_dpfi_status 385 */ 386 union cvmx_pko_dpfi_status { 387 u64 u64; 388 struct cvmx_pko_dpfi_status_s { 389 u64 ptr_cnt : 32; 390 u64 reserved_27_31 : 5; 391 u64 xpd_fif_cnt : 4; 392 u64 dalc_fif_cnt : 4; 393 u64 alc_fif_cnt : 5; 394 u64 reserved_13_13 : 1; 395 u64 isrd_ptr1_rtn_full : 1; 396 u64 isrd_ptr0_rtn_full : 1; 397 u64 isrm_ptr1_rtn_full : 1; 398 u64 isrm_ptr0_rtn_full : 1; 399 u64 isrd_ptr1_val : 1; 400 u64 isrd_ptr0_val : 1; 401 u64 isrm_ptr1_val : 1; 402 u64 isrm_ptr0_val : 1; 403 u64 ptr_req_pend : 1; 404 u64 ptr_rtn_pend : 1; 405 u64 fpa_empty : 1; 406 u64 dpfi_empty : 1; 407 u64 cache_flushed : 1; 408 } s; 409 struct cvmx_pko_dpfi_status_s cn73xx; 410 struct cvmx_pko_dpfi_status_s cn78xx; 411 struct cvmx_pko_dpfi_status_cn78xxp1 { 412 u64 ptr_cnt : 32; 413 u64 reserved_13_31 : 19; 414 u64 isrd_ptr1_rtn_full : 1; 415 u64 isrd_ptr0_rtn_full : 1; 416 u64 isrm_ptr1_rtn_full : 1; 417 u64 isrm_ptr0_rtn_full : 1; 418 u64 isrd_ptr1_val : 1; 419 u64 isrd_ptr0_val : 1; 420 u64 isrm_ptr1_val : 1; 421 u64 isrm_ptr0_val : 1; 422 u64 ptr_req_pend : 1; 423 u64 ptr_rtn_pend : 1; 424 u64 fpa_empty : 1; 425 u64 dpfi_empty : 1; 426 u64 cache_flushed : 1; 427 } cn78xxp1; 428 struct cvmx_pko_dpfi_status_s cnf75xx; 429 }; 430 431 typedef union cvmx_pko_dpfi_status cvmx_pko_dpfi_status_t; 432 433 /** 434 * cvmx_pko_dq#_bytes 435 * 436 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES. 437 * 438 */ 439 union cvmx_pko_dqx_bytes { 440 u64 u64; 441 struct cvmx_pko_dqx_bytes_s { 442 u64 reserved_48_63 : 16; 443 u64 count : 48; 444 } s; 445 struct cvmx_pko_dqx_bytes_s cn73xx; 446 struct cvmx_pko_dqx_bytes_s cn78xx; 447 struct cvmx_pko_dqx_bytes_s cn78xxp1; 448 struct cvmx_pko_dqx_bytes_s cnf75xx; 449 }; 450 451 typedef union cvmx_pko_dqx_bytes cvmx_pko_dqx_bytes_t; 452 453 /** 454 * cvmx_pko_dq#_cir 455 * 456 * This register has the same bit fields as PKO_L1_SQ()_CIR. 457 * 458 */ 459 union cvmx_pko_dqx_cir { 460 u64 u64; 461 struct cvmx_pko_dqx_cir_s { 462 u64 reserved_41_63 : 23; 463 u64 burst_exponent : 4; 464 u64 burst_mantissa : 8; 465 u64 reserved_17_28 : 12; 466 u64 rate_divider_exponent : 4; 467 u64 rate_exponent : 4; 468 u64 rate_mantissa : 8; 469 u64 enable : 1; 470 } s; 471 struct cvmx_pko_dqx_cir_s cn73xx; 472 struct cvmx_pko_dqx_cir_s cn78xx; 473 struct cvmx_pko_dqx_cir_s cn78xxp1; 474 struct cvmx_pko_dqx_cir_s cnf75xx; 475 }; 476 477 typedef union cvmx_pko_dqx_cir cvmx_pko_dqx_cir_t; 478 479 /** 480 * cvmx_pko_dq#_dropped_bytes 481 * 482 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES. 483 * 484 */ 485 union cvmx_pko_dqx_dropped_bytes { 486 u64 u64; 487 struct cvmx_pko_dqx_dropped_bytes_s { 488 u64 reserved_48_63 : 16; 489 u64 count : 48; 490 } s; 491 struct cvmx_pko_dqx_dropped_bytes_s cn73xx; 492 struct cvmx_pko_dqx_dropped_bytes_s cn78xx; 493 struct cvmx_pko_dqx_dropped_bytes_s cn78xxp1; 494 struct cvmx_pko_dqx_dropped_bytes_s cnf75xx; 495 }; 496 497 typedef union cvmx_pko_dqx_dropped_bytes cvmx_pko_dqx_dropped_bytes_t; 498 499 /** 500 * cvmx_pko_dq#_dropped_packets 501 * 502 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS. 503 * 504 */ 505 union cvmx_pko_dqx_dropped_packets { 506 u64 u64; 507 struct cvmx_pko_dqx_dropped_packets_s { 508 u64 reserved_40_63 : 24; 509 u64 count : 40; 510 } s; 511 struct cvmx_pko_dqx_dropped_packets_s cn73xx; 512 struct cvmx_pko_dqx_dropped_packets_s cn78xx; 513 struct cvmx_pko_dqx_dropped_packets_s cn78xxp1; 514 struct cvmx_pko_dqx_dropped_packets_s cnf75xx; 515 }; 516 517 typedef union cvmx_pko_dqx_dropped_packets cvmx_pko_dqx_dropped_packets_t; 518 519 /** 520 * cvmx_pko_dq#_fifo 521 */ 522 union cvmx_pko_dqx_fifo { 523 u64 u64; 524 struct cvmx_pko_dqx_fifo_s { 525 u64 reserved_15_63 : 49; 526 u64 p_con : 1; 527 u64 head : 7; 528 u64 tail : 7; 529 } s; 530 struct cvmx_pko_dqx_fifo_s cn73xx; 531 struct cvmx_pko_dqx_fifo_s cn78xx; 532 struct cvmx_pko_dqx_fifo_s cn78xxp1; 533 struct cvmx_pko_dqx_fifo_s cnf75xx; 534 }; 535 536 typedef union cvmx_pko_dqx_fifo cvmx_pko_dqx_fifo_t; 537 538 /** 539 * cvmx_pko_dq#_packets 540 * 541 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS. 542 * 543 */ 544 union cvmx_pko_dqx_packets { 545 u64 u64; 546 struct cvmx_pko_dqx_packets_s { 547 u64 reserved_40_63 : 24; 548 u64 count : 40; 549 } s; 550 struct cvmx_pko_dqx_packets_s cn73xx; 551 struct cvmx_pko_dqx_packets_s cn78xx; 552 struct cvmx_pko_dqx_packets_s cn78xxp1; 553 struct cvmx_pko_dqx_packets_s cnf75xx; 554 }; 555 556 typedef union cvmx_pko_dqx_packets cvmx_pko_dqx_packets_t; 557 558 /** 559 * cvmx_pko_dq#_pick 560 * 561 * This CSR contains the meta for the DQ, and is for debug and reconfiguration 562 * only and should never be written. See also PKO_META_DESC_S. 563 */ 564 union cvmx_pko_dqx_pick { 565 u64 u64; 566 struct cvmx_pko_dqx_pick_s { 567 u64 dq : 10; 568 u64 color : 2; 569 u64 child : 10; 570 u64 bubble : 1; 571 u64 p_con : 1; 572 u64 c_con : 1; 573 u64 uid : 7; 574 u64 jump : 1; 575 u64 fpd : 1; 576 u64 ds : 1; 577 u64 adjust : 9; 578 u64 pir_dis : 1; 579 u64 cir_dis : 1; 580 u64 red_algo_override : 2; 581 u64 length : 16; 582 } s; 583 struct cvmx_pko_dqx_pick_s cn73xx; 584 struct cvmx_pko_dqx_pick_s cn78xx; 585 struct cvmx_pko_dqx_pick_s cn78xxp1; 586 struct cvmx_pko_dqx_pick_s cnf75xx; 587 }; 588 589 typedef union cvmx_pko_dqx_pick cvmx_pko_dqx_pick_t; 590 591 /** 592 * cvmx_pko_dq#_pir 593 * 594 * This register has the same bit fields as PKO_L1_SQ()_CIR. 595 * 596 */ 597 union cvmx_pko_dqx_pir { 598 u64 u64; 599 struct cvmx_pko_dqx_pir_s { 600 u64 reserved_41_63 : 23; 601 u64 burst_exponent : 4; 602 u64 burst_mantissa : 8; 603 u64 reserved_17_28 : 12; 604 u64 rate_divider_exponent : 4; 605 u64 rate_exponent : 4; 606 u64 rate_mantissa : 8; 607 u64 enable : 1; 608 } s; 609 struct cvmx_pko_dqx_pir_s cn73xx; 610 struct cvmx_pko_dqx_pir_s cn78xx; 611 struct cvmx_pko_dqx_pir_s cn78xxp1; 612 struct cvmx_pko_dqx_pir_s cnf75xx; 613 }; 614 615 typedef union cvmx_pko_dqx_pir cvmx_pko_dqx_pir_t; 616 617 /** 618 * cvmx_pko_dq#_pointers 619 * 620 * This register has the same bit fields as PKO_L3_SQ(0..255)_POINTERS. 621 * 622 */ 623 union cvmx_pko_dqx_pointers { 624 u64 u64; 625 struct cvmx_pko_dqx_pointers_s { 626 u64 reserved_26_63 : 38; 627 u64 prev : 10; 628 u64 reserved_10_15 : 6; 629 u64 next : 10; 630 } s; 631 struct cvmx_pko_dqx_pointers_cn73xx { 632 u64 reserved_24_63 : 40; 633 u64 prev : 8; 634 u64 reserved_8_15 : 8; 635 u64 next : 8; 636 } cn73xx; 637 struct cvmx_pko_dqx_pointers_s cn78xx; 638 struct cvmx_pko_dqx_pointers_s cn78xxp1; 639 struct cvmx_pko_dqx_pointers_cn73xx cnf75xx; 640 }; 641 642 typedef union cvmx_pko_dqx_pointers cvmx_pko_dqx_pointers_t; 643 644 /** 645 * cvmx_pko_dq#_sched_state 646 * 647 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE. 648 * 649 */ 650 union cvmx_pko_dqx_sched_state { 651 u64 u64; 652 struct cvmx_pko_dqx_sched_state_s { 653 u64 reserved_25_63 : 39; 654 u64 rr_count : 25; 655 } s; 656 struct cvmx_pko_dqx_sched_state_s cn73xx; 657 struct cvmx_pko_dqx_sched_state_s cn78xx; 658 struct cvmx_pko_dqx_sched_state_s cn78xxp1; 659 struct cvmx_pko_dqx_sched_state_s cnf75xx; 660 }; 661 662 typedef union cvmx_pko_dqx_sched_state cvmx_pko_dqx_sched_state_t; 663 664 /** 665 * cvmx_pko_dq#_schedule 666 * 667 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE. 668 * 669 */ 670 union cvmx_pko_dqx_schedule { 671 u64 u64; 672 struct cvmx_pko_dqx_schedule_s { 673 u64 reserved_28_63 : 36; 674 u64 prio : 4; 675 u64 rr_quantum : 24; 676 } s; 677 struct cvmx_pko_dqx_schedule_s cn73xx; 678 struct cvmx_pko_dqx_schedule_s cn78xx; 679 struct cvmx_pko_dqx_schedule_s cn78xxp1; 680 struct cvmx_pko_dqx_schedule_s cnf75xx; 681 }; 682 683 typedef union cvmx_pko_dqx_schedule cvmx_pko_dqx_schedule_t; 684 685 /** 686 * cvmx_pko_dq#_shape 687 * 688 * This register has the same bit fields as PKO_L3_SQ()_SHAPE. 689 * 690 */ 691 union cvmx_pko_dqx_shape { 692 u64 u64; 693 struct cvmx_pko_dqx_shape_s { 694 u64 reserved_27_63 : 37; 695 u64 schedule_list : 2; 696 u64 length_disable : 1; 697 u64 reserved_13_23 : 11; 698 u64 yellow_disable : 1; 699 u64 red_disable : 1; 700 u64 red_algo : 2; 701 u64 adjust : 9; 702 } s; 703 struct cvmx_pko_dqx_shape_s cn73xx; 704 struct cvmx_pko_dqx_shape_cn78xx { 705 u64 reserved_25_63 : 39; 706 u64 length_disable : 1; 707 u64 reserved_13_23 : 11; 708 u64 yellow_disable : 1; 709 u64 red_disable : 1; 710 u64 red_algo : 2; 711 u64 adjust : 9; 712 } cn78xx; 713 struct cvmx_pko_dqx_shape_cn78xx cn78xxp1; 714 struct cvmx_pko_dqx_shape_s cnf75xx; 715 }; 716 717 typedef union cvmx_pko_dqx_shape cvmx_pko_dqx_shape_t; 718 719 /** 720 * cvmx_pko_dq#_shape_state 721 * 722 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE. 723 * This register must not be written during normal operation. 724 */ 725 union cvmx_pko_dqx_shape_state { 726 u64 u64; 727 struct cvmx_pko_dqx_shape_state_s { 728 u64 reserved_60_63 : 4; 729 u64 tw_timestamp : 6; 730 u64 color : 2; 731 u64 pir_accum : 26; 732 u64 cir_accum : 26; 733 } s; 734 struct cvmx_pko_dqx_shape_state_s cn73xx; 735 struct cvmx_pko_dqx_shape_state_s cn78xx; 736 struct cvmx_pko_dqx_shape_state_s cn78xxp1; 737 struct cvmx_pko_dqx_shape_state_s cnf75xx; 738 }; 739 740 typedef union cvmx_pko_dqx_shape_state cvmx_pko_dqx_shape_state_t; 741 742 /** 743 * cvmx_pko_dq#_sw_xoff 744 * 745 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF. 746 * 747 */ 748 union cvmx_pko_dqx_sw_xoff { 749 u64 u64; 750 struct cvmx_pko_dqx_sw_xoff_s { 751 u64 reserved_4_63 : 60; 752 u64 drain_irq : 1; 753 u64 drain_null_link : 1; 754 u64 drain : 1; 755 u64 xoff : 1; 756 } s; 757 struct cvmx_pko_dqx_sw_xoff_s cn73xx; 758 struct cvmx_pko_dqx_sw_xoff_s cn78xx; 759 struct cvmx_pko_dqx_sw_xoff_s cn78xxp1; 760 struct cvmx_pko_dqx_sw_xoff_s cnf75xx; 761 }; 762 763 typedef union cvmx_pko_dqx_sw_xoff cvmx_pko_dqx_sw_xoff_t; 764 765 /** 766 * cvmx_pko_dq#_topology 767 */ 768 union cvmx_pko_dqx_topology { 769 u64 u64; 770 struct cvmx_pko_dqx_topology_s { 771 u64 reserved_26_63 : 38; 772 u64 parent : 10; 773 u64 reserved_0_15 : 16; 774 } s; 775 struct cvmx_pko_dqx_topology_cn73xx { 776 u64 reserved_24_63 : 40; 777 u64 parent : 8; 778 u64 reserved_0_15 : 16; 779 } cn73xx; 780 struct cvmx_pko_dqx_topology_s cn78xx; 781 struct cvmx_pko_dqx_topology_s cn78xxp1; 782 struct cvmx_pko_dqx_topology_cn73xx cnf75xx; 783 }; 784 785 typedef union cvmx_pko_dqx_topology cvmx_pko_dqx_topology_t; 786 787 /** 788 * cvmx_pko_dq#_wm_buf_cnt 789 */ 790 union cvmx_pko_dqx_wm_buf_cnt { 791 u64 u64; 792 struct cvmx_pko_dqx_wm_buf_cnt_s { 793 u64 reserved_36_63 : 28; 794 u64 count : 36; 795 } s; 796 struct cvmx_pko_dqx_wm_buf_cnt_s cn73xx; 797 struct cvmx_pko_dqx_wm_buf_cnt_s cn78xx; 798 struct cvmx_pko_dqx_wm_buf_cnt_s cn78xxp1; 799 struct cvmx_pko_dqx_wm_buf_cnt_s cnf75xx; 800 }; 801 802 typedef union cvmx_pko_dqx_wm_buf_cnt cvmx_pko_dqx_wm_buf_cnt_t; 803 804 /** 805 * cvmx_pko_dq#_wm_buf_ctl 806 */ 807 union cvmx_pko_dqx_wm_buf_ctl { 808 u64 u64; 809 struct cvmx_pko_dqx_wm_buf_ctl_s { 810 u64 reserved_51_63 : 13; 811 u64 enable : 1; 812 u64 reserved_49_49 : 1; 813 u64 intr : 1; 814 u64 reserved_36_47 : 12; 815 u64 threshold : 36; 816 } s; 817 struct cvmx_pko_dqx_wm_buf_ctl_s cn73xx; 818 struct cvmx_pko_dqx_wm_buf_ctl_s cn78xx; 819 struct cvmx_pko_dqx_wm_buf_ctl_s cn78xxp1; 820 struct cvmx_pko_dqx_wm_buf_ctl_s cnf75xx; 821 }; 822 823 typedef union cvmx_pko_dqx_wm_buf_ctl cvmx_pko_dqx_wm_buf_ctl_t; 824 825 /** 826 * cvmx_pko_dq#_wm_buf_ctl_w1c 827 */ 828 union cvmx_pko_dqx_wm_buf_ctl_w1c { 829 u64 u64; 830 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s { 831 u64 reserved_49_63 : 15; 832 u64 intr : 1; 833 u64 reserved_0_47 : 48; 834 } s; 835 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn73xx; 836 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xx; 837 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cn78xxp1; 838 struct cvmx_pko_dqx_wm_buf_ctl_w1c_s cnf75xx; 839 }; 840 841 typedef union cvmx_pko_dqx_wm_buf_ctl_w1c cvmx_pko_dqx_wm_buf_ctl_w1c_t; 842 843 /** 844 * cvmx_pko_dq#_wm_cnt 845 */ 846 union cvmx_pko_dqx_wm_cnt { 847 u64 u64; 848 struct cvmx_pko_dqx_wm_cnt_s { 849 u64 reserved_48_63 : 16; 850 u64 count : 48; 851 } s; 852 struct cvmx_pko_dqx_wm_cnt_s cn73xx; 853 struct cvmx_pko_dqx_wm_cnt_s cn78xx; 854 struct cvmx_pko_dqx_wm_cnt_s cn78xxp1; 855 struct cvmx_pko_dqx_wm_cnt_s cnf75xx; 856 }; 857 858 typedef union cvmx_pko_dqx_wm_cnt cvmx_pko_dqx_wm_cnt_t; 859 860 /** 861 * cvmx_pko_dq#_wm_ctl 862 */ 863 union cvmx_pko_dqx_wm_ctl { 864 u64 u64; 865 struct cvmx_pko_dqx_wm_ctl_s { 866 u64 reserved_52_63 : 12; 867 u64 ncb_query_rsp : 1; 868 u64 enable : 1; 869 u64 kind : 1; 870 u64 intr : 1; 871 u64 threshold : 48; 872 } s; 873 struct cvmx_pko_dqx_wm_ctl_s cn73xx; 874 struct cvmx_pko_dqx_wm_ctl_s cn78xx; 875 struct cvmx_pko_dqx_wm_ctl_s cn78xxp1; 876 struct cvmx_pko_dqx_wm_ctl_s cnf75xx; 877 }; 878 879 typedef union cvmx_pko_dqx_wm_ctl cvmx_pko_dqx_wm_ctl_t; 880 881 /** 882 * cvmx_pko_dq#_wm_ctl_w1c 883 */ 884 union cvmx_pko_dqx_wm_ctl_w1c { 885 u64 u64; 886 struct cvmx_pko_dqx_wm_ctl_w1c_s { 887 u64 reserved_49_63 : 15; 888 u64 intr : 1; 889 u64 reserved_0_47 : 48; 890 } s; 891 struct cvmx_pko_dqx_wm_ctl_w1c_s cn73xx; 892 struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xx; 893 struct cvmx_pko_dqx_wm_ctl_w1c_s cn78xxp1; 894 struct cvmx_pko_dqx_wm_ctl_w1c_s cnf75xx; 895 }; 896 897 typedef union cvmx_pko_dqx_wm_ctl_w1c cvmx_pko_dqx_wm_ctl_w1c_t; 898 899 /** 900 * cvmx_pko_dq_csr_bus_debug 901 */ 902 union cvmx_pko_dq_csr_bus_debug { 903 u64 u64; 904 struct cvmx_pko_dq_csr_bus_debug_s { 905 u64 csr_bus_debug : 64; 906 } s; 907 struct cvmx_pko_dq_csr_bus_debug_s cn73xx; 908 struct cvmx_pko_dq_csr_bus_debug_s cn78xx; 909 struct cvmx_pko_dq_csr_bus_debug_s cn78xxp1; 910 struct cvmx_pko_dq_csr_bus_debug_s cnf75xx; 911 }; 912 913 typedef union cvmx_pko_dq_csr_bus_debug cvmx_pko_dq_csr_bus_debug_t; 914 915 /** 916 * cvmx_pko_dq_debug 917 */ 918 union cvmx_pko_dq_debug { 919 u64 u64; 920 struct cvmx_pko_dq_debug_s { 921 u64 dbg_vec : 64; 922 } s; 923 struct cvmx_pko_dq_debug_s cn73xx; 924 struct cvmx_pko_dq_debug_s cn78xx; 925 struct cvmx_pko_dq_debug_s cn78xxp1; 926 struct cvmx_pko_dq_debug_s cnf75xx; 927 }; 928 929 typedef union cvmx_pko_dq_debug cvmx_pko_dq_debug_t; 930 931 /** 932 * cvmx_pko_drain_irq 933 */ 934 union cvmx_pko_drain_irq { 935 u64 u64; 936 struct cvmx_pko_drain_irq_s { 937 u64 reserved_1_63 : 63; 938 u64 intr : 1; 939 } s; 940 struct cvmx_pko_drain_irq_s cn73xx; 941 struct cvmx_pko_drain_irq_s cn78xx; 942 struct cvmx_pko_drain_irq_s cn78xxp1; 943 struct cvmx_pko_drain_irq_s cnf75xx; 944 }; 945 946 typedef union cvmx_pko_drain_irq cvmx_pko_drain_irq_t; 947 948 /** 949 * cvmx_pko_enable 950 */ 951 union cvmx_pko_enable { 952 u64 u64; 953 struct cvmx_pko_enable_s { 954 u64 reserved_1_63 : 63; 955 u64 enable : 1; 956 } s; 957 struct cvmx_pko_enable_s cn73xx; 958 struct cvmx_pko_enable_s cn78xx; 959 struct cvmx_pko_enable_s cn78xxp1; 960 struct cvmx_pko_enable_s cnf75xx; 961 }; 962 963 typedef union cvmx_pko_enable cvmx_pko_enable_t; 964 965 /** 966 * cvmx_pko_format#_ctl 967 * 968 * Describes packet marking calculations for YELLOW and for RED_SEND packets. 969 * PKO_SEND_HDR_S[FORMAT] selects the CSR used for the packet descriptor. 970 * 971 * All the packet marking calculations assume big-endian bits within a byte. 972 * 973 * For example, if MARKPTR is 3 and [OFFSET] is 5 and the packet is YELLOW, 974 * the PKO marking hardware would do this: 975 * 976 * _ byte[3]<2:0> |= Y_VAL<3:1> 977 * _ byte[3]<2:0> &= ~Y_MASK<3:1> 978 * _ byte[4]<7> |= Y_VAL<0> 979 * _ byte[4]<7> &= ~Y_MASK<0> 980 * 981 * where byte[3] is the 3rd byte in the packet, and byte[4] the 4th. 982 * 983 * For another example, if MARKPTR is 3 and [OFFSET] is 0 and the packet is RED_SEND, 984 * 985 * _ byte[3]<7:4> |= R_VAL<3:0> 986 * _ byte[3]<7:4> &= ~R_MASK<3:0> 987 */ 988 union cvmx_pko_formatx_ctl { 989 u64 u64; 990 struct cvmx_pko_formatx_ctl_s { 991 u64 reserved_27_63 : 37; 992 u64 offset : 11; 993 u64 y_mask : 4; 994 u64 y_val : 4; 995 u64 r_mask : 4; 996 u64 r_val : 4; 997 } s; 998 struct cvmx_pko_formatx_ctl_s cn73xx; 999 struct cvmx_pko_formatx_ctl_s cn78xx; 1000 struct cvmx_pko_formatx_ctl_s cn78xxp1; 1001 struct cvmx_pko_formatx_ctl_s cnf75xx; 1002 }; 1003 1004 typedef union cvmx_pko_formatx_ctl cvmx_pko_formatx_ctl_t; 1005 1006 /** 1007 * cvmx_pko_l1_sq#_cir 1008 */ 1009 union cvmx_pko_l1_sqx_cir { 1010 u64 u64; 1011 struct cvmx_pko_l1_sqx_cir_s { 1012 u64 reserved_41_63 : 23; 1013 u64 burst_exponent : 4; 1014 u64 burst_mantissa : 8; 1015 u64 reserved_17_28 : 12; 1016 u64 rate_divider_exponent : 4; 1017 u64 rate_exponent : 4; 1018 u64 rate_mantissa : 8; 1019 u64 enable : 1; 1020 } s; 1021 struct cvmx_pko_l1_sqx_cir_s cn73xx; 1022 struct cvmx_pko_l1_sqx_cir_s cn78xx; 1023 struct cvmx_pko_l1_sqx_cir_s cn78xxp1; 1024 struct cvmx_pko_l1_sqx_cir_s cnf75xx; 1025 }; 1026 1027 typedef union cvmx_pko_l1_sqx_cir cvmx_pko_l1_sqx_cir_t; 1028 1029 /** 1030 * cvmx_pko_l1_sq#_dropped_bytes 1031 * 1032 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES. 1033 * 1034 */ 1035 union cvmx_pko_l1_sqx_dropped_bytes { 1036 u64 u64; 1037 struct cvmx_pko_l1_sqx_dropped_bytes_s { 1038 u64 reserved_48_63 : 16; 1039 u64 count : 48; 1040 } s; 1041 struct cvmx_pko_l1_sqx_dropped_bytes_s cn73xx; 1042 struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xx; 1043 struct cvmx_pko_l1_sqx_dropped_bytes_s cn78xxp1; 1044 struct cvmx_pko_l1_sqx_dropped_bytes_s cnf75xx; 1045 }; 1046 1047 typedef union cvmx_pko_l1_sqx_dropped_bytes cvmx_pko_l1_sqx_dropped_bytes_t; 1048 1049 /** 1050 * cvmx_pko_l1_sq#_dropped_packets 1051 * 1052 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS. 1053 * 1054 */ 1055 union cvmx_pko_l1_sqx_dropped_packets { 1056 u64 u64; 1057 struct cvmx_pko_l1_sqx_dropped_packets_s { 1058 u64 reserved_40_63 : 24; 1059 u64 count : 40; 1060 } s; 1061 struct cvmx_pko_l1_sqx_dropped_packets_s cn73xx; 1062 struct cvmx_pko_l1_sqx_dropped_packets_s cn78xx; 1063 struct cvmx_pko_l1_sqx_dropped_packets_s cn78xxp1; 1064 struct cvmx_pko_l1_sqx_dropped_packets_s cnf75xx; 1065 }; 1066 1067 typedef union cvmx_pko_l1_sqx_dropped_packets cvmx_pko_l1_sqx_dropped_packets_t; 1068 1069 /** 1070 * cvmx_pko_l1_sq#_green 1071 */ 1072 union cvmx_pko_l1_sqx_green { 1073 u64 u64; 1074 struct cvmx_pko_l1_sqx_green_s { 1075 u64 reserved_41_63 : 23; 1076 u64 rr_active : 1; 1077 u64 active_vec : 20; 1078 u64 reserved_19_19 : 1; 1079 u64 head : 9; 1080 u64 reserved_9_9 : 1; 1081 u64 tail : 9; 1082 } s; 1083 struct cvmx_pko_l1_sqx_green_s cn73xx; 1084 struct cvmx_pko_l1_sqx_green_s cn78xx; 1085 struct cvmx_pko_l1_sqx_green_s cn78xxp1; 1086 struct cvmx_pko_l1_sqx_green_s cnf75xx; 1087 }; 1088 1089 typedef union cvmx_pko_l1_sqx_green cvmx_pko_l1_sqx_green_t; 1090 1091 /** 1092 * cvmx_pko_l1_sq#_green_bytes 1093 */ 1094 union cvmx_pko_l1_sqx_green_bytes { 1095 u64 u64; 1096 struct cvmx_pko_l1_sqx_green_bytes_s { 1097 u64 reserved_48_63 : 16; 1098 u64 count : 48; 1099 } s; 1100 struct cvmx_pko_l1_sqx_green_bytes_s cn73xx; 1101 struct cvmx_pko_l1_sqx_green_bytes_s cn78xx; 1102 struct cvmx_pko_l1_sqx_green_bytes_s cn78xxp1; 1103 struct cvmx_pko_l1_sqx_green_bytes_s cnf75xx; 1104 }; 1105 1106 typedef union cvmx_pko_l1_sqx_green_bytes cvmx_pko_l1_sqx_green_bytes_t; 1107 1108 /** 1109 * cvmx_pko_l1_sq#_green_packets 1110 */ 1111 union cvmx_pko_l1_sqx_green_packets { 1112 u64 u64; 1113 struct cvmx_pko_l1_sqx_green_packets_s { 1114 u64 reserved_40_63 : 24; 1115 u64 count : 40; 1116 } s; 1117 struct cvmx_pko_l1_sqx_green_packets_s cn73xx; 1118 struct cvmx_pko_l1_sqx_green_packets_s cn78xx; 1119 struct cvmx_pko_l1_sqx_green_packets_s cn78xxp1; 1120 struct cvmx_pko_l1_sqx_green_packets_s cnf75xx; 1121 }; 1122 1123 typedef union cvmx_pko_l1_sqx_green_packets cvmx_pko_l1_sqx_green_packets_t; 1124 1125 /** 1126 * cvmx_pko_l1_sq#_link 1127 */ 1128 union cvmx_pko_l1_sqx_link { 1129 u64 u64; 1130 struct cvmx_pko_l1_sqx_link_s { 1131 u64 reserved_49_63 : 15; 1132 u64 link : 5; 1133 u64 reserved_32_43 : 12; 1134 u64 cc_word_cnt : 20; 1135 u64 cc_packet_cnt : 10; 1136 u64 cc_enable : 1; 1137 u64 reserved_0_0 : 1; 1138 } s; 1139 struct cvmx_pko_l1_sqx_link_cn73xx { 1140 u64 reserved_48_63 : 16; 1141 u64 link : 4; 1142 u64 reserved_32_43 : 12; 1143 u64 cc_word_cnt : 20; 1144 u64 cc_packet_cnt : 10; 1145 u64 cc_enable : 1; 1146 u64 reserved_0_0 : 1; 1147 } cn73xx; 1148 struct cvmx_pko_l1_sqx_link_s cn78xx; 1149 struct cvmx_pko_l1_sqx_link_s cn78xxp1; 1150 struct cvmx_pko_l1_sqx_link_cn73xx cnf75xx; 1151 }; 1152 1153 typedef union cvmx_pko_l1_sqx_link cvmx_pko_l1_sqx_link_t; 1154 1155 /** 1156 * cvmx_pko_l1_sq#_pick 1157 * 1158 * This CSR contains the meta for the L1 SQ, and is for debug and reconfiguration 1159 * only and should never be written. See also PKO_META_DESC_S. 1160 */ 1161 union cvmx_pko_l1_sqx_pick { 1162 u64 u64; 1163 struct cvmx_pko_l1_sqx_pick_s { 1164 u64 dq : 10; 1165 u64 color : 2; 1166 u64 child : 10; 1167 u64 bubble : 1; 1168 u64 p_con : 1; 1169 u64 c_con : 1; 1170 u64 uid : 7; 1171 u64 jump : 1; 1172 u64 fpd : 1; 1173 u64 ds : 1; 1174 u64 adjust : 9; 1175 u64 pir_dis : 1; 1176 u64 cir_dis : 1; 1177 u64 red_algo_override : 2; 1178 u64 length : 16; 1179 } s; 1180 struct cvmx_pko_l1_sqx_pick_s cn73xx; 1181 struct cvmx_pko_l1_sqx_pick_s cn78xx; 1182 struct cvmx_pko_l1_sqx_pick_s cn78xxp1; 1183 struct cvmx_pko_l1_sqx_pick_s cnf75xx; 1184 }; 1185 1186 typedef union cvmx_pko_l1_sqx_pick cvmx_pko_l1_sqx_pick_t; 1187 1188 /** 1189 * cvmx_pko_l1_sq#_red 1190 * 1191 * This register has the same bit fields as PKO_L1_SQ()_YELLOW. 1192 * 1193 */ 1194 union cvmx_pko_l1_sqx_red { 1195 u64 u64; 1196 struct cvmx_pko_l1_sqx_red_s { 1197 u64 reserved_19_63 : 45; 1198 u64 head : 9; 1199 u64 reserved_9_9 : 1; 1200 u64 tail : 9; 1201 } s; 1202 struct cvmx_pko_l1_sqx_red_s cn73xx; 1203 struct cvmx_pko_l1_sqx_red_s cn78xx; 1204 struct cvmx_pko_l1_sqx_red_s cn78xxp1; 1205 struct cvmx_pko_l1_sqx_red_s cnf75xx; 1206 }; 1207 1208 typedef union cvmx_pko_l1_sqx_red cvmx_pko_l1_sqx_red_t; 1209 1210 /** 1211 * cvmx_pko_l1_sq#_red_bytes 1212 * 1213 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES. 1214 * 1215 */ 1216 union cvmx_pko_l1_sqx_red_bytes { 1217 u64 u64; 1218 struct cvmx_pko_l1_sqx_red_bytes_s { 1219 u64 reserved_48_63 : 16; 1220 u64 count : 48; 1221 } s; 1222 struct cvmx_pko_l1_sqx_red_bytes_s cn73xx; 1223 struct cvmx_pko_l1_sqx_red_bytes_s cn78xx; 1224 struct cvmx_pko_l1_sqx_red_bytes_s cn78xxp1; 1225 struct cvmx_pko_l1_sqx_red_bytes_s cnf75xx; 1226 }; 1227 1228 typedef union cvmx_pko_l1_sqx_red_bytes cvmx_pko_l1_sqx_red_bytes_t; 1229 1230 /** 1231 * cvmx_pko_l1_sq#_red_packets 1232 * 1233 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS. 1234 * 1235 */ 1236 union cvmx_pko_l1_sqx_red_packets { 1237 u64 u64; 1238 struct cvmx_pko_l1_sqx_red_packets_s { 1239 u64 reserved_40_63 : 24; 1240 u64 count : 40; 1241 } s; 1242 struct cvmx_pko_l1_sqx_red_packets_s cn73xx; 1243 struct cvmx_pko_l1_sqx_red_packets_s cn78xx; 1244 struct cvmx_pko_l1_sqx_red_packets_s cn78xxp1; 1245 struct cvmx_pko_l1_sqx_red_packets_s cnf75xx; 1246 }; 1247 1248 typedef union cvmx_pko_l1_sqx_red_packets cvmx_pko_l1_sqx_red_packets_t; 1249 1250 /** 1251 * cvmx_pko_l1_sq#_schedule 1252 */ 1253 union cvmx_pko_l1_sqx_schedule { 1254 u64 u64; 1255 struct cvmx_pko_l1_sqx_schedule_s { 1256 u64 dummy : 40; 1257 u64 rr_quantum : 24; 1258 } s; 1259 struct cvmx_pko_l1_sqx_schedule_cn73xx { 1260 u64 reserved_24_63 : 40; 1261 u64 rr_quantum : 24; 1262 } cn73xx; 1263 struct cvmx_pko_l1_sqx_schedule_cn73xx cn78xx; 1264 struct cvmx_pko_l1_sqx_schedule_s cn78xxp1; 1265 struct cvmx_pko_l1_sqx_schedule_cn73xx cnf75xx; 1266 }; 1267 1268 typedef union cvmx_pko_l1_sqx_schedule cvmx_pko_l1_sqx_schedule_t; 1269 1270 /** 1271 * cvmx_pko_l1_sq#_shape 1272 */ 1273 union cvmx_pko_l1_sqx_shape { 1274 u64 u64; 1275 struct cvmx_pko_l1_sqx_shape_s { 1276 u64 reserved_25_63 : 39; 1277 u64 length_disable : 1; 1278 u64 reserved_18_23 : 6; 1279 u64 link : 5; 1280 u64 reserved_9_12 : 4; 1281 u64 adjust : 9; 1282 } s; 1283 struct cvmx_pko_l1_sqx_shape_cn73xx { 1284 u64 reserved_25_63 : 39; 1285 u64 length_disable : 1; 1286 u64 reserved_17_23 : 7; 1287 u64 link : 4; 1288 u64 reserved_9_12 : 4; 1289 u64 adjust : 9; 1290 } cn73xx; 1291 struct cvmx_pko_l1_sqx_shape_s cn78xx; 1292 struct cvmx_pko_l1_sqx_shape_s cn78xxp1; 1293 struct cvmx_pko_l1_sqx_shape_cn73xx cnf75xx; 1294 }; 1295 1296 typedef union cvmx_pko_l1_sqx_shape cvmx_pko_l1_sqx_shape_t; 1297 1298 /** 1299 * cvmx_pko_l1_sq#_shape_state 1300 * 1301 * This register must not be written during normal operation. 1302 * 1303 */ 1304 union cvmx_pko_l1_sqx_shape_state { 1305 u64 u64; 1306 struct cvmx_pko_l1_sqx_shape_state_s { 1307 u64 reserved_60_63 : 4; 1308 u64 tw_timestamp : 6; 1309 u64 color2 : 1; 1310 u64 color : 1; 1311 u64 reserved_26_51 : 26; 1312 u64 cir_accum : 26; 1313 } s; 1314 struct cvmx_pko_l1_sqx_shape_state_cn73xx { 1315 u64 reserved_60_63 : 4; 1316 u64 tw_timestamp : 6; 1317 u64 reserved_53_53 : 1; 1318 u64 color : 1; 1319 u64 reserved_26_51 : 26; 1320 u64 cir_accum : 26; 1321 } cn73xx; 1322 struct cvmx_pko_l1_sqx_shape_state_cn73xx cn78xx; 1323 struct cvmx_pko_l1_sqx_shape_state_s cn78xxp1; 1324 struct cvmx_pko_l1_sqx_shape_state_cn73xx cnf75xx; 1325 }; 1326 1327 typedef union cvmx_pko_l1_sqx_shape_state cvmx_pko_l1_sqx_shape_state_t; 1328 1329 /** 1330 * cvmx_pko_l1_sq#_sw_xoff 1331 */ 1332 union cvmx_pko_l1_sqx_sw_xoff { 1333 u64 u64; 1334 struct cvmx_pko_l1_sqx_sw_xoff_s { 1335 u64 reserved_4_63 : 60; 1336 u64 drain_irq : 1; 1337 u64 drain_null_link : 1; 1338 u64 drain : 1; 1339 u64 xoff : 1; 1340 } s; 1341 struct cvmx_pko_l1_sqx_sw_xoff_s cn73xx; 1342 struct cvmx_pko_l1_sqx_sw_xoff_s cn78xx; 1343 struct cvmx_pko_l1_sqx_sw_xoff_s cn78xxp1; 1344 struct cvmx_pko_l1_sqx_sw_xoff_s cnf75xx; 1345 }; 1346 1347 typedef union cvmx_pko_l1_sqx_sw_xoff cvmx_pko_l1_sqx_sw_xoff_t; 1348 1349 /** 1350 * cvmx_pko_l1_sq#_topology 1351 */ 1352 union cvmx_pko_l1_sqx_topology { 1353 u64 u64; 1354 struct cvmx_pko_l1_sqx_topology_s { 1355 u64 reserved_41_63 : 23; 1356 u64 prio_anchor : 9; 1357 u64 reserved_21_31 : 11; 1358 u64 link : 5; 1359 u64 reserved_5_15 : 11; 1360 u64 rr_prio : 4; 1361 u64 reserved_0_0 : 1; 1362 } s; 1363 struct cvmx_pko_l1_sqx_topology_cn73xx { 1364 u64 reserved_40_63 : 24; 1365 u64 prio_anchor : 8; 1366 u64 reserved_20_31 : 12; 1367 u64 link : 4; 1368 u64 reserved_5_15 : 11; 1369 u64 rr_prio : 4; 1370 u64 reserved_0_0 : 1; 1371 } cn73xx; 1372 struct cvmx_pko_l1_sqx_topology_s cn78xx; 1373 struct cvmx_pko_l1_sqx_topology_s cn78xxp1; 1374 struct cvmx_pko_l1_sqx_topology_cn73xx cnf75xx; 1375 }; 1376 1377 typedef union cvmx_pko_l1_sqx_topology cvmx_pko_l1_sqx_topology_t; 1378 1379 /** 1380 * cvmx_pko_l1_sq#_yellow 1381 */ 1382 union cvmx_pko_l1_sqx_yellow { 1383 u64 u64; 1384 struct cvmx_pko_l1_sqx_yellow_s { 1385 u64 reserved_19_63 : 45; 1386 u64 head : 9; 1387 u64 reserved_9_9 : 1; 1388 u64 tail : 9; 1389 } s; 1390 struct cvmx_pko_l1_sqx_yellow_s cn73xx; 1391 struct cvmx_pko_l1_sqx_yellow_s cn78xx; 1392 struct cvmx_pko_l1_sqx_yellow_s cn78xxp1; 1393 struct cvmx_pko_l1_sqx_yellow_s cnf75xx; 1394 }; 1395 1396 typedef union cvmx_pko_l1_sqx_yellow cvmx_pko_l1_sqx_yellow_t; 1397 1398 /** 1399 * cvmx_pko_l1_sq#_yellow_bytes 1400 * 1401 * This register has the same bit fields as PKO_L1_SQ()_GREEN_BYTES. 1402 * 1403 */ 1404 union cvmx_pko_l1_sqx_yellow_bytes { 1405 u64 u64; 1406 struct cvmx_pko_l1_sqx_yellow_bytes_s { 1407 u64 reserved_48_63 : 16; 1408 u64 count : 48; 1409 } s; 1410 struct cvmx_pko_l1_sqx_yellow_bytes_s cn73xx; 1411 struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xx; 1412 struct cvmx_pko_l1_sqx_yellow_bytes_s cn78xxp1; 1413 struct cvmx_pko_l1_sqx_yellow_bytes_s cnf75xx; 1414 }; 1415 1416 typedef union cvmx_pko_l1_sqx_yellow_bytes cvmx_pko_l1_sqx_yellow_bytes_t; 1417 1418 /** 1419 * cvmx_pko_l1_sq#_yellow_packets 1420 * 1421 * This register has the same bit fields as PKO_L1_SQ()_GREEN_PACKETS. 1422 * 1423 */ 1424 union cvmx_pko_l1_sqx_yellow_packets { 1425 u64 u64; 1426 struct cvmx_pko_l1_sqx_yellow_packets_s { 1427 u64 reserved_40_63 : 24; 1428 u64 count : 40; 1429 } s; 1430 struct cvmx_pko_l1_sqx_yellow_packets_s cn73xx; 1431 struct cvmx_pko_l1_sqx_yellow_packets_s cn78xx; 1432 struct cvmx_pko_l1_sqx_yellow_packets_s cn78xxp1; 1433 struct cvmx_pko_l1_sqx_yellow_packets_s cnf75xx; 1434 }; 1435 1436 typedef union cvmx_pko_l1_sqx_yellow_packets cvmx_pko_l1_sqx_yellow_packets_t; 1437 1438 /** 1439 * cvmx_pko_l1_sq_csr_bus_debug 1440 */ 1441 union cvmx_pko_l1_sq_csr_bus_debug { 1442 u64 u64; 1443 struct cvmx_pko_l1_sq_csr_bus_debug_s { 1444 u64 csr_bus_debug : 64; 1445 } s; 1446 struct cvmx_pko_l1_sq_csr_bus_debug_s cn73xx; 1447 struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xx; 1448 struct cvmx_pko_l1_sq_csr_bus_debug_s cn78xxp1; 1449 struct cvmx_pko_l1_sq_csr_bus_debug_s cnf75xx; 1450 }; 1451 1452 typedef union cvmx_pko_l1_sq_csr_bus_debug cvmx_pko_l1_sq_csr_bus_debug_t; 1453 1454 /** 1455 * cvmx_pko_l1_sqa_debug 1456 * 1457 * This register has the same bit fields as PKO_PQA_DEBUG. 1458 * 1459 */ 1460 union cvmx_pko_l1_sqa_debug { 1461 u64 u64; 1462 struct cvmx_pko_l1_sqa_debug_s { 1463 u64 dbg_vec : 64; 1464 } s; 1465 struct cvmx_pko_l1_sqa_debug_s cn73xx; 1466 struct cvmx_pko_l1_sqa_debug_s cn78xx; 1467 struct cvmx_pko_l1_sqa_debug_s cn78xxp1; 1468 struct cvmx_pko_l1_sqa_debug_s cnf75xx; 1469 }; 1470 1471 typedef union cvmx_pko_l1_sqa_debug cvmx_pko_l1_sqa_debug_t; 1472 1473 /** 1474 * cvmx_pko_l1_sqb_debug 1475 * 1476 * This register has the same bit fields as PKO_PQA_DEBUG. 1477 * 1478 */ 1479 union cvmx_pko_l1_sqb_debug { 1480 u64 u64; 1481 struct cvmx_pko_l1_sqb_debug_s { 1482 u64 dbg_vec : 64; 1483 } s; 1484 struct cvmx_pko_l1_sqb_debug_s cn73xx; 1485 struct cvmx_pko_l1_sqb_debug_s cn78xx; 1486 struct cvmx_pko_l1_sqb_debug_s cn78xxp1; 1487 struct cvmx_pko_l1_sqb_debug_s cnf75xx; 1488 }; 1489 1490 typedef union cvmx_pko_l1_sqb_debug cvmx_pko_l1_sqb_debug_t; 1491 1492 /** 1493 * cvmx_pko_l2_sq#_cir 1494 * 1495 * This register has the same bit fields as PKO_L1_SQ()_CIR. 1496 * 1497 */ 1498 union cvmx_pko_l2_sqx_cir { 1499 u64 u64; 1500 struct cvmx_pko_l2_sqx_cir_s { 1501 u64 reserved_41_63 : 23; 1502 u64 burst_exponent : 4; 1503 u64 burst_mantissa : 8; 1504 u64 reserved_17_28 : 12; 1505 u64 rate_divider_exponent : 4; 1506 u64 rate_exponent : 4; 1507 u64 rate_mantissa : 8; 1508 u64 enable : 1; 1509 } s; 1510 struct cvmx_pko_l2_sqx_cir_s cn73xx; 1511 struct cvmx_pko_l2_sqx_cir_s cn78xx; 1512 struct cvmx_pko_l2_sqx_cir_s cn78xxp1; 1513 struct cvmx_pko_l2_sqx_cir_s cnf75xx; 1514 }; 1515 1516 typedef union cvmx_pko_l2_sqx_cir cvmx_pko_l2_sqx_cir_t; 1517 1518 /** 1519 * cvmx_pko_l2_sq#_green 1520 * 1521 * This register has the same bit fields as PKO_L1_SQ()_GREEN. 1522 * 1523 */ 1524 union cvmx_pko_l2_sqx_green { 1525 u64 u64; 1526 struct cvmx_pko_l2_sqx_green_s { 1527 u64 reserved_41_63 : 23; 1528 u64 rr_active : 1; 1529 u64 active_vec : 20; 1530 u64 reserved_19_19 : 1; 1531 u64 head : 9; 1532 u64 reserved_9_9 : 1; 1533 u64 tail : 9; 1534 } s; 1535 struct cvmx_pko_l2_sqx_green_s cn73xx; 1536 struct cvmx_pko_l2_sqx_green_s cn78xx; 1537 struct cvmx_pko_l2_sqx_green_s cn78xxp1; 1538 struct cvmx_pko_l2_sqx_green_s cnf75xx; 1539 }; 1540 1541 typedef union cvmx_pko_l2_sqx_green cvmx_pko_l2_sqx_green_t; 1542 1543 /** 1544 * cvmx_pko_l2_sq#_pick 1545 * 1546 * This CSR contains the meta for the L2 SQ, and is for debug and reconfiguration 1547 * only and should never be written. See also PKO_META_DESC_S. 1548 */ 1549 union cvmx_pko_l2_sqx_pick { 1550 u64 u64; 1551 struct cvmx_pko_l2_sqx_pick_s { 1552 u64 dq : 10; 1553 u64 color : 2; 1554 u64 child : 10; 1555 u64 bubble : 1; 1556 u64 p_con : 1; 1557 u64 c_con : 1; 1558 u64 uid : 7; 1559 u64 jump : 1; 1560 u64 fpd : 1; 1561 u64 ds : 1; 1562 u64 adjust : 9; 1563 u64 pir_dis : 1; 1564 u64 cir_dis : 1; 1565 u64 red_algo_override : 2; 1566 u64 length : 16; 1567 } s; 1568 struct cvmx_pko_l2_sqx_pick_s cn73xx; 1569 struct cvmx_pko_l2_sqx_pick_s cn78xx; 1570 struct cvmx_pko_l2_sqx_pick_s cn78xxp1; 1571 struct cvmx_pko_l2_sqx_pick_s cnf75xx; 1572 }; 1573 1574 typedef union cvmx_pko_l2_sqx_pick cvmx_pko_l2_sqx_pick_t; 1575 1576 /** 1577 * cvmx_pko_l2_sq#_pir 1578 * 1579 * This register has the same bit fields as PKO_L1_SQ()_CIR. 1580 * 1581 */ 1582 union cvmx_pko_l2_sqx_pir { 1583 u64 u64; 1584 struct cvmx_pko_l2_sqx_pir_s { 1585 u64 reserved_41_63 : 23; 1586 u64 burst_exponent : 4; 1587 u64 burst_mantissa : 8; 1588 u64 reserved_17_28 : 12; 1589 u64 rate_divider_exponent : 4; 1590 u64 rate_exponent : 4; 1591 u64 rate_mantissa : 8; 1592 u64 enable : 1; 1593 } s; 1594 struct cvmx_pko_l2_sqx_pir_s cn73xx; 1595 struct cvmx_pko_l2_sqx_pir_s cn78xx; 1596 struct cvmx_pko_l2_sqx_pir_s cn78xxp1; 1597 struct cvmx_pko_l2_sqx_pir_s cnf75xx; 1598 }; 1599 1600 typedef union cvmx_pko_l2_sqx_pir cvmx_pko_l2_sqx_pir_t; 1601 1602 /** 1603 * cvmx_pko_l2_sq#_pointers 1604 */ 1605 union cvmx_pko_l2_sqx_pointers { 1606 u64 u64; 1607 struct cvmx_pko_l2_sqx_pointers_s { 1608 u64 reserved_25_63 : 39; 1609 u64 prev : 9; 1610 u64 reserved_9_15 : 7; 1611 u64 next : 9; 1612 } s; 1613 struct cvmx_pko_l2_sqx_pointers_cn73xx { 1614 u64 reserved_24_63 : 40; 1615 u64 prev : 8; 1616 u64 reserved_8_15 : 8; 1617 u64 next : 8; 1618 } cn73xx; 1619 struct cvmx_pko_l2_sqx_pointers_s cn78xx; 1620 struct cvmx_pko_l2_sqx_pointers_s cn78xxp1; 1621 struct cvmx_pko_l2_sqx_pointers_cn73xx cnf75xx; 1622 }; 1623 1624 typedef union cvmx_pko_l2_sqx_pointers cvmx_pko_l2_sqx_pointers_t; 1625 1626 /** 1627 * cvmx_pko_l2_sq#_red 1628 * 1629 * This register has the same bit fields as PKO_L1_SQ()_RED. 1630 * 1631 */ 1632 union cvmx_pko_l2_sqx_red { 1633 u64 u64; 1634 struct cvmx_pko_l2_sqx_red_s { 1635 u64 reserved_19_63 : 45; 1636 u64 head : 9; 1637 u64 reserved_9_9 : 1; 1638 u64 tail : 9; 1639 } s; 1640 struct cvmx_pko_l2_sqx_red_s cn73xx; 1641 struct cvmx_pko_l2_sqx_red_s cn78xx; 1642 struct cvmx_pko_l2_sqx_red_s cn78xxp1; 1643 struct cvmx_pko_l2_sqx_red_s cnf75xx; 1644 }; 1645 1646 typedef union cvmx_pko_l2_sqx_red cvmx_pko_l2_sqx_red_t; 1647 1648 /** 1649 * cvmx_pko_l2_sq#_sched_state 1650 */ 1651 union cvmx_pko_l2_sqx_sched_state { 1652 u64 u64; 1653 struct cvmx_pko_l2_sqx_sched_state_s { 1654 u64 reserved_25_63 : 39; 1655 u64 rr_count : 25; 1656 } s; 1657 struct cvmx_pko_l2_sqx_sched_state_s cn73xx; 1658 struct cvmx_pko_l2_sqx_sched_state_s cn78xx; 1659 struct cvmx_pko_l2_sqx_sched_state_s cn78xxp1; 1660 struct cvmx_pko_l2_sqx_sched_state_s cnf75xx; 1661 }; 1662 1663 typedef union cvmx_pko_l2_sqx_sched_state cvmx_pko_l2_sqx_sched_state_t; 1664 1665 /** 1666 * cvmx_pko_l2_sq#_schedule 1667 */ 1668 union cvmx_pko_l2_sqx_schedule { 1669 u64 u64; 1670 struct cvmx_pko_l2_sqx_schedule_s { 1671 u64 reserved_28_63 : 36; 1672 u64 prio : 4; 1673 u64 rr_quantum : 24; 1674 } s; 1675 struct cvmx_pko_l2_sqx_schedule_s cn73xx; 1676 struct cvmx_pko_l2_sqx_schedule_s cn78xx; 1677 struct cvmx_pko_l2_sqx_schedule_s cn78xxp1; 1678 struct cvmx_pko_l2_sqx_schedule_s cnf75xx; 1679 }; 1680 1681 typedef union cvmx_pko_l2_sqx_schedule cvmx_pko_l2_sqx_schedule_t; 1682 1683 /** 1684 * cvmx_pko_l2_sq#_shape 1685 */ 1686 union cvmx_pko_l2_sqx_shape { 1687 u64 u64; 1688 struct cvmx_pko_l2_sqx_shape_s { 1689 u64 reserved_27_63 : 37; 1690 u64 schedule_list : 2; 1691 u64 length_disable : 1; 1692 u64 reserved_13_23 : 11; 1693 u64 yellow_disable : 1; 1694 u64 red_disable : 1; 1695 u64 red_algo : 2; 1696 u64 adjust : 9; 1697 } s; 1698 struct cvmx_pko_l2_sqx_shape_s cn73xx; 1699 struct cvmx_pko_l2_sqx_shape_cn78xx { 1700 u64 reserved_25_63 : 39; 1701 u64 length_disable : 1; 1702 u64 reserved_13_23 : 11; 1703 u64 yellow_disable : 1; 1704 u64 red_disable : 1; 1705 u64 red_algo : 2; 1706 u64 adjust : 9; 1707 } cn78xx; 1708 struct cvmx_pko_l2_sqx_shape_cn78xx cn78xxp1; 1709 struct cvmx_pko_l2_sqx_shape_s cnf75xx; 1710 }; 1711 1712 typedef union cvmx_pko_l2_sqx_shape cvmx_pko_l2_sqx_shape_t; 1713 1714 /** 1715 * cvmx_pko_l2_sq#_shape_state 1716 * 1717 * This register must not be written during normal operation. 1718 * 1719 */ 1720 union cvmx_pko_l2_sqx_shape_state { 1721 u64 u64; 1722 struct cvmx_pko_l2_sqx_shape_state_s { 1723 u64 reserved_60_63 : 4; 1724 u64 tw_timestamp : 6; 1725 u64 color : 2; 1726 u64 pir_accum : 26; 1727 u64 cir_accum : 26; 1728 } s; 1729 struct cvmx_pko_l2_sqx_shape_state_s cn73xx; 1730 struct cvmx_pko_l2_sqx_shape_state_s cn78xx; 1731 struct cvmx_pko_l2_sqx_shape_state_s cn78xxp1; 1732 struct cvmx_pko_l2_sqx_shape_state_s cnf75xx; 1733 }; 1734 1735 typedef union cvmx_pko_l2_sqx_shape_state cvmx_pko_l2_sqx_shape_state_t; 1736 1737 /** 1738 * cvmx_pko_l2_sq#_sw_xoff 1739 * 1740 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF. 1741 * 1742 */ 1743 union cvmx_pko_l2_sqx_sw_xoff { 1744 u64 u64; 1745 struct cvmx_pko_l2_sqx_sw_xoff_s { 1746 u64 reserved_4_63 : 60; 1747 u64 drain_irq : 1; 1748 u64 drain_null_link : 1; 1749 u64 drain : 1; 1750 u64 xoff : 1; 1751 } s; 1752 struct cvmx_pko_l2_sqx_sw_xoff_s cn73xx; 1753 struct cvmx_pko_l2_sqx_sw_xoff_s cn78xx; 1754 struct cvmx_pko_l2_sqx_sw_xoff_s cn78xxp1; 1755 struct cvmx_pko_l2_sqx_sw_xoff_s cnf75xx; 1756 }; 1757 1758 typedef union cvmx_pko_l2_sqx_sw_xoff cvmx_pko_l2_sqx_sw_xoff_t; 1759 1760 /** 1761 * cvmx_pko_l2_sq#_topology 1762 */ 1763 union cvmx_pko_l2_sqx_topology { 1764 u64 u64; 1765 struct cvmx_pko_l2_sqx_topology_s { 1766 u64 reserved_41_63 : 23; 1767 u64 prio_anchor : 9; 1768 u64 reserved_21_31 : 11; 1769 u64 parent : 5; 1770 u64 reserved_5_15 : 11; 1771 u64 rr_prio : 4; 1772 u64 reserved_0_0 : 1; 1773 } s; 1774 struct cvmx_pko_l2_sqx_topology_cn73xx { 1775 u64 reserved_40_63 : 24; 1776 u64 prio_anchor : 8; 1777 u64 reserved_20_31 : 12; 1778 u64 parent : 4; 1779 u64 reserved_5_15 : 11; 1780 u64 rr_prio : 4; 1781 u64 reserved_0_0 : 1; 1782 } cn73xx; 1783 struct cvmx_pko_l2_sqx_topology_s cn78xx; 1784 struct cvmx_pko_l2_sqx_topology_s cn78xxp1; 1785 struct cvmx_pko_l2_sqx_topology_cn73xx cnf75xx; 1786 }; 1787 1788 typedef union cvmx_pko_l2_sqx_topology cvmx_pko_l2_sqx_topology_t; 1789 1790 /** 1791 * cvmx_pko_l2_sq#_yellow 1792 * 1793 * This register has the same bit fields as PKO_L1_SQ()_YELLOW. 1794 * 1795 */ 1796 union cvmx_pko_l2_sqx_yellow { 1797 u64 u64; 1798 struct cvmx_pko_l2_sqx_yellow_s { 1799 u64 reserved_19_63 : 45; 1800 u64 head : 9; 1801 u64 reserved_9_9 : 1; 1802 u64 tail : 9; 1803 } s; 1804 struct cvmx_pko_l2_sqx_yellow_s cn73xx; 1805 struct cvmx_pko_l2_sqx_yellow_s cn78xx; 1806 struct cvmx_pko_l2_sqx_yellow_s cn78xxp1; 1807 struct cvmx_pko_l2_sqx_yellow_s cnf75xx; 1808 }; 1809 1810 typedef union cvmx_pko_l2_sqx_yellow cvmx_pko_l2_sqx_yellow_t; 1811 1812 /** 1813 * cvmx_pko_l2_sq_csr_bus_debug 1814 */ 1815 union cvmx_pko_l2_sq_csr_bus_debug { 1816 u64 u64; 1817 struct cvmx_pko_l2_sq_csr_bus_debug_s { 1818 u64 csr_bus_debug : 64; 1819 } s; 1820 struct cvmx_pko_l2_sq_csr_bus_debug_s cn73xx; 1821 struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xx; 1822 struct cvmx_pko_l2_sq_csr_bus_debug_s cn78xxp1; 1823 struct cvmx_pko_l2_sq_csr_bus_debug_s cnf75xx; 1824 }; 1825 1826 typedef union cvmx_pko_l2_sq_csr_bus_debug cvmx_pko_l2_sq_csr_bus_debug_t; 1827 1828 /** 1829 * cvmx_pko_l2_sqa_debug 1830 * 1831 * This register has the same bit fields as PKO_PQA_DEBUG. 1832 * 1833 */ 1834 union cvmx_pko_l2_sqa_debug { 1835 u64 u64; 1836 struct cvmx_pko_l2_sqa_debug_s { 1837 u64 dbg_vec : 64; 1838 } s; 1839 struct cvmx_pko_l2_sqa_debug_s cn73xx; 1840 struct cvmx_pko_l2_sqa_debug_s cn78xx; 1841 struct cvmx_pko_l2_sqa_debug_s cn78xxp1; 1842 struct cvmx_pko_l2_sqa_debug_s cnf75xx; 1843 }; 1844 1845 typedef union cvmx_pko_l2_sqa_debug cvmx_pko_l2_sqa_debug_t; 1846 1847 /** 1848 * cvmx_pko_l2_sqb_debug 1849 * 1850 * This register has the same bit fields as PKO_PQA_DEBUG. 1851 * 1852 */ 1853 union cvmx_pko_l2_sqb_debug { 1854 u64 u64; 1855 struct cvmx_pko_l2_sqb_debug_s { 1856 u64 dbg_vec : 64; 1857 } s; 1858 struct cvmx_pko_l2_sqb_debug_s cn73xx; 1859 struct cvmx_pko_l2_sqb_debug_s cn78xx; 1860 struct cvmx_pko_l2_sqb_debug_s cn78xxp1; 1861 struct cvmx_pko_l2_sqb_debug_s cnf75xx; 1862 }; 1863 1864 typedef union cvmx_pko_l2_sqb_debug cvmx_pko_l2_sqb_debug_t; 1865 1866 /** 1867 * cvmx_pko_l3_l2_sq#_channel 1868 * 1869 * PKO_CHANNEL_LEVEL[CC_LEVEL] determines whether this CSR array is associated to 1870 * the L2 SQs or the L3 SQs. 1871 */ 1872 union cvmx_pko_l3_l2_sqx_channel { 1873 u64 u64; 1874 struct cvmx_pko_l3_l2_sqx_channel_s { 1875 u64 reserved_44_63 : 20; 1876 u64 cc_channel : 12; 1877 u64 cc_word_cnt : 20; 1878 u64 cc_packet_cnt : 10; 1879 u64 cc_enable : 1; 1880 u64 hw_xoff : 1; 1881 } s; 1882 struct cvmx_pko_l3_l2_sqx_channel_s cn73xx; 1883 struct cvmx_pko_l3_l2_sqx_channel_s cn78xx; 1884 struct cvmx_pko_l3_l2_sqx_channel_s cn78xxp1; 1885 struct cvmx_pko_l3_l2_sqx_channel_s cnf75xx; 1886 }; 1887 1888 typedef union cvmx_pko_l3_l2_sqx_channel cvmx_pko_l3_l2_sqx_channel_t; 1889 1890 /** 1891 * cvmx_pko_l3_sq#_cir 1892 * 1893 * This register has the same bit fields as PKO_L1_SQ()_CIR. 1894 * 1895 */ 1896 union cvmx_pko_l3_sqx_cir { 1897 u64 u64; 1898 struct cvmx_pko_l3_sqx_cir_s { 1899 u64 reserved_41_63 : 23; 1900 u64 burst_exponent : 4; 1901 u64 burst_mantissa : 8; 1902 u64 reserved_17_28 : 12; 1903 u64 rate_divider_exponent : 4; 1904 u64 rate_exponent : 4; 1905 u64 rate_mantissa : 8; 1906 u64 enable : 1; 1907 } s; 1908 struct cvmx_pko_l3_sqx_cir_s cn73xx; 1909 struct cvmx_pko_l3_sqx_cir_s cn78xx; 1910 struct cvmx_pko_l3_sqx_cir_s cn78xxp1; 1911 struct cvmx_pko_l3_sqx_cir_s cnf75xx; 1912 }; 1913 1914 typedef union cvmx_pko_l3_sqx_cir cvmx_pko_l3_sqx_cir_t; 1915 1916 /** 1917 * cvmx_pko_l3_sq#_green 1918 */ 1919 union cvmx_pko_l3_sqx_green { 1920 u64 u64; 1921 struct cvmx_pko_l3_sqx_green_s { 1922 u64 reserved_41_63 : 23; 1923 u64 rr_active : 1; 1924 u64 active_vec : 20; 1925 u64 head : 10; 1926 u64 tail : 10; 1927 } s; 1928 struct cvmx_pko_l3_sqx_green_cn73xx { 1929 u64 reserved_41_63 : 23; 1930 u64 rr_active : 1; 1931 u64 active_vec : 20; 1932 u64 reserved_18_19 : 2; 1933 u64 head : 8; 1934 u64 reserved_8_9 : 2; 1935 u64 tail : 8; 1936 } cn73xx; 1937 struct cvmx_pko_l3_sqx_green_s cn78xx; 1938 struct cvmx_pko_l3_sqx_green_s cn78xxp1; 1939 struct cvmx_pko_l3_sqx_green_cn73xx cnf75xx; 1940 }; 1941 1942 typedef union cvmx_pko_l3_sqx_green cvmx_pko_l3_sqx_green_t; 1943 1944 /** 1945 * cvmx_pko_l3_sq#_pick 1946 * 1947 * This CSR contains the meta for the L3 SQ, and is for debug and reconfiguration 1948 * only and should never be written. See also PKO_META_DESC_S. 1949 */ 1950 union cvmx_pko_l3_sqx_pick { 1951 u64 u64; 1952 struct cvmx_pko_l3_sqx_pick_s { 1953 u64 dq : 10; 1954 u64 color : 2; 1955 u64 child : 10; 1956 u64 bubble : 1; 1957 u64 p_con : 1; 1958 u64 c_con : 1; 1959 u64 uid : 7; 1960 u64 jump : 1; 1961 u64 fpd : 1; 1962 u64 ds : 1; 1963 u64 adjust : 9; 1964 u64 pir_dis : 1; 1965 u64 cir_dis : 1; 1966 u64 red_algo_override : 2; 1967 u64 length : 16; 1968 } s; 1969 struct cvmx_pko_l3_sqx_pick_s cn73xx; 1970 struct cvmx_pko_l3_sqx_pick_s cn78xx; 1971 struct cvmx_pko_l3_sqx_pick_s cn78xxp1; 1972 struct cvmx_pko_l3_sqx_pick_s cnf75xx; 1973 }; 1974 1975 typedef union cvmx_pko_l3_sqx_pick cvmx_pko_l3_sqx_pick_t; 1976 1977 /** 1978 * cvmx_pko_l3_sq#_pir 1979 * 1980 * This register has the same bit fields as PKO_L1_SQ()_CIR. 1981 * 1982 */ 1983 union cvmx_pko_l3_sqx_pir { 1984 u64 u64; 1985 struct cvmx_pko_l3_sqx_pir_s { 1986 u64 reserved_41_63 : 23; 1987 u64 burst_exponent : 4; 1988 u64 burst_mantissa : 8; 1989 u64 reserved_17_28 : 12; 1990 u64 rate_divider_exponent : 4; 1991 u64 rate_exponent : 4; 1992 u64 rate_mantissa : 8; 1993 u64 enable : 1; 1994 } s; 1995 struct cvmx_pko_l3_sqx_pir_s cn73xx; 1996 struct cvmx_pko_l3_sqx_pir_s cn78xx; 1997 struct cvmx_pko_l3_sqx_pir_s cn78xxp1; 1998 struct cvmx_pko_l3_sqx_pir_s cnf75xx; 1999 }; 2000 2001 typedef union cvmx_pko_l3_sqx_pir cvmx_pko_l3_sqx_pir_t; 2002 2003 /** 2004 * cvmx_pko_l3_sq#_pointers 2005 * 2006 * This register has the same bit fields as PKO_L2_SQ()_POINTERS. 2007 * 2008 */ 2009 union cvmx_pko_l3_sqx_pointers { 2010 u64 u64; 2011 struct cvmx_pko_l3_sqx_pointers_s { 2012 u64 reserved_25_63 : 39; 2013 u64 prev : 9; 2014 u64 reserved_9_15 : 7; 2015 u64 next : 9; 2016 } s; 2017 struct cvmx_pko_l3_sqx_pointers_cn73xx { 2018 u64 reserved_24_63 : 40; 2019 u64 prev : 8; 2020 u64 reserved_8_15 : 8; 2021 u64 next : 8; 2022 } cn73xx; 2023 struct cvmx_pko_l3_sqx_pointers_s cn78xx; 2024 struct cvmx_pko_l3_sqx_pointers_s cn78xxp1; 2025 struct cvmx_pko_l3_sqx_pointers_cn73xx cnf75xx; 2026 }; 2027 2028 typedef union cvmx_pko_l3_sqx_pointers cvmx_pko_l3_sqx_pointers_t; 2029 2030 /** 2031 * cvmx_pko_l3_sq#_red 2032 * 2033 * This register has the same bit fields as PKO_L3_SQ()_YELLOW. 2034 * 2035 */ 2036 union cvmx_pko_l3_sqx_red { 2037 u64 u64; 2038 struct cvmx_pko_l3_sqx_red_s { 2039 u64 reserved_20_63 : 44; 2040 u64 head : 10; 2041 u64 tail : 10; 2042 } s; 2043 struct cvmx_pko_l3_sqx_red_cn73xx { 2044 u64 reserved_18_63 : 46; 2045 u64 head : 8; 2046 u64 reserved_8_9 : 2; 2047 u64 tail : 8; 2048 } cn73xx; 2049 struct cvmx_pko_l3_sqx_red_s cn78xx; 2050 struct cvmx_pko_l3_sqx_red_s cn78xxp1; 2051 struct cvmx_pko_l3_sqx_red_cn73xx cnf75xx; 2052 }; 2053 2054 typedef union cvmx_pko_l3_sqx_red cvmx_pko_l3_sqx_red_t; 2055 2056 /** 2057 * cvmx_pko_l3_sq#_sched_state 2058 * 2059 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE. 2060 * 2061 */ 2062 union cvmx_pko_l3_sqx_sched_state { 2063 u64 u64; 2064 struct cvmx_pko_l3_sqx_sched_state_s { 2065 u64 reserved_25_63 : 39; 2066 u64 rr_count : 25; 2067 } s; 2068 struct cvmx_pko_l3_sqx_sched_state_s cn73xx; 2069 struct cvmx_pko_l3_sqx_sched_state_s cn78xx; 2070 struct cvmx_pko_l3_sqx_sched_state_s cn78xxp1; 2071 struct cvmx_pko_l3_sqx_sched_state_s cnf75xx; 2072 }; 2073 2074 typedef union cvmx_pko_l3_sqx_sched_state cvmx_pko_l3_sqx_sched_state_t; 2075 2076 /** 2077 * cvmx_pko_l3_sq#_schedule 2078 * 2079 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE. 2080 * 2081 */ 2082 union cvmx_pko_l3_sqx_schedule { 2083 u64 u64; 2084 struct cvmx_pko_l3_sqx_schedule_s { 2085 u64 reserved_28_63 : 36; 2086 u64 prio : 4; 2087 u64 rr_quantum : 24; 2088 } s; 2089 struct cvmx_pko_l3_sqx_schedule_s cn73xx; 2090 struct cvmx_pko_l3_sqx_schedule_s cn78xx; 2091 struct cvmx_pko_l3_sqx_schedule_s cn78xxp1; 2092 struct cvmx_pko_l3_sqx_schedule_s cnf75xx; 2093 }; 2094 2095 typedef union cvmx_pko_l3_sqx_schedule cvmx_pko_l3_sqx_schedule_t; 2096 2097 /** 2098 * cvmx_pko_l3_sq#_shape 2099 */ 2100 union cvmx_pko_l3_sqx_shape { 2101 u64 u64; 2102 struct cvmx_pko_l3_sqx_shape_s { 2103 u64 reserved_27_63 : 37; 2104 u64 schedule_list : 2; 2105 u64 length_disable : 1; 2106 u64 reserved_13_23 : 11; 2107 u64 yellow_disable : 1; 2108 u64 red_disable : 1; 2109 u64 red_algo : 2; 2110 u64 adjust : 9; 2111 } s; 2112 struct cvmx_pko_l3_sqx_shape_s cn73xx; 2113 struct cvmx_pko_l3_sqx_shape_cn78xx { 2114 u64 reserved_25_63 : 39; 2115 u64 length_disable : 1; 2116 u64 reserved_13_23 : 11; 2117 u64 yellow_disable : 1; 2118 u64 red_disable : 1; 2119 u64 red_algo : 2; 2120 u64 adjust : 9; 2121 } cn78xx; 2122 struct cvmx_pko_l3_sqx_shape_cn78xx cn78xxp1; 2123 struct cvmx_pko_l3_sqx_shape_s cnf75xx; 2124 }; 2125 2126 typedef union cvmx_pko_l3_sqx_shape cvmx_pko_l3_sqx_shape_t; 2127 2128 /** 2129 * cvmx_pko_l3_sq#_shape_state 2130 * 2131 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE. 2132 * This register must not be written during normal operation. 2133 */ 2134 union cvmx_pko_l3_sqx_shape_state { 2135 u64 u64; 2136 struct cvmx_pko_l3_sqx_shape_state_s { 2137 u64 reserved_60_63 : 4; 2138 u64 tw_timestamp : 6; 2139 u64 color : 2; 2140 u64 pir_accum : 26; 2141 u64 cir_accum : 26; 2142 } s; 2143 struct cvmx_pko_l3_sqx_shape_state_s cn73xx; 2144 struct cvmx_pko_l3_sqx_shape_state_s cn78xx; 2145 struct cvmx_pko_l3_sqx_shape_state_s cn78xxp1; 2146 struct cvmx_pko_l3_sqx_shape_state_s cnf75xx; 2147 }; 2148 2149 typedef union cvmx_pko_l3_sqx_shape_state cvmx_pko_l3_sqx_shape_state_t; 2150 2151 /** 2152 * cvmx_pko_l3_sq#_sw_xoff 2153 * 2154 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF 2155 * 2156 */ 2157 union cvmx_pko_l3_sqx_sw_xoff { 2158 u64 u64; 2159 struct cvmx_pko_l3_sqx_sw_xoff_s { 2160 u64 reserved_4_63 : 60; 2161 u64 drain_irq : 1; 2162 u64 drain_null_link : 1; 2163 u64 drain : 1; 2164 u64 xoff : 1; 2165 } s; 2166 struct cvmx_pko_l3_sqx_sw_xoff_s cn73xx; 2167 struct cvmx_pko_l3_sqx_sw_xoff_s cn78xx; 2168 struct cvmx_pko_l3_sqx_sw_xoff_s cn78xxp1; 2169 struct cvmx_pko_l3_sqx_sw_xoff_s cnf75xx; 2170 }; 2171 2172 typedef union cvmx_pko_l3_sqx_sw_xoff cvmx_pko_l3_sqx_sw_xoff_t; 2173 2174 /** 2175 * cvmx_pko_l3_sq#_topology 2176 */ 2177 union cvmx_pko_l3_sqx_topology { 2178 u64 u64; 2179 struct cvmx_pko_l3_sqx_topology_s { 2180 u64 reserved_42_63 : 22; 2181 u64 prio_anchor : 10; 2182 u64 reserved_25_31 : 7; 2183 u64 parent : 9; 2184 u64 reserved_5_15 : 11; 2185 u64 rr_prio : 4; 2186 u64 reserved_0_0 : 1; 2187 } s; 2188 struct cvmx_pko_l3_sqx_topology_cn73xx { 2189 u64 reserved_40_63 : 24; 2190 u64 prio_anchor : 8; 2191 u64 reserved_24_31 : 8; 2192 u64 parent : 8; 2193 u64 reserved_5_15 : 11; 2194 u64 rr_prio : 4; 2195 u64 reserved_0_0 : 1; 2196 } cn73xx; 2197 struct cvmx_pko_l3_sqx_topology_s cn78xx; 2198 struct cvmx_pko_l3_sqx_topology_s cn78xxp1; 2199 struct cvmx_pko_l3_sqx_topology_cn73xx cnf75xx; 2200 }; 2201 2202 typedef union cvmx_pko_l3_sqx_topology cvmx_pko_l3_sqx_topology_t; 2203 2204 /** 2205 * cvmx_pko_l3_sq#_yellow 2206 */ 2207 union cvmx_pko_l3_sqx_yellow { 2208 u64 u64; 2209 struct cvmx_pko_l3_sqx_yellow_s { 2210 u64 reserved_20_63 : 44; 2211 u64 head : 10; 2212 u64 tail : 10; 2213 } s; 2214 struct cvmx_pko_l3_sqx_yellow_cn73xx { 2215 u64 reserved_18_63 : 46; 2216 u64 head : 8; 2217 u64 reserved_8_9 : 2; 2218 u64 tail : 8; 2219 } cn73xx; 2220 struct cvmx_pko_l3_sqx_yellow_s cn78xx; 2221 struct cvmx_pko_l3_sqx_yellow_s cn78xxp1; 2222 struct cvmx_pko_l3_sqx_yellow_cn73xx cnf75xx; 2223 }; 2224 2225 typedef union cvmx_pko_l3_sqx_yellow cvmx_pko_l3_sqx_yellow_t; 2226 2227 /** 2228 * cvmx_pko_l3_sq_csr_bus_debug 2229 */ 2230 union cvmx_pko_l3_sq_csr_bus_debug { 2231 u64 u64; 2232 struct cvmx_pko_l3_sq_csr_bus_debug_s { 2233 u64 csr_bus_debug : 64; 2234 } s; 2235 struct cvmx_pko_l3_sq_csr_bus_debug_s cn73xx; 2236 struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xx; 2237 struct cvmx_pko_l3_sq_csr_bus_debug_s cn78xxp1; 2238 struct cvmx_pko_l3_sq_csr_bus_debug_s cnf75xx; 2239 }; 2240 2241 typedef union cvmx_pko_l3_sq_csr_bus_debug cvmx_pko_l3_sq_csr_bus_debug_t; 2242 2243 /** 2244 * cvmx_pko_l3_sqa_debug 2245 * 2246 * This register has the same bit fields as PKO_PQA_DEBUG. 2247 * 2248 */ 2249 union cvmx_pko_l3_sqa_debug { 2250 u64 u64; 2251 struct cvmx_pko_l3_sqa_debug_s { 2252 u64 dbg_vec : 64; 2253 } s; 2254 struct cvmx_pko_l3_sqa_debug_s cn73xx; 2255 struct cvmx_pko_l3_sqa_debug_s cn78xx; 2256 struct cvmx_pko_l3_sqa_debug_s cn78xxp1; 2257 struct cvmx_pko_l3_sqa_debug_s cnf75xx; 2258 }; 2259 2260 typedef union cvmx_pko_l3_sqa_debug cvmx_pko_l3_sqa_debug_t; 2261 2262 /** 2263 * cvmx_pko_l3_sqb_debug 2264 * 2265 * This register has the same bit fields as PKO_PQA_DEBUG. 2266 * 2267 */ 2268 union cvmx_pko_l3_sqb_debug { 2269 u64 u64; 2270 struct cvmx_pko_l3_sqb_debug_s { 2271 u64 dbg_vec : 64; 2272 } s; 2273 struct cvmx_pko_l3_sqb_debug_s cn73xx; 2274 struct cvmx_pko_l3_sqb_debug_s cn78xx; 2275 struct cvmx_pko_l3_sqb_debug_s cn78xxp1; 2276 struct cvmx_pko_l3_sqb_debug_s cnf75xx; 2277 }; 2278 2279 typedef union cvmx_pko_l3_sqb_debug cvmx_pko_l3_sqb_debug_t; 2280 2281 /** 2282 * cvmx_pko_l4_sq#_cir 2283 * 2284 * This register has the same bit fields as PKO_L1_SQ()_CIR. 2285 * 2286 */ 2287 union cvmx_pko_l4_sqx_cir { 2288 u64 u64; 2289 struct cvmx_pko_l4_sqx_cir_s { 2290 u64 reserved_41_63 : 23; 2291 u64 burst_exponent : 4; 2292 u64 burst_mantissa : 8; 2293 u64 reserved_17_28 : 12; 2294 u64 rate_divider_exponent : 4; 2295 u64 rate_exponent : 4; 2296 u64 rate_mantissa : 8; 2297 u64 enable : 1; 2298 } s; 2299 struct cvmx_pko_l4_sqx_cir_s cn78xx; 2300 struct cvmx_pko_l4_sqx_cir_s cn78xxp1; 2301 }; 2302 2303 typedef union cvmx_pko_l4_sqx_cir cvmx_pko_l4_sqx_cir_t; 2304 2305 /** 2306 * cvmx_pko_l4_sq#_green 2307 * 2308 * This register has the same bit fields as PKO_L3_SQ()_GREEN. 2309 * 2310 */ 2311 union cvmx_pko_l4_sqx_green { 2312 u64 u64; 2313 struct cvmx_pko_l4_sqx_green_s { 2314 u64 reserved_41_63 : 23; 2315 u64 rr_active : 1; 2316 u64 active_vec : 20; 2317 u64 head : 10; 2318 u64 tail : 10; 2319 } s; 2320 struct cvmx_pko_l4_sqx_green_s cn78xx; 2321 struct cvmx_pko_l4_sqx_green_s cn78xxp1; 2322 }; 2323 2324 typedef union cvmx_pko_l4_sqx_green cvmx_pko_l4_sqx_green_t; 2325 2326 /** 2327 * cvmx_pko_l4_sq#_pick 2328 * 2329 * This CSR contains the meta for the L4 SQ, and is for debug and reconfiguration 2330 * only and should never be written. See also PKO_META_DESC_S. 2331 */ 2332 union cvmx_pko_l4_sqx_pick { 2333 u64 u64; 2334 struct cvmx_pko_l4_sqx_pick_s { 2335 u64 dq : 10; 2336 u64 color : 2; 2337 u64 child : 10; 2338 u64 bubble : 1; 2339 u64 p_con : 1; 2340 u64 c_con : 1; 2341 u64 uid : 7; 2342 u64 jump : 1; 2343 u64 fpd : 1; 2344 u64 ds : 1; 2345 u64 adjust : 9; 2346 u64 pir_dis : 1; 2347 u64 cir_dis : 1; 2348 u64 red_algo_override : 2; 2349 u64 length : 16; 2350 } s; 2351 struct cvmx_pko_l4_sqx_pick_s cn78xx; 2352 struct cvmx_pko_l4_sqx_pick_s cn78xxp1; 2353 }; 2354 2355 typedef union cvmx_pko_l4_sqx_pick cvmx_pko_l4_sqx_pick_t; 2356 2357 /** 2358 * cvmx_pko_l4_sq#_pir 2359 * 2360 * This register has the same bit fields as PKO_L1_SQ()_CIR. 2361 * 2362 */ 2363 union cvmx_pko_l4_sqx_pir { 2364 u64 u64; 2365 struct cvmx_pko_l4_sqx_pir_s { 2366 u64 reserved_41_63 : 23; 2367 u64 burst_exponent : 4; 2368 u64 burst_mantissa : 8; 2369 u64 reserved_17_28 : 12; 2370 u64 rate_divider_exponent : 4; 2371 u64 rate_exponent : 4; 2372 u64 rate_mantissa : 8; 2373 u64 enable : 1; 2374 } s; 2375 struct cvmx_pko_l4_sqx_pir_s cn78xx; 2376 struct cvmx_pko_l4_sqx_pir_s cn78xxp1; 2377 }; 2378 2379 typedef union cvmx_pko_l4_sqx_pir cvmx_pko_l4_sqx_pir_t; 2380 2381 /** 2382 * cvmx_pko_l4_sq#_pointers 2383 */ 2384 union cvmx_pko_l4_sqx_pointers { 2385 u64 u64; 2386 struct cvmx_pko_l4_sqx_pointers_s { 2387 u64 reserved_26_63 : 38; 2388 u64 prev : 10; 2389 u64 reserved_10_15 : 6; 2390 u64 next : 10; 2391 } s; 2392 struct cvmx_pko_l4_sqx_pointers_s cn78xx; 2393 struct cvmx_pko_l4_sqx_pointers_s cn78xxp1; 2394 }; 2395 2396 typedef union cvmx_pko_l4_sqx_pointers cvmx_pko_l4_sqx_pointers_t; 2397 2398 /** 2399 * cvmx_pko_l4_sq#_red 2400 * 2401 * This register has the same bit fields as PKO_L3_SQ()_YELLOW. 2402 * 2403 */ 2404 union cvmx_pko_l4_sqx_red { 2405 u64 u64; 2406 struct cvmx_pko_l4_sqx_red_s { 2407 u64 reserved_20_63 : 44; 2408 u64 head : 10; 2409 u64 tail : 10; 2410 } s; 2411 struct cvmx_pko_l4_sqx_red_s cn78xx; 2412 struct cvmx_pko_l4_sqx_red_s cn78xxp1; 2413 }; 2414 2415 typedef union cvmx_pko_l4_sqx_red cvmx_pko_l4_sqx_red_t; 2416 2417 /** 2418 * cvmx_pko_l4_sq#_sched_state 2419 * 2420 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE. 2421 * 2422 */ 2423 union cvmx_pko_l4_sqx_sched_state { 2424 u64 u64; 2425 struct cvmx_pko_l4_sqx_sched_state_s { 2426 u64 reserved_25_63 : 39; 2427 u64 rr_count : 25; 2428 } s; 2429 struct cvmx_pko_l4_sqx_sched_state_s cn78xx; 2430 struct cvmx_pko_l4_sqx_sched_state_s cn78xxp1; 2431 }; 2432 2433 typedef union cvmx_pko_l4_sqx_sched_state cvmx_pko_l4_sqx_sched_state_t; 2434 2435 /** 2436 * cvmx_pko_l4_sq#_schedule 2437 * 2438 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE. 2439 * 2440 */ 2441 union cvmx_pko_l4_sqx_schedule { 2442 u64 u64; 2443 struct cvmx_pko_l4_sqx_schedule_s { 2444 u64 reserved_28_63 : 36; 2445 u64 prio : 4; 2446 u64 rr_quantum : 24; 2447 } s; 2448 struct cvmx_pko_l4_sqx_schedule_s cn78xx; 2449 struct cvmx_pko_l4_sqx_schedule_s cn78xxp1; 2450 }; 2451 2452 typedef union cvmx_pko_l4_sqx_schedule cvmx_pko_l4_sqx_schedule_t; 2453 2454 /** 2455 * cvmx_pko_l4_sq#_shape 2456 * 2457 * This register has the same bit fields as PKO_L3_SQ()_SHAPE. 2458 * 2459 */ 2460 union cvmx_pko_l4_sqx_shape { 2461 u64 u64; 2462 struct cvmx_pko_l4_sqx_shape_s { 2463 u64 reserved_25_63 : 39; 2464 u64 length_disable : 1; 2465 u64 reserved_13_23 : 11; 2466 u64 yellow_disable : 1; 2467 u64 red_disable : 1; 2468 u64 red_algo : 2; 2469 u64 adjust : 9; 2470 } s; 2471 struct cvmx_pko_l4_sqx_shape_s cn78xx; 2472 struct cvmx_pko_l4_sqx_shape_s cn78xxp1; 2473 }; 2474 2475 typedef union cvmx_pko_l4_sqx_shape cvmx_pko_l4_sqx_shape_t; 2476 2477 /** 2478 * cvmx_pko_l4_sq#_shape_state 2479 * 2480 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE. 2481 * This register must not be written during normal operation. 2482 */ 2483 union cvmx_pko_l4_sqx_shape_state { 2484 u64 u64; 2485 struct cvmx_pko_l4_sqx_shape_state_s { 2486 u64 reserved_60_63 : 4; 2487 u64 tw_timestamp : 6; 2488 u64 color : 2; 2489 u64 pir_accum : 26; 2490 u64 cir_accum : 26; 2491 } s; 2492 struct cvmx_pko_l4_sqx_shape_state_s cn78xx; 2493 struct cvmx_pko_l4_sqx_shape_state_s cn78xxp1; 2494 }; 2495 2496 typedef union cvmx_pko_l4_sqx_shape_state cvmx_pko_l4_sqx_shape_state_t; 2497 2498 /** 2499 * cvmx_pko_l4_sq#_sw_xoff 2500 * 2501 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF. 2502 * 2503 */ 2504 union cvmx_pko_l4_sqx_sw_xoff { 2505 u64 u64; 2506 struct cvmx_pko_l4_sqx_sw_xoff_s { 2507 u64 reserved_4_63 : 60; 2508 u64 drain_irq : 1; 2509 u64 drain_null_link : 1; 2510 u64 drain : 1; 2511 u64 xoff : 1; 2512 } s; 2513 struct cvmx_pko_l4_sqx_sw_xoff_s cn78xx; 2514 struct cvmx_pko_l4_sqx_sw_xoff_s cn78xxp1; 2515 }; 2516 2517 typedef union cvmx_pko_l4_sqx_sw_xoff cvmx_pko_l4_sqx_sw_xoff_t; 2518 2519 /** 2520 * cvmx_pko_l4_sq#_topology 2521 */ 2522 union cvmx_pko_l4_sqx_topology { 2523 u64 u64; 2524 struct cvmx_pko_l4_sqx_topology_s { 2525 u64 reserved_42_63 : 22; 2526 u64 prio_anchor : 10; 2527 u64 reserved_25_31 : 7; 2528 u64 parent : 9; 2529 u64 reserved_5_15 : 11; 2530 u64 rr_prio : 4; 2531 u64 reserved_0_0 : 1; 2532 } s; 2533 struct cvmx_pko_l4_sqx_topology_s cn78xx; 2534 struct cvmx_pko_l4_sqx_topology_s cn78xxp1; 2535 }; 2536 2537 typedef union cvmx_pko_l4_sqx_topology cvmx_pko_l4_sqx_topology_t; 2538 2539 /** 2540 * cvmx_pko_l4_sq#_yellow 2541 * 2542 * This register has the same bit fields as PKO_L3_SQ()_YELLOW. 2543 * 2544 */ 2545 union cvmx_pko_l4_sqx_yellow { 2546 u64 u64; 2547 struct cvmx_pko_l4_sqx_yellow_s { 2548 u64 reserved_20_63 : 44; 2549 u64 head : 10; 2550 u64 tail : 10; 2551 } s; 2552 struct cvmx_pko_l4_sqx_yellow_s cn78xx; 2553 struct cvmx_pko_l4_sqx_yellow_s cn78xxp1; 2554 }; 2555 2556 typedef union cvmx_pko_l4_sqx_yellow cvmx_pko_l4_sqx_yellow_t; 2557 2558 /** 2559 * cvmx_pko_l4_sq_csr_bus_debug 2560 */ 2561 union cvmx_pko_l4_sq_csr_bus_debug { 2562 u64 u64; 2563 struct cvmx_pko_l4_sq_csr_bus_debug_s { 2564 u64 csr_bus_debug : 64; 2565 } s; 2566 struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xx; 2567 struct cvmx_pko_l4_sq_csr_bus_debug_s cn78xxp1; 2568 }; 2569 2570 typedef union cvmx_pko_l4_sq_csr_bus_debug cvmx_pko_l4_sq_csr_bus_debug_t; 2571 2572 /** 2573 * cvmx_pko_l4_sqa_debug 2574 * 2575 * This register has the same bit fields as PKO_PQA_DEBUG. 2576 * 2577 */ 2578 union cvmx_pko_l4_sqa_debug { 2579 u64 u64; 2580 struct cvmx_pko_l4_sqa_debug_s { 2581 u64 dbg_vec : 64; 2582 } s; 2583 struct cvmx_pko_l4_sqa_debug_s cn78xx; 2584 struct cvmx_pko_l4_sqa_debug_s cn78xxp1; 2585 }; 2586 2587 typedef union cvmx_pko_l4_sqa_debug cvmx_pko_l4_sqa_debug_t; 2588 2589 /** 2590 * cvmx_pko_l4_sqb_debug 2591 * 2592 * This register has the same bit fields as PKO_PQA_DEBUG. 2593 * 2594 */ 2595 union cvmx_pko_l4_sqb_debug { 2596 u64 u64; 2597 struct cvmx_pko_l4_sqb_debug_s { 2598 u64 dbg_vec : 64; 2599 } s; 2600 struct cvmx_pko_l4_sqb_debug_s cn78xx; 2601 struct cvmx_pko_l4_sqb_debug_s cn78xxp1; 2602 }; 2603 2604 typedef union cvmx_pko_l4_sqb_debug cvmx_pko_l4_sqb_debug_t; 2605 2606 /** 2607 * cvmx_pko_l5_sq#_cir 2608 * 2609 * This register has the same bit fields as PKO_L1_SQ()_CIR. 2610 * 2611 */ 2612 union cvmx_pko_l5_sqx_cir { 2613 u64 u64; 2614 struct cvmx_pko_l5_sqx_cir_s { 2615 u64 reserved_41_63 : 23; 2616 u64 burst_exponent : 4; 2617 u64 burst_mantissa : 8; 2618 u64 reserved_17_28 : 12; 2619 u64 rate_divider_exponent : 4; 2620 u64 rate_exponent : 4; 2621 u64 rate_mantissa : 8; 2622 u64 enable : 1; 2623 } s; 2624 struct cvmx_pko_l5_sqx_cir_s cn78xx; 2625 struct cvmx_pko_l5_sqx_cir_s cn78xxp1; 2626 }; 2627 2628 typedef union cvmx_pko_l5_sqx_cir cvmx_pko_l5_sqx_cir_t; 2629 2630 /** 2631 * cvmx_pko_l5_sq#_green 2632 * 2633 * This register has the same bit fields as PKO_L3_SQ()_GREEN. 2634 * 2635 */ 2636 union cvmx_pko_l5_sqx_green { 2637 u64 u64; 2638 struct cvmx_pko_l5_sqx_green_s { 2639 u64 reserved_41_63 : 23; 2640 u64 rr_active : 1; 2641 u64 active_vec : 20; 2642 u64 head : 10; 2643 u64 tail : 10; 2644 } s; 2645 struct cvmx_pko_l5_sqx_green_s cn78xx; 2646 struct cvmx_pko_l5_sqx_green_s cn78xxp1; 2647 }; 2648 2649 typedef union cvmx_pko_l5_sqx_green cvmx_pko_l5_sqx_green_t; 2650 2651 /** 2652 * cvmx_pko_l5_sq#_pick 2653 * 2654 * This CSR contains the meta for the L5 SQ, and is for debug and reconfiguration 2655 * only and should never be written. See also PKO_META_DESC_S. 2656 */ 2657 union cvmx_pko_l5_sqx_pick { 2658 u64 u64; 2659 struct cvmx_pko_l5_sqx_pick_s { 2660 u64 dq : 10; 2661 u64 color : 2; 2662 u64 child : 10; 2663 u64 bubble : 1; 2664 u64 p_con : 1; 2665 u64 c_con : 1; 2666 u64 uid : 7; 2667 u64 jump : 1; 2668 u64 fpd : 1; 2669 u64 ds : 1; 2670 u64 adjust : 9; 2671 u64 pir_dis : 1; 2672 u64 cir_dis : 1; 2673 u64 red_algo_override : 2; 2674 u64 length : 16; 2675 } s; 2676 struct cvmx_pko_l5_sqx_pick_s cn78xx; 2677 struct cvmx_pko_l5_sqx_pick_s cn78xxp1; 2678 }; 2679 2680 typedef union cvmx_pko_l5_sqx_pick cvmx_pko_l5_sqx_pick_t; 2681 2682 /** 2683 * cvmx_pko_l5_sq#_pir 2684 * 2685 * This register has the same bit fields as PKO_L1_SQ()_CIR. 2686 * 2687 */ 2688 union cvmx_pko_l5_sqx_pir { 2689 u64 u64; 2690 struct cvmx_pko_l5_sqx_pir_s { 2691 u64 reserved_41_63 : 23; 2692 u64 burst_exponent : 4; 2693 u64 burst_mantissa : 8; 2694 u64 reserved_17_28 : 12; 2695 u64 rate_divider_exponent : 4; 2696 u64 rate_exponent : 4; 2697 u64 rate_mantissa : 8; 2698 u64 enable : 1; 2699 } s; 2700 struct cvmx_pko_l5_sqx_pir_s cn78xx; 2701 struct cvmx_pko_l5_sqx_pir_s cn78xxp1; 2702 }; 2703 2704 typedef union cvmx_pko_l5_sqx_pir cvmx_pko_l5_sqx_pir_t; 2705 2706 /** 2707 * cvmx_pko_l5_sq#_pointers 2708 * 2709 * This register has the same bit fields as PKO_L4_SQ()_POINTERS. 2710 * 2711 */ 2712 union cvmx_pko_l5_sqx_pointers { 2713 u64 u64; 2714 struct cvmx_pko_l5_sqx_pointers_s { 2715 u64 reserved_26_63 : 38; 2716 u64 prev : 10; 2717 u64 reserved_10_15 : 6; 2718 u64 next : 10; 2719 } s; 2720 struct cvmx_pko_l5_sqx_pointers_s cn78xx; 2721 struct cvmx_pko_l5_sqx_pointers_s cn78xxp1; 2722 }; 2723 2724 typedef union cvmx_pko_l5_sqx_pointers cvmx_pko_l5_sqx_pointers_t; 2725 2726 /** 2727 * cvmx_pko_l5_sq#_red 2728 * 2729 * This register has the same bit fields as PKO_L3_SQ()_YELLOW. 2730 * 2731 */ 2732 union cvmx_pko_l5_sqx_red { 2733 u64 u64; 2734 struct cvmx_pko_l5_sqx_red_s { 2735 u64 reserved_20_63 : 44; 2736 u64 head : 10; 2737 u64 tail : 10; 2738 } s; 2739 struct cvmx_pko_l5_sqx_red_s cn78xx; 2740 struct cvmx_pko_l5_sqx_red_s cn78xxp1; 2741 }; 2742 2743 typedef union cvmx_pko_l5_sqx_red cvmx_pko_l5_sqx_red_t; 2744 2745 /** 2746 * cvmx_pko_l5_sq#_sched_state 2747 * 2748 * This register has the same bit fields as PKO_L2_SQ()_SCHED_STATE. 2749 * 2750 */ 2751 union cvmx_pko_l5_sqx_sched_state { 2752 u64 u64; 2753 struct cvmx_pko_l5_sqx_sched_state_s { 2754 u64 reserved_25_63 : 39; 2755 u64 rr_count : 25; 2756 } s; 2757 struct cvmx_pko_l5_sqx_sched_state_s cn78xx; 2758 struct cvmx_pko_l5_sqx_sched_state_s cn78xxp1; 2759 }; 2760 2761 typedef union cvmx_pko_l5_sqx_sched_state cvmx_pko_l5_sqx_sched_state_t; 2762 2763 /** 2764 * cvmx_pko_l5_sq#_schedule 2765 * 2766 * This register has the same bit fields as PKO_L2_SQ()_SCHEDULE. 2767 * 2768 */ 2769 union cvmx_pko_l5_sqx_schedule { 2770 u64 u64; 2771 struct cvmx_pko_l5_sqx_schedule_s { 2772 u64 reserved_28_63 : 36; 2773 u64 prio : 4; 2774 u64 rr_quantum : 24; 2775 } s; 2776 struct cvmx_pko_l5_sqx_schedule_s cn78xx; 2777 struct cvmx_pko_l5_sqx_schedule_s cn78xxp1; 2778 }; 2779 2780 typedef union cvmx_pko_l5_sqx_schedule cvmx_pko_l5_sqx_schedule_t; 2781 2782 /** 2783 * cvmx_pko_l5_sq#_shape 2784 */ 2785 union cvmx_pko_l5_sqx_shape { 2786 u64 u64; 2787 struct cvmx_pko_l5_sqx_shape_s { 2788 u64 reserved_25_63 : 39; 2789 u64 length_disable : 1; 2790 u64 reserved_13_23 : 11; 2791 u64 yellow_disable : 1; 2792 u64 red_disable : 1; 2793 u64 red_algo : 2; 2794 u64 adjust : 9; 2795 } s; 2796 struct cvmx_pko_l5_sqx_shape_s cn78xx; 2797 struct cvmx_pko_l5_sqx_shape_s cn78xxp1; 2798 }; 2799 2800 typedef union cvmx_pko_l5_sqx_shape cvmx_pko_l5_sqx_shape_t; 2801 2802 /** 2803 * cvmx_pko_l5_sq#_shape_state 2804 * 2805 * This register has the same bit fields as PKO_L2_SQ()_SHAPE_STATE. 2806 * This register must not be written during normal operation. 2807 */ 2808 union cvmx_pko_l5_sqx_shape_state { 2809 u64 u64; 2810 struct cvmx_pko_l5_sqx_shape_state_s { 2811 u64 reserved_60_63 : 4; 2812 u64 tw_timestamp : 6; 2813 u64 color : 2; 2814 u64 pir_accum : 26; 2815 u64 cir_accum : 26; 2816 } s; 2817 struct cvmx_pko_l5_sqx_shape_state_s cn78xx; 2818 struct cvmx_pko_l5_sqx_shape_state_s cn78xxp1; 2819 }; 2820 2821 typedef union cvmx_pko_l5_sqx_shape_state cvmx_pko_l5_sqx_shape_state_t; 2822 2823 /** 2824 * cvmx_pko_l5_sq#_sw_xoff 2825 * 2826 * This register has the same bit fields as PKO_L1_SQ()_SW_XOFF. 2827 * 2828 */ 2829 union cvmx_pko_l5_sqx_sw_xoff { 2830 u64 u64; 2831 struct cvmx_pko_l5_sqx_sw_xoff_s { 2832 u64 reserved_4_63 : 60; 2833 u64 drain_irq : 1; 2834 u64 drain_null_link : 1; 2835 u64 drain : 1; 2836 u64 xoff : 1; 2837 } s; 2838 struct cvmx_pko_l5_sqx_sw_xoff_s cn78xx; 2839 struct cvmx_pko_l5_sqx_sw_xoff_s cn78xxp1; 2840 }; 2841 2842 typedef union cvmx_pko_l5_sqx_sw_xoff cvmx_pko_l5_sqx_sw_xoff_t; 2843 2844 /** 2845 * cvmx_pko_l5_sq#_topology 2846 */ 2847 union cvmx_pko_l5_sqx_topology { 2848 u64 u64; 2849 struct cvmx_pko_l5_sqx_topology_s { 2850 u64 reserved_42_63 : 22; 2851 u64 prio_anchor : 10; 2852 u64 reserved_26_31 : 6; 2853 u64 parent : 10; 2854 u64 reserved_5_15 : 11; 2855 u64 rr_prio : 4; 2856 u64 reserved_0_0 : 1; 2857 } s; 2858 struct cvmx_pko_l5_sqx_topology_s cn78xx; 2859 struct cvmx_pko_l5_sqx_topology_s cn78xxp1; 2860 }; 2861 2862 typedef union cvmx_pko_l5_sqx_topology cvmx_pko_l5_sqx_topology_t; 2863 2864 /** 2865 * cvmx_pko_l5_sq#_yellow 2866 * 2867 * This register has the same bit fields as PKO_L3_SQ()_YELLOW. 2868 * 2869 */ 2870 union cvmx_pko_l5_sqx_yellow { 2871 u64 u64; 2872 struct cvmx_pko_l5_sqx_yellow_s { 2873 u64 reserved_20_63 : 44; 2874 u64 head : 10; 2875 u64 tail : 10; 2876 } s; 2877 struct cvmx_pko_l5_sqx_yellow_s cn78xx; 2878 struct cvmx_pko_l5_sqx_yellow_s cn78xxp1; 2879 }; 2880 2881 typedef union cvmx_pko_l5_sqx_yellow cvmx_pko_l5_sqx_yellow_t; 2882 2883 /** 2884 * cvmx_pko_l5_sq_csr_bus_debug 2885 */ 2886 union cvmx_pko_l5_sq_csr_bus_debug { 2887 u64 u64; 2888 struct cvmx_pko_l5_sq_csr_bus_debug_s { 2889 u64 csr_bus_debug : 64; 2890 } s; 2891 struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xx; 2892 struct cvmx_pko_l5_sq_csr_bus_debug_s cn78xxp1; 2893 }; 2894 2895 typedef union cvmx_pko_l5_sq_csr_bus_debug cvmx_pko_l5_sq_csr_bus_debug_t; 2896 2897 /** 2898 * cvmx_pko_l5_sqa_debug 2899 * 2900 * This register has the same bit fields as PKO_PQA_DEBUG. 2901 * 2902 */ 2903 union cvmx_pko_l5_sqa_debug { 2904 u64 u64; 2905 struct cvmx_pko_l5_sqa_debug_s { 2906 u64 dbg_vec : 64; 2907 } s; 2908 struct cvmx_pko_l5_sqa_debug_s cn78xx; 2909 struct cvmx_pko_l5_sqa_debug_s cn78xxp1; 2910 }; 2911 2912 typedef union cvmx_pko_l5_sqa_debug cvmx_pko_l5_sqa_debug_t; 2913 2914 /** 2915 * cvmx_pko_l5_sqb_debug 2916 * 2917 * This register has the same bit fields as PKO_PQA_DEBUG. 2918 * 2919 */ 2920 union cvmx_pko_l5_sqb_debug { 2921 u64 u64; 2922 struct cvmx_pko_l5_sqb_debug_s { 2923 u64 dbg_vec : 64; 2924 } s; 2925 struct cvmx_pko_l5_sqb_debug_s cn78xx; 2926 struct cvmx_pko_l5_sqb_debug_s cn78xxp1; 2927 }; 2928 2929 typedef union cvmx_pko_l5_sqb_debug cvmx_pko_l5_sqb_debug_t; 2930 2931 /** 2932 * cvmx_pko_lut# 2933 * 2934 * PKO_LUT has a location for each used PKI_CHAN_E. The following table 2935 * shows the mapping between LINK/MAC_NUM's, PKI_CHAN_E channels, and 2936 * PKO_LUT indices. 2937 * 2938 * <pre> 2939 * LINK/ PKI_CHAN_E Corresponding 2940 * MAC_NUM Range PKO_LUT index Description 2941 * ------- ----------- ------------- ----------------- 2942 * 0 0x000-0x03F 0x040-0x07F LBK Loopback 2943 * 1 0x100-0x13F 0x080-0x0BF DPI packet output 2944 * 2 0x800-0x80F 0x000-0x00F BGX0 Logical MAC 0 2945 * 3 0x810-0x81F 0x010-0x01F BGX0 Logical MAC 1 2946 * 4 0x820-0x82F 0x020-0x02F BGX0 Logical MAC 2 2947 * 5 0x830-0x83F 0x030-0x03F BGX0 Logical MAC 3 2948 * </pre> 2949 */ 2950 union cvmx_pko_lutx { 2951 u64 u64; 2952 struct cvmx_pko_lutx_s { 2953 u64 reserved_16_63 : 48; 2954 u64 valid : 1; 2955 u64 reserved_14_14 : 1; 2956 u64 pq_idx : 5; 2957 u64 queue_number : 9; 2958 } s; 2959 struct cvmx_pko_lutx_cn73xx { 2960 u64 reserved_16_63 : 48; 2961 u64 valid : 1; 2962 u64 reserved_13_14 : 2; 2963 u64 pq_idx : 4; 2964 u64 reserved_8_8 : 1; 2965 u64 queue_number : 8; 2966 } cn73xx; 2967 struct cvmx_pko_lutx_s cn78xx; 2968 struct cvmx_pko_lutx_s cn78xxp1; 2969 struct cvmx_pko_lutx_cn73xx cnf75xx; 2970 }; 2971 2972 typedef union cvmx_pko_lutx cvmx_pko_lutx_t; 2973 2974 /** 2975 * cvmx_pko_lut_bist_status 2976 */ 2977 union cvmx_pko_lut_bist_status { 2978 u64 u64; 2979 struct cvmx_pko_lut_bist_status_s { 2980 u64 reserved_1_63 : 63; 2981 u64 bist_status : 1; 2982 } s; 2983 struct cvmx_pko_lut_bist_status_s cn73xx; 2984 struct cvmx_pko_lut_bist_status_s cn78xx; 2985 struct cvmx_pko_lut_bist_status_s cn78xxp1; 2986 struct cvmx_pko_lut_bist_status_s cnf75xx; 2987 }; 2988 2989 typedef union cvmx_pko_lut_bist_status cvmx_pko_lut_bist_status_t; 2990 2991 /** 2992 * cvmx_pko_lut_ecc_ctl0 2993 */ 2994 union cvmx_pko_lut_ecc_ctl0 { 2995 u64 u64; 2996 struct cvmx_pko_lut_ecc_ctl0_s { 2997 u64 c2q_lut_ram_flip : 2; 2998 u64 c2q_lut_ram_cdis : 1; 2999 u64 reserved_0_60 : 61; 3000 } s; 3001 struct cvmx_pko_lut_ecc_ctl0_s cn73xx; 3002 struct cvmx_pko_lut_ecc_ctl0_s cn78xx; 3003 struct cvmx_pko_lut_ecc_ctl0_s cn78xxp1; 3004 struct cvmx_pko_lut_ecc_ctl0_s cnf75xx; 3005 }; 3006 3007 typedef union cvmx_pko_lut_ecc_ctl0 cvmx_pko_lut_ecc_ctl0_t; 3008 3009 /** 3010 * cvmx_pko_lut_ecc_dbe_sts0 3011 */ 3012 union cvmx_pko_lut_ecc_dbe_sts0 { 3013 u64 u64; 3014 struct cvmx_pko_lut_ecc_dbe_sts0_s { 3015 u64 c2q_lut_ram_dbe : 1; 3016 u64 reserved_0_62 : 63; 3017 } s; 3018 struct cvmx_pko_lut_ecc_dbe_sts0_s cn73xx; 3019 struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xx; 3020 struct cvmx_pko_lut_ecc_dbe_sts0_s cn78xxp1; 3021 struct cvmx_pko_lut_ecc_dbe_sts0_s cnf75xx; 3022 }; 3023 3024 typedef union cvmx_pko_lut_ecc_dbe_sts0 cvmx_pko_lut_ecc_dbe_sts0_t; 3025 3026 /** 3027 * cvmx_pko_lut_ecc_dbe_sts_cmb0 3028 */ 3029 union cvmx_pko_lut_ecc_dbe_sts_cmb0 { 3030 u64 u64; 3031 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s { 3032 u64 lut_dbe_cmb0 : 1; 3033 u64 reserved_0_62 : 63; 3034 } s; 3035 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn73xx; 3036 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xx; 3037 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cn78xxp1; 3038 struct cvmx_pko_lut_ecc_dbe_sts_cmb0_s cnf75xx; 3039 }; 3040 3041 typedef union cvmx_pko_lut_ecc_dbe_sts_cmb0 cvmx_pko_lut_ecc_dbe_sts_cmb0_t; 3042 3043 /** 3044 * cvmx_pko_lut_ecc_sbe_sts0 3045 */ 3046 union cvmx_pko_lut_ecc_sbe_sts0 { 3047 u64 u64; 3048 struct cvmx_pko_lut_ecc_sbe_sts0_s { 3049 u64 c2q_lut_ram_sbe : 1; 3050 u64 reserved_0_62 : 63; 3051 } s; 3052 struct cvmx_pko_lut_ecc_sbe_sts0_s cn73xx; 3053 struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xx; 3054 struct cvmx_pko_lut_ecc_sbe_sts0_s cn78xxp1; 3055 struct cvmx_pko_lut_ecc_sbe_sts0_s cnf75xx; 3056 }; 3057 3058 typedef union cvmx_pko_lut_ecc_sbe_sts0 cvmx_pko_lut_ecc_sbe_sts0_t; 3059 3060 /** 3061 * cvmx_pko_lut_ecc_sbe_sts_cmb0 3062 */ 3063 union cvmx_pko_lut_ecc_sbe_sts_cmb0 { 3064 u64 u64; 3065 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s { 3066 u64 lut_sbe_cmb0 : 1; 3067 u64 reserved_0_62 : 63; 3068 } s; 3069 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn73xx; 3070 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xx; 3071 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cn78xxp1; 3072 struct cvmx_pko_lut_ecc_sbe_sts_cmb0_s cnf75xx; 3073 }; 3074 3075 typedef union cvmx_pko_lut_ecc_sbe_sts_cmb0 cvmx_pko_lut_ecc_sbe_sts_cmb0_t; 3076 3077 /** 3078 * cvmx_pko_mac#_cfg 3079 * 3080 * These registers create the links between the MACs and the TxFIFO used to store the data, 3081 * and hold the per-MAC configuration bits. These registers must be disabled (FIFO_NUM set 3082 * to 31) prior to reconfiguration of any of the other bits. 3083 * 3084 * <pre> 3085 * CSR Name Associated MAC 3086 * ------------ ------------------- 3087 * PKO_MAC0_CFG LBK loopback 3088 * PKO_MAC1_CFG DPI packet output 3089 * PKO_MAC2_CFG BGX0 logical MAC 0 3090 * PKO_MAC3_CFG BGX0 logical MAC 1 3091 * PKO_MAC4_CFG BGX0 logical MAC 2 3092 * PKO_MAC5_CFG BGX0 logical MAC 3 3093 * PKO_MAC6_CFG SRIO0 logical MAC 0 3094 * PKO_MAC7_CFG SRIO0 logical MAC 1 3095 * PKO_MAC8_CFG SRIO1 logical MAC 0 3096 * PKO_MAC9_CFG SRIO1 logical MAC 1 3097 * </pre> 3098 */ 3099 union cvmx_pko_macx_cfg { 3100 u64 u64; 3101 struct cvmx_pko_macx_cfg_s { 3102 u64 reserved_17_63 : 47; 3103 u64 min_pad_ena : 1; 3104 u64 fcs_ena : 1; 3105 u64 fcs_sop_off : 8; 3106 u64 skid_max_cnt : 2; 3107 u64 fifo_num : 5; 3108 } s; 3109 struct cvmx_pko_macx_cfg_s cn73xx; 3110 struct cvmx_pko_macx_cfg_s cn78xx; 3111 struct cvmx_pko_macx_cfg_s cn78xxp1; 3112 struct cvmx_pko_macx_cfg_s cnf75xx; 3113 }; 3114 3115 typedef union cvmx_pko_macx_cfg cvmx_pko_macx_cfg_t; 3116 3117 /** 3118 * cvmx_pko_mci0_cred_cnt# 3119 */ 3120 union cvmx_pko_mci0_cred_cntx { 3121 u64 u64; 3122 struct cvmx_pko_mci0_cred_cntx_s { 3123 u64 reserved_13_63 : 51; 3124 u64 cred_cnt : 13; 3125 } s; 3126 struct cvmx_pko_mci0_cred_cntx_s cn78xx; 3127 struct cvmx_pko_mci0_cred_cntx_s cn78xxp1; 3128 }; 3129 3130 typedef union cvmx_pko_mci0_cred_cntx cvmx_pko_mci0_cred_cntx_t; 3131 3132 /** 3133 * cvmx_pko_mci0_max_cred# 3134 */ 3135 union cvmx_pko_mci0_max_credx { 3136 u64 u64; 3137 struct cvmx_pko_mci0_max_credx_s { 3138 u64 reserved_12_63 : 52; 3139 u64 max_cred_lim : 12; 3140 } s; 3141 struct cvmx_pko_mci0_max_credx_s cn78xx; 3142 struct cvmx_pko_mci0_max_credx_s cn78xxp1; 3143 }; 3144 3145 typedef union cvmx_pko_mci0_max_credx cvmx_pko_mci0_max_credx_t; 3146 3147 /** 3148 * cvmx_pko_mci1_cred_cnt# 3149 */ 3150 union cvmx_pko_mci1_cred_cntx { 3151 u64 u64; 3152 struct cvmx_pko_mci1_cred_cntx_s { 3153 u64 reserved_13_63 : 51; 3154 u64 cred_cnt : 13; 3155 } s; 3156 struct cvmx_pko_mci1_cred_cntx_s cn73xx; 3157 struct cvmx_pko_mci1_cred_cntx_s cn78xx; 3158 struct cvmx_pko_mci1_cred_cntx_s cn78xxp1; 3159 struct cvmx_pko_mci1_cred_cntx_s cnf75xx; 3160 }; 3161 3162 typedef union cvmx_pko_mci1_cred_cntx cvmx_pko_mci1_cred_cntx_t; 3163 3164 /** 3165 * cvmx_pko_mci1_max_cred# 3166 */ 3167 union cvmx_pko_mci1_max_credx { 3168 u64 u64; 3169 struct cvmx_pko_mci1_max_credx_s { 3170 u64 reserved_12_63 : 52; 3171 u64 max_cred_lim : 12; 3172 } s; 3173 struct cvmx_pko_mci1_max_credx_s cn73xx; 3174 struct cvmx_pko_mci1_max_credx_s cn78xx; 3175 struct cvmx_pko_mci1_max_credx_s cn78xxp1; 3176 struct cvmx_pko_mci1_max_credx_s cnf75xx; 3177 }; 3178 3179 typedef union cvmx_pko_mci1_max_credx cvmx_pko_mci1_max_credx_t; 3180 3181 /** 3182 * cvmx_pko_mem_count0 3183 * 3184 * Notes: 3185 * Total number of packets seen by PKO, per port 3186 * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 3187 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3188 * CSR read operations to this address can be performed. A read of any entry that has not been 3189 * previously written is illegal and will result in unpredictable CSR read data. 3190 */ 3191 union cvmx_pko_mem_count0 { 3192 u64 u64; 3193 struct cvmx_pko_mem_count0_s { 3194 u64 reserved_32_63 : 32; 3195 u64 count : 32; 3196 } s; 3197 struct cvmx_pko_mem_count0_s cn30xx; 3198 struct cvmx_pko_mem_count0_s cn31xx; 3199 struct cvmx_pko_mem_count0_s cn38xx; 3200 struct cvmx_pko_mem_count0_s cn38xxp2; 3201 struct cvmx_pko_mem_count0_s cn50xx; 3202 struct cvmx_pko_mem_count0_s cn52xx; 3203 struct cvmx_pko_mem_count0_s cn52xxp1; 3204 struct cvmx_pko_mem_count0_s cn56xx; 3205 struct cvmx_pko_mem_count0_s cn56xxp1; 3206 struct cvmx_pko_mem_count0_s cn58xx; 3207 struct cvmx_pko_mem_count0_s cn58xxp1; 3208 struct cvmx_pko_mem_count0_s cn61xx; 3209 struct cvmx_pko_mem_count0_s cn63xx; 3210 struct cvmx_pko_mem_count0_s cn63xxp1; 3211 struct cvmx_pko_mem_count0_s cn66xx; 3212 struct cvmx_pko_mem_count0_s cn68xx; 3213 struct cvmx_pko_mem_count0_s cn68xxp1; 3214 struct cvmx_pko_mem_count0_s cn70xx; 3215 struct cvmx_pko_mem_count0_s cn70xxp1; 3216 struct cvmx_pko_mem_count0_s cnf71xx; 3217 }; 3218 3219 typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t; 3220 3221 /** 3222 * cvmx_pko_mem_count1 3223 * 3224 * Notes: 3225 * Total number of bytes seen by PKO, per port 3226 * A write to this address will clear the entry whose index is specified as COUNT[5:0]. 3227 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3228 * CSR read operations to this address can be performed. A read of any entry that has not been 3229 * previously written is illegal and will result in unpredictable CSR read data. 3230 */ 3231 union cvmx_pko_mem_count1 { 3232 u64 u64; 3233 struct cvmx_pko_mem_count1_s { 3234 u64 reserved_48_63 : 16; 3235 u64 count : 48; 3236 } s; 3237 struct cvmx_pko_mem_count1_s cn30xx; 3238 struct cvmx_pko_mem_count1_s cn31xx; 3239 struct cvmx_pko_mem_count1_s cn38xx; 3240 struct cvmx_pko_mem_count1_s cn38xxp2; 3241 struct cvmx_pko_mem_count1_s cn50xx; 3242 struct cvmx_pko_mem_count1_s cn52xx; 3243 struct cvmx_pko_mem_count1_s cn52xxp1; 3244 struct cvmx_pko_mem_count1_s cn56xx; 3245 struct cvmx_pko_mem_count1_s cn56xxp1; 3246 struct cvmx_pko_mem_count1_s cn58xx; 3247 struct cvmx_pko_mem_count1_s cn58xxp1; 3248 struct cvmx_pko_mem_count1_s cn61xx; 3249 struct cvmx_pko_mem_count1_s cn63xx; 3250 struct cvmx_pko_mem_count1_s cn63xxp1; 3251 struct cvmx_pko_mem_count1_s cn66xx; 3252 struct cvmx_pko_mem_count1_s cn68xx; 3253 struct cvmx_pko_mem_count1_s cn68xxp1; 3254 struct cvmx_pko_mem_count1_s cn70xx; 3255 struct cvmx_pko_mem_count1_s cn70xxp1; 3256 struct cvmx_pko_mem_count1_s cnf71xx; 3257 }; 3258 3259 typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t; 3260 3261 /** 3262 * cvmx_pko_mem_debug0 3263 * 3264 * Notes: 3265 * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0] 3266 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3267 * CSR read operations to this address can be performed. 3268 */ 3269 union cvmx_pko_mem_debug0 { 3270 u64 u64; 3271 struct cvmx_pko_mem_debug0_s { 3272 u64 fau : 28; 3273 u64 cmd : 14; 3274 u64 segs : 6; 3275 u64 size : 16; 3276 } s; 3277 struct cvmx_pko_mem_debug0_s cn30xx; 3278 struct cvmx_pko_mem_debug0_s cn31xx; 3279 struct cvmx_pko_mem_debug0_s cn38xx; 3280 struct cvmx_pko_mem_debug0_s cn38xxp2; 3281 struct cvmx_pko_mem_debug0_s cn50xx; 3282 struct cvmx_pko_mem_debug0_s cn52xx; 3283 struct cvmx_pko_mem_debug0_s cn52xxp1; 3284 struct cvmx_pko_mem_debug0_s cn56xx; 3285 struct cvmx_pko_mem_debug0_s cn56xxp1; 3286 struct cvmx_pko_mem_debug0_s cn58xx; 3287 struct cvmx_pko_mem_debug0_s cn58xxp1; 3288 struct cvmx_pko_mem_debug0_s cn61xx; 3289 struct cvmx_pko_mem_debug0_s cn63xx; 3290 struct cvmx_pko_mem_debug0_s cn63xxp1; 3291 struct cvmx_pko_mem_debug0_s cn66xx; 3292 struct cvmx_pko_mem_debug0_s cn68xx; 3293 struct cvmx_pko_mem_debug0_s cn68xxp1; 3294 struct cvmx_pko_mem_debug0_s cn70xx; 3295 struct cvmx_pko_mem_debug0_s cn70xxp1; 3296 struct cvmx_pko_mem_debug0_s cnf71xx; 3297 }; 3298 3299 typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t; 3300 3301 /** 3302 * cvmx_pko_mem_debug1 3303 * 3304 * Notes: 3305 * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0] 3306 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3307 * CSR read operations to this address can be performed. 3308 */ 3309 union cvmx_pko_mem_debug1 { 3310 u64 u64; 3311 struct cvmx_pko_mem_debug1_s { 3312 u64 i : 1; 3313 u64 back : 4; 3314 u64 pool : 3; 3315 u64 size : 16; 3316 u64 ptr : 40; 3317 } s; 3318 struct cvmx_pko_mem_debug1_s cn30xx; 3319 struct cvmx_pko_mem_debug1_s cn31xx; 3320 struct cvmx_pko_mem_debug1_s cn38xx; 3321 struct cvmx_pko_mem_debug1_s cn38xxp2; 3322 struct cvmx_pko_mem_debug1_s cn50xx; 3323 struct cvmx_pko_mem_debug1_s cn52xx; 3324 struct cvmx_pko_mem_debug1_s cn52xxp1; 3325 struct cvmx_pko_mem_debug1_s cn56xx; 3326 struct cvmx_pko_mem_debug1_s cn56xxp1; 3327 struct cvmx_pko_mem_debug1_s cn58xx; 3328 struct cvmx_pko_mem_debug1_s cn58xxp1; 3329 struct cvmx_pko_mem_debug1_s cn61xx; 3330 struct cvmx_pko_mem_debug1_s cn63xx; 3331 struct cvmx_pko_mem_debug1_s cn63xxp1; 3332 struct cvmx_pko_mem_debug1_s cn66xx; 3333 struct cvmx_pko_mem_debug1_s cn68xx; 3334 struct cvmx_pko_mem_debug1_s cn68xxp1; 3335 struct cvmx_pko_mem_debug1_s cn70xx; 3336 struct cvmx_pko_mem_debug1_s cn70xxp1; 3337 struct cvmx_pko_mem_debug1_s cnf71xx; 3338 }; 3339 3340 typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t; 3341 3342 /** 3343 * cvmx_pko_mem_debug10 3344 * 3345 * Notes: 3346 * Internal per-engine state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2 3347 * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3348 * CSR read operations to this address can be performed. 3349 */ 3350 union cvmx_pko_mem_debug10 { 3351 u64 u64; 3352 struct cvmx_pko_mem_debug10_s { 3353 u64 reserved_0_63 : 64; 3354 } s; 3355 struct cvmx_pko_mem_debug10_cn30xx { 3356 u64 fau : 28; 3357 u64 cmd : 14; 3358 u64 segs : 6; 3359 u64 size : 16; 3360 } cn30xx; 3361 struct cvmx_pko_mem_debug10_cn30xx cn31xx; 3362 struct cvmx_pko_mem_debug10_cn30xx cn38xx; 3363 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; 3364 struct cvmx_pko_mem_debug10_cn50xx { 3365 u64 reserved_49_63 : 15; 3366 u64 ptrs1 : 17; 3367 u64 reserved_17_31 : 15; 3368 u64 ptrs2 : 17; 3369 } cn50xx; 3370 struct cvmx_pko_mem_debug10_cn50xx cn52xx; 3371 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; 3372 struct cvmx_pko_mem_debug10_cn50xx cn56xx; 3373 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; 3374 struct cvmx_pko_mem_debug10_cn50xx cn58xx; 3375 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; 3376 struct cvmx_pko_mem_debug10_cn50xx cn61xx; 3377 struct cvmx_pko_mem_debug10_cn50xx cn63xx; 3378 struct cvmx_pko_mem_debug10_cn50xx cn63xxp1; 3379 struct cvmx_pko_mem_debug10_cn50xx cn66xx; 3380 struct cvmx_pko_mem_debug10_cn50xx cn68xx; 3381 struct cvmx_pko_mem_debug10_cn50xx cn68xxp1; 3382 struct cvmx_pko_mem_debug10_cn50xx cn70xx; 3383 struct cvmx_pko_mem_debug10_cn50xx cn70xxp1; 3384 struct cvmx_pko_mem_debug10_cn50xx cnf71xx; 3385 }; 3386 3387 typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t; 3388 3389 /** 3390 * cvmx_pko_mem_debug11 3391 * 3392 * Notes: 3393 * Internal per-engine state intended for debug use only - pko.out.sta.state[22:0] 3394 * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3395 * CSR read operations to this address can be performed. 3396 */ 3397 union cvmx_pko_mem_debug11 { 3398 u64 u64; 3399 struct cvmx_pko_mem_debug11_s { 3400 u64 i : 1; 3401 u64 back : 4; 3402 u64 pool : 3; 3403 u64 size : 16; 3404 u64 reserved_0_39 : 40; 3405 } s; 3406 struct cvmx_pko_mem_debug11_cn30xx { 3407 u64 i : 1; 3408 u64 back : 4; 3409 u64 pool : 3; 3410 u64 size : 16; 3411 u64 ptr : 40; 3412 } cn30xx; 3413 struct cvmx_pko_mem_debug11_cn30xx cn31xx; 3414 struct cvmx_pko_mem_debug11_cn30xx cn38xx; 3415 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; 3416 struct cvmx_pko_mem_debug11_cn50xx { 3417 u64 reserved_23_63 : 41; 3418 u64 maj : 1; 3419 u64 uid : 3; 3420 u64 sop : 1; 3421 u64 len : 1; 3422 u64 chk : 1; 3423 u64 cnt : 13; 3424 u64 mod : 3; 3425 } cn50xx; 3426 struct cvmx_pko_mem_debug11_cn50xx cn52xx; 3427 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; 3428 struct cvmx_pko_mem_debug11_cn50xx cn56xx; 3429 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; 3430 struct cvmx_pko_mem_debug11_cn50xx cn58xx; 3431 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; 3432 struct cvmx_pko_mem_debug11_cn50xx cn61xx; 3433 struct cvmx_pko_mem_debug11_cn50xx cn63xx; 3434 struct cvmx_pko_mem_debug11_cn50xx cn63xxp1; 3435 struct cvmx_pko_mem_debug11_cn50xx cn66xx; 3436 struct cvmx_pko_mem_debug11_cn50xx cn68xx; 3437 struct cvmx_pko_mem_debug11_cn50xx cn68xxp1; 3438 struct cvmx_pko_mem_debug11_cn50xx cn70xx; 3439 struct cvmx_pko_mem_debug11_cn50xx cn70xxp1; 3440 struct cvmx_pko_mem_debug11_cn50xx cnf71xx; 3441 }; 3442 3443 typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t; 3444 3445 /** 3446 * cvmx_pko_mem_debug12 3447 * 3448 * Notes: 3449 * Internal per-engine x4 state intended for debug use only - pko.out.ctl.cmnd[63:0] 3450 * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3451 * CSR read operations to this address can be performed. 3452 */ 3453 union cvmx_pko_mem_debug12 { 3454 u64 u64; 3455 struct cvmx_pko_mem_debug12_s { 3456 u64 reserved_0_63 : 64; 3457 } s; 3458 struct cvmx_pko_mem_debug12_cn30xx { 3459 u64 data : 64; 3460 } cn30xx; 3461 struct cvmx_pko_mem_debug12_cn30xx cn31xx; 3462 struct cvmx_pko_mem_debug12_cn30xx cn38xx; 3463 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; 3464 struct cvmx_pko_mem_debug12_cn50xx { 3465 u64 fau : 28; 3466 u64 cmd : 14; 3467 u64 segs : 6; 3468 u64 size : 16; 3469 } cn50xx; 3470 struct cvmx_pko_mem_debug12_cn50xx cn52xx; 3471 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; 3472 struct cvmx_pko_mem_debug12_cn50xx cn56xx; 3473 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; 3474 struct cvmx_pko_mem_debug12_cn50xx cn58xx; 3475 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; 3476 struct cvmx_pko_mem_debug12_cn50xx cn61xx; 3477 struct cvmx_pko_mem_debug12_cn50xx cn63xx; 3478 struct cvmx_pko_mem_debug12_cn50xx cn63xxp1; 3479 struct cvmx_pko_mem_debug12_cn50xx cn66xx; 3480 struct cvmx_pko_mem_debug12_cn68xx { 3481 u64 state : 64; 3482 } cn68xx; 3483 struct cvmx_pko_mem_debug12_cn68xx cn68xxp1; 3484 struct cvmx_pko_mem_debug12_cn50xx cn70xx; 3485 struct cvmx_pko_mem_debug12_cn50xx cn70xxp1; 3486 struct cvmx_pko_mem_debug12_cn50xx cnf71xx; 3487 }; 3488 3489 typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t; 3490 3491 /** 3492 * cvmx_pko_mem_debug13 3493 * 3494 * Notes: 3495 * Internal per-engine x4 state intended for debug use only - pko.out.ctl.head[63:0] 3496 * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3497 * CSR read operations to this address can be performed. 3498 */ 3499 union cvmx_pko_mem_debug13 { 3500 u64 u64; 3501 struct cvmx_pko_mem_debug13_s { 3502 u64 reserved_0_63 : 64; 3503 } s; 3504 struct cvmx_pko_mem_debug13_cn30xx { 3505 u64 reserved_51_63 : 13; 3506 u64 widx : 17; 3507 u64 ridx2 : 17; 3508 u64 widx2 : 17; 3509 } cn30xx; 3510 struct cvmx_pko_mem_debug13_cn30xx cn31xx; 3511 struct cvmx_pko_mem_debug13_cn30xx cn38xx; 3512 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; 3513 struct cvmx_pko_mem_debug13_cn50xx { 3514 u64 i : 1; 3515 u64 back : 4; 3516 u64 pool : 3; 3517 u64 size : 16; 3518 u64 ptr : 40; 3519 } cn50xx; 3520 struct cvmx_pko_mem_debug13_cn50xx cn52xx; 3521 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; 3522 struct cvmx_pko_mem_debug13_cn50xx cn56xx; 3523 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; 3524 struct cvmx_pko_mem_debug13_cn50xx cn58xx; 3525 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; 3526 struct cvmx_pko_mem_debug13_cn50xx cn61xx; 3527 struct cvmx_pko_mem_debug13_cn50xx cn63xx; 3528 struct cvmx_pko_mem_debug13_cn50xx cn63xxp1; 3529 struct cvmx_pko_mem_debug13_cn50xx cn66xx; 3530 struct cvmx_pko_mem_debug13_cn68xx { 3531 u64 state : 64; 3532 } cn68xx; 3533 struct cvmx_pko_mem_debug13_cn68xx cn68xxp1; 3534 struct cvmx_pko_mem_debug13_cn50xx cn70xx; 3535 struct cvmx_pko_mem_debug13_cn50xx cn70xxp1; 3536 struct cvmx_pko_mem_debug13_cn50xx cnf71xx; 3537 }; 3538 3539 typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t; 3540 3541 /** 3542 * cvmx_pko_mem_debug14 3543 * 3544 * Notes: 3545 * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0] 3546 * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3547 * CSR read operations to this address can be performed. 3548 */ 3549 union cvmx_pko_mem_debug14 { 3550 u64 u64; 3551 struct cvmx_pko_mem_debug14_s { 3552 u64 reserved_0_63 : 64; 3553 } s; 3554 struct cvmx_pko_mem_debug14_cn30xx { 3555 u64 reserved_17_63 : 47; 3556 u64 ridx : 17; 3557 } cn30xx; 3558 struct cvmx_pko_mem_debug14_cn30xx cn31xx; 3559 struct cvmx_pko_mem_debug14_cn30xx cn38xx; 3560 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; 3561 struct cvmx_pko_mem_debug14_cn52xx { 3562 u64 data : 64; 3563 } cn52xx; 3564 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; 3565 struct cvmx_pko_mem_debug14_cn52xx cn56xx; 3566 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; 3567 struct cvmx_pko_mem_debug14_cn52xx cn61xx; 3568 struct cvmx_pko_mem_debug14_cn52xx cn63xx; 3569 struct cvmx_pko_mem_debug14_cn52xx cn63xxp1; 3570 struct cvmx_pko_mem_debug14_cn52xx cn66xx; 3571 struct cvmx_pko_mem_debug14_cn52xx cn70xx; 3572 struct cvmx_pko_mem_debug14_cn52xx cn70xxp1; 3573 struct cvmx_pko_mem_debug14_cn52xx cnf71xx; 3574 }; 3575 3576 typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t; 3577 3578 /** 3579 * cvmx_pko_mem_debug2 3580 * 3581 * Notes: 3582 * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0] 3583 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3584 * CSR read operations to this address can be performed. 3585 */ 3586 union cvmx_pko_mem_debug2 { 3587 u64 u64; 3588 struct cvmx_pko_mem_debug2_s { 3589 u64 i : 1; 3590 u64 back : 4; 3591 u64 pool : 3; 3592 u64 size : 16; 3593 u64 ptr : 40; 3594 } s; 3595 struct cvmx_pko_mem_debug2_s cn30xx; 3596 struct cvmx_pko_mem_debug2_s cn31xx; 3597 struct cvmx_pko_mem_debug2_s cn38xx; 3598 struct cvmx_pko_mem_debug2_s cn38xxp2; 3599 struct cvmx_pko_mem_debug2_s cn50xx; 3600 struct cvmx_pko_mem_debug2_s cn52xx; 3601 struct cvmx_pko_mem_debug2_s cn52xxp1; 3602 struct cvmx_pko_mem_debug2_s cn56xx; 3603 struct cvmx_pko_mem_debug2_s cn56xxp1; 3604 struct cvmx_pko_mem_debug2_s cn58xx; 3605 struct cvmx_pko_mem_debug2_s cn58xxp1; 3606 struct cvmx_pko_mem_debug2_s cn61xx; 3607 struct cvmx_pko_mem_debug2_s cn63xx; 3608 struct cvmx_pko_mem_debug2_s cn63xxp1; 3609 struct cvmx_pko_mem_debug2_s cn66xx; 3610 struct cvmx_pko_mem_debug2_s cn68xx; 3611 struct cvmx_pko_mem_debug2_s cn68xxp1; 3612 struct cvmx_pko_mem_debug2_s cn70xx; 3613 struct cvmx_pko_mem_debug2_s cn70xxp1; 3614 struct cvmx_pko_mem_debug2_s cnf71xx; 3615 }; 3616 3617 typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t; 3618 3619 /** 3620 * cvmx_pko_mem_debug3 3621 * 3622 * Notes: 3623 * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0] 3624 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3625 * CSR read operations to this address can be performed. 3626 */ 3627 union cvmx_pko_mem_debug3 { 3628 u64 u64; 3629 struct cvmx_pko_mem_debug3_s { 3630 u64 reserved_0_63 : 64; 3631 } s; 3632 struct cvmx_pko_mem_debug3_cn30xx { 3633 u64 i : 1; 3634 u64 back : 4; 3635 u64 pool : 3; 3636 u64 size : 16; 3637 u64 ptr : 40; 3638 } cn30xx; 3639 struct cvmx_pko_mem_debug3_cn30xx cn31xx; 3640 struct cvmx_pko_mem_debug3_cn30xx cn38xx; 3641 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; 3642 struct cvmx_pko_mem_debug3_cn50xx { 3643 u64 data : 64; 3644 } cn50xx; 3645 struct cvmx_pko_mem_debug3_cn50xx cn52xx; 3646 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; 3647 struct cvmx_pko_mem_debug3_cn50xx cn56xx; 3648 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; 3649 struct cvmx_pko_mem_debug3_cn50xx cn58xx; 3650 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; 3651 struct cvmx_pko_mem_debug3_cn50xx cn61xx; 3652 struct cvmx_pko_mem_debug3_cn50xx cn63xx; 3653 struct cvmx_pko_mem_debug3_cn50xx cn63xxp1; 3654 struct cvmx_pko_mem_debug3_cn50xx cn66xx; 3655 struct cvmx_pko_mem_debug3_cn50xx cn68xx; 3656 struct cvmx_pko_mem_debug3_cn50xx cn68xxp1; 3657 struct cvmx_pko_mem_debug3_cn50xx cn70xx; 3658 struct cvmx_pko_mem_debug3_cn50xx cn70xxp1; 3659 struct cvmx_pko_mem_debug3_cn50xx cnf71xx; 3660 }; 3661 3662 typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t; 3663 3664 /** 3665 * cvmx_pko_mem_debug4 3666 * 3667 * Notes: 3668 * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0] 3669 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3670 * CSR read operations to this address can be performed. 3671 */ 3672 union cvmx_pko_mem_debug4 { 3673 u64 u64; 3674 struct cvmx_pko_mem_debug4_s { 3675 u64 reserved_0_63 : 64; 3676 } s; 3677 struct cvmx_pko_mem_debug4_cn30xx { 3678 u64 data : 64; 3679 } cn30xx; 3680 struct cvmx_pko_mem_debug4_cn30xx cn31xx; 3681 struct cvmx_pko_mem_debug4_cn30xx cn38xx; 3682 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; 3683 struct cvmx_pko_mem_debug4_cn50xx { 3684 u64 cmnd_segs : 3; 3685 u64 cmnd_siz : 16; 3686 u64 cmnd_off : 6; 3687 u64 uid : 3; 3688 u64 dread_sop : 1; 3689 u64 init_dwrite : 1; 3690 u64 chk_once : 1; 3691 u64 chk_mode : 1; 3692 u64 active : 1; 3693 u64 static_p : 1; 3694 u64 qos : 3; 3695 u64 qcb_ridx : 5; 3696 u64 qid_off_max : 4; 3697 u64 qid_off : 4; 3698 u64 qid_base : 8; 3699 u64 wait : 1; 3700 u64 minor : 2; 3701 u64 major : 3; 3702 } cn50xx; 3703 struct cvmx_pko_mem_debug4_cn52xx { 3704 u64 curr_siz : 8; 3705 u64 curr_off : 16; 3706 u64 cmnd_segs : 6; 3707 u64 cmnd_siz : 16; 3708 u64 cmnd_off : 6; 3709 u64 uid : 2; 3710 u64 dread_sop : 1; 3711 u64 init_dwrite : 1; 3712 u64 chk_once : 1; 3713 u64 chk_mode : 1; 3714 u64 wait : 1; 3715 u64 minor : 2; 3716 u64 major : 3; 3717 } cn52xx; 3718 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; 3719 struct cvmx_pko_mem_debug4_cn52xx cn56xx; 3720 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; 3721 struct cvmx_pko_mem_debug4_cn50xx cn58xx; 3722 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; 3723 struct cvmx_pko_mem_debug4_cn52xx cn61xx; 3724 struct cvmx_pko_mem_debug4_cn52xx cn63xx; 3725 struct cvmx_pko_mem_debug4_cn52xx cn63xxp1; 3726 struct cvmx_pko_mem_debug4_cn52xx cn66xx; 3727 struct cvmx_pko_mem_debug4_cn68xx { 3728 u64 curr_siz : 9; 3729 u64 curr_off : 16; 3730 u64 cmnd_segs : 6; 3731 u64 cmnd_siz : 16; 3732 u64 cmnd_off : 6; 3733 u64 dread_sop : 1; 3734 u64 init_dwrite : 1; 3735 u64 chk_once : 1; 3736 u64 chk_mode : 1; 3737 u64 reserved_6_6 : 1; 3738 u64 minor : 2; 3739 u64 major : 4; 3740 } cn68xx; 3741 struct cvmx_pko_mem_debug4_cn68xx cn68xxp1; 3742 struct cvmx_pko_mem_debug4_cn52xx cn70xx; 3743 struct cvmx_pko_mem_debug4_cn52xx cn70xxp1; 3744 struct cvmx_pko_mem_debug4_cn52xx cnf71xx; 3745 }; 3746 3747 typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t; 3748 3749 /** 3750 * cvmx_pko_mem_debug5 3751 * 3752 * Notes: 3753 * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64] 3754 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3755 * CSR read operations to this address can be performed. 3756 */ 3757 union cvmx_pko_mem_debug5 { 3758 u64 u64; 3759 struct cvmx_pko_mem_debug5_s { 3760 u64 reserved_0_63 : 64; 3761 } s; 3762 struct cvmx_pko_mem_debug5_cn30xx { 3763 u64 dwri_mod : 1; 3764 u64 dwri_sop : 1; 3765 u64 dwri_len : 1; 3766 u64 dwri_cnt : 13; 3767 u64 cmnd_siz : 16; 3768 u64 uid : 1; 3769 u64 xfer_wor : 1; 3770 u64 xfer_dwr : 1; 3771 u64 cbuf_fre : 1; 3772 u64 reserved_27_27 : 1; 3773 u64 chk_mode : 1; 3774 u64 active : 1; 3775 u64 qos : 3; 3776 u64 qcb_ridx : 5; 3777 u64 qid_off : 3; 3778 u64 qid_base : 7; 3779 u64 wait : 1; 3780 u64 minor : 2; 3781 u64 major : 4; 3782 } cn30xx; 3783 struct cvmx_pko_mem_debug5_cn30xx cn31xx; 3784 struct cvmx_pko_mem_debug5_cn30xx cn38xx; 3785 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; 3786 struct cvmx_pko_mem_debug5_cn50xx { 3787 u64 curr_ptr : 29; 3788 u64 curr_siz : 16; 3789 u64 curr_off : 16; 3790 u64 cmnd_segs : 3; 3791 } cn50xx; 3792 struct cvmx_pko_mem_debug5_cn52xx { 3793 u64 reserved_54_63 : 10; 3794 u64 nxt_inflt : 6; 3795 u64 curr_ptr : 40; 3796 u64 curr_siz : 8; 3797 } cn52xx; 3798 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; 3799 struct cvmx_pko_mem_debug5_cn52xx cn56xx; 3800 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; 3801 struct cvmx_pko_mem_debug5_cn50xx cn58xx; 3802 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; 3803 struct cvmx_pko_mem_debug5_cn61xx { 3804 u64 reserved_56_63 : 8; 3805 u64 ptp : 1; 3806 u64 major_3 : 1; 3807 u64 nxt_inflt : 6; 3808 u64 curr_ptr : 40; 3809 u64 curr_siz : 8; 3810 } cn61xx; 3811 struct cvmx_pko_mem_debug5_cn61xx cn63xx; 3812 struct cvmx_pko_mem_debug5_cn61xx cn63xxp1; 3813 struct cvmx_pko_mem_debug5_cn61xx cn66xx; 3814 struct cvmx_pko_mem_debug5_cn68xx { 3815 u64 reserved_57_63 : 7; 3816 u64 uid : 3; 3817 u64 ptp : 1; 3818 u64 nxt_inflt : 6; 3819 u64 curr_ptr : 40; 3820 u64 curr_siz : 7; 3821 } cn68xx; 3822 struct cvmx_pko_mem_debug5_cn68xx cn68xxp1; 3823 struct cvmx_pko_mem_debug5_cn61xx cn70xx; 3824 struct cvmx_pko_mem_debug5_cn61xx cn70xxp1; 3825 struct cvmx_pko_mem_debug5_cn61xx cnf71xx; 3826 }; 3827 3828 typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t; 3829 3830 /** 3831 * cvmx_pko_mem_debug6 3832 * 3833 * Notes: 3834 * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0] 3835 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3836 * CSR read operations to this address can be performed. 3837 */ 3838 union cvmx_pko_mem_debug6 { 3839 u64 u64; 3840 struct cvmx_pko_mem_debug6_s { 3841 u64 reserved_38_63 : 26; 3842 u64 qos_active : 1; 3843 u64 reserved_0_36 : 37; 3844 } s; 3845 struct cvmx_pko_mem_debug6_cn30xx { 3846 u64 reserved_11_63 : 53; 3847 u64 qid_offm : 3; 3848 u64 static_p : 1; 3849 u64 work_min : 3; 3850 u64 dwri_chk : 1; 3851 u64 dwri_uid : 1; 3852 u64 dwri_mod : 2; 3853 } cn30xx; 3854 struct cvmx_pko_mem_debug6_cn30xx cn31xx; 3855 struct cvmx_pko_mem_debug6_cn30xx cn38xx; 3856 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; 3857 struct cvmx_pko_mem_debug6_cn50xx { 3858 u64 reserved_11_63 : 53; 3859 u64 curr_ptr : 11; 3860 } cn50xx; 3861 struct cvmx_pko_mem_debug6_cn52xx { 3862 u64 reserved_37_63 : 27; 3863 u64 qid_offres : 4; 3864 u64 qid_offths : 4; 3865 u64 preempter : 1; 3866 u64 preemptee : 1; 3867 u64 preempted : 1; 3868 u64 active : 1; 3869 u64 statc : 1; 3870 u64 qos : 3; 3871 u64 qcb_ridx : 5; 3872 u64 qid_offmax : 4; 3873 u64 qid_off : 4; 3874 u64 qid_base : 8; 3875 } cn52xx; 3876 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; 3877 struct cvmx_pko_mem_debug6_cn52xx cn56xx; 3878 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; 3879 struct cvmx_pko_mem_debug6_cn50xx cn58xx; 3880 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; 3881 struct cvmx_pko_mem_debug6_cn52xx cn61xx; 3882 struct cvmx_pko_mem_debug6_cn52xx cn63xx; 3883 struct cvmx_pko_mem_debug6_cn52xx cn63xxp1; 3884 struct cvmx_pko_mem_debug6_cn52xx cn66xx; 3885 struct cvmx_pko_mem_debug6_cn68xx { 3886 u64 reserved_38_63 : 26; 3887 u64 qos_active : 1; 3888 u64 qid_offths : 5; 3889 u64 preempter : 1; 3890 u64 preemptee : 1; 3891 u64 active : 1; 3892 u64 static_p : 1; 3893 u64 qos : 3; 3894 u64 qcb_ridx : 7; 3895 u64 qid_offmax : 5; 3896 u64 qid_off : 5; 3897 u64 qid_base : 8; 3898 } cn68xx; 3899 struct cvmx_pko_mem_debug6_cn68xx cn68xxp1; 3900 struct cvmx_pko_mem_debug6_cn70xx { 3901 u64 reserved_63_37 : 27; 3902 u64 qid_offres : 4; 3903 u64 qid_offths : 4; 3904 u64 preempter : 1; 3905 u64 preemptee : 1; 3906 u64 preempted : 1; 3907 u64 active : 1; 3908 u64 staticb : 1; 3909 u64 qos : 3; 3910 u64 qcb_ridx : 5; 3911 u64 qid_offmax : 4; 3912 u64 qid_off : 4; 3913 u64 qid_base : 8; 3914 } cn70xx; 3915 struct cvmx_pko_mem_debug6_cn70xx cn70xxp1; 3916 struct cvmx_pko_mem_debug6_cn52xx cnf71xx; 3917 }; 3918 3919 typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t; 3920 3921 /** 3922 * cvmx_pko_mem_debug7 3923 * 3924 * Notes: 3925 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0] 3926 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3927 * CSR read operations to this address can be performed. 3928 */ 3929 union cvmx_pko_mem_debug7 { 3930 u64 u64; 3931 struct cvmx_pko_mem_debug7_s { 3932 u64 reserved_0_63 : 64; 3933 } s; 3934 struct cvmx_pko_mem_debug7_cn30xx { 3935 u64 reserved_58_63 : 6; 3936 u64 dwb : 9; 3937 u64 start : 33; 3938 u64 size : 16; 3939 } cn30xx; 3940 struct cvmx_pko_mem_debug7_cn30xx cn31xx; 3941 struct cvmx_pko_mem_debug7_cn30xx cn38xx; 3942 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; 3943 struct cvmx_pko_mem_debug7_cn50xx { 3944 u64 qos : 5; 3945 u64 tail : 1; 3946 u64 buf_siz : 13; 3947 u64 buf_ptr : 33; 3948 u64 qcb_widx : 6; 3949 u64 qcb_ridx : 6; 3950 } cn50xx; 3951 struct cvmx_pko_mem_debug7_cn50xx cn52xx; 3952 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; 3953 struct cvmx_pko_mem_debug7_cn50xx cn56xx; 3954 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; 3955 struct cvmx_pko_mem_debug7_cn50xx cn58xx; 3956 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; 3957 struct cvmx_pko_mem_debug7_cn50xx cn61xx; 3958 struct cvmx_pko_mem_debug7_cn50xx cn63xx; 3959 struct cvmx_pko_mem_debug7_cn50xx cn63xxp1; 3960 struct cvmx_pko_mem_debug7_cn50xx cn66xx; 3961 struct cvmx_pko_mem_debug7_cn68xx { 3962 u64 buf_siz : 11; 3963 u64 buf_ptr : 37; 3964 u64 qcb_widx : 8; 3965 u64 qcb_ridx : 8; 3966 } cn68xx; 3967 struct cvmx_pko_mem_debug7_cn68xx cn68xxp1; 3968 struct cvmx_pko_mem_debug7_cn50xx cn70xx; 3969 struct cvmx_pko_mem_debug7_cn50xx cn70xxp1; 3970 struct cvmx_pko_mem_debug7_cn50xx cnf71xx; 3971 }; 3972 3973 typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t; 3974 3975 /** 3976 * cvmx_pko_mem_debug8 3977 * 3978 * Notes: 3979 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64] 3980 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 3981 * CSR read operations to this address can be performed. 3982 */ 3983 union cvmx_pko_mem_debug8 { 3984 u64 u64; 3985 struct cvmx_pko_mem_debug8_s { 3986 u64 reserved_59_63 : 5; 3987 u64 tail : 1; 3988 u64 reserved_0_57 : 58; 3989 } s; 3990 struct cvmx_pko_mem_debug8_cn30xx { 3991 u64 qos : 5; 3992 u64 tail : 1; 3993 u64 buf_siz : 13; 3994 u64 buf_ptr : 33; 3995 u64 qcb_widx : 6; 3996 u64 qcb_ridx : 6; 3997 } cn30xx; 3998 struct cvmx_pko_mem_debug8_cn30xx cn31xx; 3999 struct cvmx_pko_mem_debug8_cn30xx cn38xx; 4000 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; 4001 struct cvmx_pko_mem_debug8_cn50xx { 4002 u64 reserved_28_63 : 36; 4003 u64 doorbell : 20; 4004 u64 reserved_6_7 : 2; 4005 u64 static_p : 1; 4006 u64 s_tail : 1; 4007 u64 static_q : 1; 4008 u64 qos : 3; 4009 } cn50xx; 4010 struct cvmx_pko_mem_debug8_cn52xx { 4011 u64 reserved_29_63 : 35; 4012 u64 preempter : 1; 4013 u64 doorbell : 20; 4014 u64 reserved_7_7 : 1; 4015 u64 preemptee : 1; 4016 u64 static_p : 1; 4017 u64 s_tail : 1; 4018 u64 static_q : 1; 4019 u64 qos : 3; 4020 } cn52xx; 4021 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; 4022 struct cvmx_pko_mem_debug8_cn52xx cn56xx; 4023 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; 4024 struct cvmx_pko_mem_debug8_cn50xx cn58xx; 4025 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; 4026 struct cvmx_pko_mem_debug8_cn61xx { 4027 u64 reserved_42_63 : 22; 4028 u64 qid_qqos : 8; 4029 u64 reserved_33_33 : 1; 4030 u64 qid_idx : 4; 4031 u64 preempter : 1; 4032 u64 doorbell : 20; 4033 u64 reserved_7_7 : 1; 4034 u64 preemptee : 1; 4035 u64 static_p : 1; 4036 u64 s_tail : 1; 4037 u64 static_q : 1; 4038 u64 qos : 3; 4039 } cn61xx; 4040 struct cvmx_pko_mem_debug8_cn52xx cn63xx; 4041 struct cvmx_pko_mem_debug8_cn52xx cn63xxp1; 4042 struct cvmx_pko_mem_debug8_cn61xx cn66xx; 4043 struct cvmx_pko_mem_debug8_cn68xx { 4044 u64 reserved_50_63 : 14; 4045 u64 qid_qqos : 8; 4046 u64 qid_idx : 5; 4047 u64 preempter : 1; 4048 u64 doorbell : 20; 4049 u64 reserved_9_15 : 7; 4050 u64 qid_qos : 6; 4051 u64 qid_tail : 1; 4052 u64 buf_siz : 2; 4053 } cn68xx; 4054 struct cvmx_pko_mem_debug8_cn68xx cn68xxp1; 4055 struct cvmx_pko_mem_debug8_cn61xx cn70xx; 4056 struct cvmx_pko_mem_debug8_cn61xx cn70xxp1; 4057 struct cvmx_pko_mem_debug8_cn61xx cnf71xx; 4058 }; 4059 4060 typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t; 4061 4062 /** 4063 * cvmx_pko_mem_debug9 4064 * 4065 * Notes: 4066 * Internal per-engine state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3 4067 * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4068 * CSR read operations to this address can be performed. 4069 */ 4070 union cvmx_pko_mem_debug9 { 4071 u64 u64; 4072 struct cvmx_pko_mem_debug9_s { 4073 u64 reserved_49_63 : 15; 4074 u64 ptrs0 : 17; 4075 u64 reserved_0_31 : 32; 4076 } s; 4077 struct cvmx_pko_mem_debug9_cn30xx { 4078 u64 reserved_28_63 : 36; 4079 u64 doorbell : 20; 4080 u64 reserved_5_7 : 3; 4081 u64 s_tail : 1; 4082 u64 static_q : 1; 4083 u64 qos : 3; 4084 } cn30xx; 4085 struct cvmx_pko_mem_debug9_cn30xx cn31xx; 4086 struct cvmx_pko_mem_debug9_cn38xx { 4087 u64 reserved_28_63 : 36; 4088 u64 doorbell : 20; 4089 u64 reserved_6_7 : 2; 4090 u64 static_p : 1; 4091 u64 s_tail : 1; 4092 u64 static_q : 1; 4093 u64 qos : 3; 4094 } cn38xx; 4095 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; 4096 struct cvmx_pko_mem_debug9_cn50xx { 4097 u64 reserved_49_63 : 15; 4098 u64 ptrs0 : 17; 4099 u64 reserved_17_31 : 15; 4100 u64 ptrs3 : 17; 4101 } cn50xx; 4102 struct cvmx_pko_mem_debug9_cn50xx cn52xx; 4103 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; 4104 struct cvmx_pko_mem_debug9_cn50xx cn56xx; 4105 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; 4106 struct cvmx_pko_mem_debug9_cn50xx cn58xx; 4107 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; 4108 struct cvmx_pko_mem_debug9_cn50xx cn61xx; 4109 struct cvmx_pko_mem_debug9_cn50xx cn63xx; 4110 struct cvmx_pko_mem_debug9_cn50xx cn63xxp1; 4111 struct cvmx_pko_mem_debug9_cn50xx cn66xx; 4112 struct cvmx_pko_mem_debug9_cn50xx cn68xx; 4113 struct cvmx_pko_mem_debug9_cn50xx cn68xxp1; 4114 struct cvmx_pko_mem_debug9_cn50xx cn70xx; 4115 struct cvmx_pko_mem_debug9_cn50xx cn70xxp1; 4116 struct cvmx_pko_mem_debug9_cn50xx cnf71xx; 4117 }; 4118 4119 typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t; 4120 4121 /** 4122 * cvmx_pko_mem_iport_ptrs 4123 * 4124 * Notes: 4125 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4126 * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of any 4127 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4128 */ 4129 union cvmx_pko_mem_iport_ptrs { 4130 u64 u64; 4131 struct cvmx_pko_mem_iport_ptrs_s { 4132 u64 reserved_63_63 : 1; 4133 u64 crc : 1; 4134 u64 static_p : 1; 4135 u64 qos_mask : 8; 4136 u64 min_pkt : 3; 4137 u64 reserved_31_49 : 19; 4138 u64 pipe : 7; 4139 u64 reserved_21_23 : 3; 4140 u64 intr : 5; 4141 u64 reserved_13_15 : 3; 4142 u64 eid : 5; 4143 u64 reserved_7_7 : 1; 4144 u64 ipid : 7; 4145 } s; 4146 struct cvmx_pko_mem_iport_ptrs_s cn68xx; 4147 struct cvmx_pko_mem_iport_ptrs_s cn68xxp1; 4148 }; 4149 4150 typedef union cvmx_pko_mem_iport_ptrs cvmx_pko_mem_iport_ptrs_t; 4151 4152 /** 4153 * cvmx_pko_mem_iport_qos 4154 * 4155 * Notes: 4156 * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 4157 * bits in PKO_MEM_IPORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 4158 * operation without affecting any other port state. The engine to which port PID is mapped is engine 4159 * EID. Note that the port to engine mapping must be the same as was previously programmed via the 4160 * PKO_MEM_IPORT_PTRS CSR. 4161 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4162 * CSR read operations to this address can be performed. The index to this CSR is an IPORT. A read of 4163 * any entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4164 */ 4165 union cvmx_pko_mem_iport_qos { 4166 u64 u64; 4167 struct cvmx_pko_mem_iport_qos_s { 4168 u64 reserved_61_63 : 3; 4169 u64 qos_mask : 8; 4170 u64 reserved_13_52 : 40; 4171 u64 eid : 5; 4172 u64 reserved_7_7 : 1; 4173 u64 ipid : 7; 4174 } s; 4175 struct cvmx_pko_mem_iport_qos_s cn68xx; 4176 struct cvmx_pko_mem_iport_qos_s cn68xxp1; 4177 }; 4178 4179 typedef union cvmx_pko_mem_iport_qos cvmx_pko_mem_iport_qos_t; 4180 4181 /** 4182 * cvmx_pko_mem_iqueue_ptrs 4183 * 4184 * Notes: 4185 * Sets the queue to port mapping and the initial command buffer pointer, per queue. Unused queues must 4186 * set BUF_PTR=0. Each queue may map to at most one port. No more than 32 queues may map to a port. 4187 * The set of queues that is mapped to a port must be a contiguous array of queues. The port to which 4188 * queue QID is mapped is port IPID. The index of queue QID in port IPID's queue list is IDX. The last 4189 * queue in port IPID's queue array must have its TAIL bit set. 4190 * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port IPID to which QID is 4191 * mapped as having at least one queue with static priority. If any QID that maps to IPID has static 4192 * priority, then all QID that map to IPID must have STATIC_P set. Queues marked as static priority 4193 * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 4194 * must have its S_TAIL bit set. 4195 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4196 * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 4197 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4198 */ 4199 union cvmx_pko_mem_iqueue_ptrs { 4200 u64 u64; 4201 struct cvmx_pko_mem_iqueue_ptrs_s { 4202 u64 s_tail : 1; 4203 u64 static_p : 1; 4204 u64 static_q : 1; 4205 u64 qos_mask : 8; 4206 u64 buf_ptr : 31; 4207 u64 tail : 1; 4208 u64 index : 5; 4209 u64 reserved_15_15 : 1; 4210 u64 ipid : 7; 4211 u64 qid : 8; 4212 } s; 4213 struct cvmx_pko_mem_iqueue_ptrs_s cn68xx; 4214 struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1; 4215 }; 4216 4217 typedef union cvmx_pko_mem_iqueue_ptrs cvmx_pko_mem_iqueue_ptrs_t; 4218 4219 /** 4220 * cvmx_pko_mem_iqueue_qos 4221 * 4222 * Notes: 4223 * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 4224 * bits in PKO_MEM_IQUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 4225 * operation without affecting any other queue state. The port to which queue QID is mapped is port 4226 * IPID. Note that the queue to port mapping must be the same as was previously programmed via the 4227 * PKO_MEM_IQUEUE_PTRS CSR. 4228 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4229 * CSR read operations to this address can be performed. The index to this CSR is an IQUEUE. A read of any 4230 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4231 */ 4232 union cvmx_pko_mem_iqueue_qos { 4233 u64 u64; 4234 struct cvmx_pko_mem_iqueue_qos_s { 4235 u64 reserved_61_63 : 3; 4236 u64 qos_mask : 8; 4237 u64 reserved_15_52 : 38; 4238 u64 ipid : 7; 4239 u64 qid : 8; 4240 } s; 4241 struct cvmx_pko_mem_iqueue_qos_s cn68xx; 4242 struct cvmx_pko_mem_iqueue_qos_s cn68xxp1; 4243 }; 4244 4245 typedef union cvmx_pko_mem_iqueue_qos cvmx_pko_mem_iqueue_qos_t; 4246 4247 /** 4248 * cvmx_pko_mem_port_ptrs 4249 * 4250 * Notes: 4251 * Sets the port to engine mapping, per port. Ports marked as static priority need not be contiguous, 4252 * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff. If EID==8 4253 * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface. 4254 * EID==15 can be used for unused PKO-internal ports. 4255 * The reset configuration is the following: 4256 * PID EID(ext port) BP_PORT QOS_MASK STATIC_P 4257 * ------------------------------------------- 4258 * 0 0( 0) 0 0xff 0 4259 * 1 1( 1) 1 0xff 0 4260 * 2 2( 2) 2 0xff 0 4261 * 3 3( 3) 3 0xff 0 4262 * 4 0( 0) 4 0xff 0 4263 * 5 1( 1) 5 0xff 0 4264 * 6 2( 2) 6 0xff 0 4265 * 7 3( 3) 7 0xff 0 4266 * 8 0( 0) 8 0xff 0 4267 * 9 1( 1) 9 0xff 0 4268 * 10 2( 2) 10 0xff 0 4269 * 11 3( 3) 11 0xff 0 4270 * 12 0( 0) 12 0xff 0 4271 * 13 1( 1) 13 0xff 0 4272 * 14 2( 2) 14 0xff 0 4273 * 15 3( 3) 15 0xff 0 4274 * ------------------------------------------- 4275 * 16 4(16) 16 0xff 0 4276 * 17 5(17) 17 0xff 0 4277 * 18 6(18) 18 0xff 0 4278 * 19 7(19) 19 0xff 0 4279 * 20 4(16) 20 0xff 0 4280 * 21 5(17) 21 0xff 0 4281 * 22 6(18) 22 0xff 0 4282 * 23 7(19) 23 0xff 0 4283 * 24 4(16) 24 0xff 0 4284 * 25 5(17) 25 0xff 0 4285 * 26 6(18) 26 0xff 0 4286 * 27 7(19) 27 0xff 0 4287 * 28 4(16) 28 0xff 0 4288 * 29 5(17) 29 0xff 0 4289 * 30 6(18) 30 0xff 0 4290 * 31 7(19) 31 0xff 0 4291 * ------------------------------------------- 4292 * 32 8(32) 32 0xff 0 4293 * 33 8(33) 33 0xff 0 4294 * 34 8(34) 34 0xff 0 4295 * 35 8(35) 35 0xff 0 4296 * ------------------------------------------- 4297 * 36 9(36) 36 0xff 0 4298 * 37 9(37) 37 0xff 0 4299 * 38 9(38) 38 0xff 0 4300 * 39 9(39) 39 0xff 0 4301 * 4302 * This CSR is a memory of 48 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4303 * CSR read operations to this address can be performed. A read of any entry that has not been 4304 * previously written is illegal and will result in unpredictable CSR read data. 4305 */ 4306 union cvmx_pko_mem_port_ptrs { 4307 u64 u64; 4308 struct cvmx_pko_mem_port_ptrs_s { 4309 u64 reserved_62_63 : 2; 4310 u64 static_p : 1; 4311 u64 qos_mask : 8; 4312 u64 reserved_16_52 : 37; 4313 u64 bp_port : 6; 4314 u64 eid : 4; 4315 u64 pid : 6; 4316 } s; 4317 struct cvmx_pko_mem_port_ptrs_s cn52xx; 4318 struct cvmx_pko_mem_port_ptrs_s cn52xxp1; 4319 struct cvmx_pko_mem_port_ptrs_s cn56xx; 4320 struct cvmx_pko_mem_port_ptrs_s cn56xxp1; 4321 struct cvmx_pko_mem_port_ptrs_s cn61xx; 4322 struct cvmx_pko_mem_port_ptrs_s cn63xx; 4323 struct cvmx_pko_mem_port_ptrs_s cn63xxp1; 4324 struct cvmx_pko_mem_port_ptrs_s cn66xx; 4325 struct cvmx_pko_mem_port_ptrs_s cn70xx; 4326 struct cvmx_pko_mem_port_ptrs_s cn70xxp1; 4327 struct cvmx_pko_mem_port_ptrs_s cnf71xx; 4328 }; 4329 4330 typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t; 4331 4332 /** 4333 * cvmx_pko_mem_port_qos 4334 * 4335 * Notes: 4336 * Sets the QOS mask, per port. These QOS_MASK bits are logically and physically the same QOS_MASK 4337 * bits in PKO_MEM_PORT_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 4338 * operation without affecting any other port state. The engine to which port PID is mapped is engine 4339 * EID. Note that the port to engine mapping must be the same as was previously programmed via the 4340 * PKO_MEM_PORT_PTRS CSR. 4341 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4342 * CSR read operations to this address can be performed. A read of any entry that has not been 4343 * previously written is illegal and will result in unpredictable CSR read data. 4344 */ 4345 union cvmx_pko_mem_port_qos { 4346 u64 u64; 4347 struct cvmx_pko_mem_port_qos_s { 4348 u64 reserved_61_63 : 3; 4349 u64 qos_mask : 8; 4350 u64 reserved_10_52 : 43; 4351 u64 eid : 4; 4352 u64 pid : 6; 4353 } s; 4354 struct cvmx_pko_mem_port_qos_s cn52xx; 4355 struct cvmx_pko_mem_port_qos_s cn52xxp1; 4356 struct cvmx_pko_mem_port_qos_s cn56xx; 4357 struct cvmx_pko_mem_port_qos_s cn56xxp1; 4358 struct cvmx_pko_mem_port_qos_s cn61xx; 4359 struct cvmx_pko_mem_port_qos_s cn63xx; 4360 struct cvmx_pko_mem_port_qos_s cn63xxp1; 4361 struct cvmx_pko_mem_port_qos_s cn66xx; 4362 struct cvmx_pko_mem_port_qos_s cn70xx; 4363 struct cvmx_pko_mem_port_qos_s cn70xxp1; 4364 struct cvmx_pko_mem_port_qos_s cnf71xx; 4365 }; 4366 4367 typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t; 4368 4369 /** 4370 * cvmx_pko_mem_port_rate0 4371 * 4372 * Notes: 4373 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4374 * CSR read operations to this address can be performed. A read of any entry that has not been 4375 * previously written is illegal and will result in unpredictable CSR read data. 4376 */ 4377 union cvmx_pko_mem_port_rate0 { 4378 u64 u64; 4379 struct cvmx_pko_mem_port_rate0_s { 4380 u64 reserved_51_63 : 13; 4381 u64 rate_word : 19; 4382 u64 rate_pkt : 24; 4383 u64 reserved_7_7 : 1; 4384 u64 pid : 7; 4385 } s; 4386 struct cvmx_pko_mem_port_rate0_cn52xx { 4387 u64 reserved_51_63 : 13; 4388 u64 rate_word : 19; 4389 u64 rate_pkt : 24; 4390 u64 reserved_6_7 : 2; 4391 u64 pid : 6; 4392 } cn52xx; 4393 struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1; 4394 struct cvmx_pko_mem_port_rate0_cn52xx cn56xx; 4395 struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1; 4396 struct cvmx_pko_mem_port_rate0_cn52xx cn61xx; 4397 struct cvmx_pko_mem_port_rate0_cn52xx cn63xx; 4398 struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1; 4399 struct cvmx_pko_mem_port_rate0_cn52xx cn66xx; 4400 struct cvmx_pko_mem_port_rate0_s cn68xx; 4401 struct cvmx_pko_mem_port_rate0_s cn68xxp1; 4402 struct cvmx_pko_mem_port_rate0_cn52xx cn70xx; 4403 struct cvmx_pko_mem_port_rate0_cn52xx cn70xxp1; 4404 struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx; 4405 }; 4406 4407 typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t; 4408 4409 /** 4410 * cvmx_pko_mem_port_rate1 4411 * 4412 * Notes: 4413 * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding 4414 * accumulator to zero. 4415 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4416 * CSR read operations to this address can be performed. A read of any entry that has not been 4417 * previously written is illegal and will result in unpredictable CSR read data. 4418 */ 4419 union cvmx_pko_mem_port_rate1 { 4420 u64 u64; 4421 struct cvmx_pko_mem_port_rate1_s { 4422 u64 reserved_32_63 : 32; 4423 u64 rate_lim : 24; 4424 u64 reserved_7_7 : 1; 4425 u64 pid : 7; 4426 } s; 4427 struct cvmx_pko_mem_port_rate1_cn52xx { 4428 u64 reserved_32_63 : 32; 4429 u64 rate_lim : 24; 4430 u64 reserved_6_7 : 2; 4431 u64 pid : 6; 4432 } cn52xx; 4433 struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1; 4434 struct cvmx_pko_mem_port_rate1_cn52xx cn56xx; 4435 struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1; 4436 struct cvmx_pko_mem_port_rate1_cn52xx cn61xx; 4437 struct cvmx_pko_mem_port_rate1_cn52xx cn63xx; 4438 struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1; 4439 struct cvmx_pko_mem_port_rate1_cn52xx cn66xx; 4440 struct cvmx_pko_mem_port_rate1_s cn68xx; 4441 struct cvmx_pko_mem_port_rate1_s cn68xxp1; 4442 struct cvmx_pko_mem_port_rate1_cn52xx cn70xx; 4443 struct cvmx_pko_mem_port_rate1_cn52xx cn70xxp1; 4444 struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx; 4445 }; 4446 4447 typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t; 4448 4449 /** 4450 * cvmx_pko_mem_queue_ptrs 4451 * 4452 * Notes: 4453 * Sets the queue to port mapping and the initial command buffer pointer, per queue 4454 * Each queue may map to at most one port. No more than 16 queues may map to a port. The set of 4455 * queues that is mapped to a port must be a contiguous array of queues. The port to which queue QID 4456 * is mapped is port PID. The index of queue QID in port PID's queue list is IDX. The last queue in 4457 * port PID's queue array must have its TAIL bit set. Unused queues must be mapped to port 63. 4458 * STATIC_Q marks queue QID as having static priority. STATIC_P marks the port PID to which QID is 4459 * mapped as having at least one queue with static priority. If any QID that maps to PID has static 4460 * priority, then all QID that map to PID must have STATIC_P set. Queues marked as static priority 4461 * must be contiguous and begin at IDX 0. The last queue that is marked as having static priority 4462 * must have its S_TAIL bit set. 4463 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4464 * CSR read operations to this address can be performed. A read of any entry that has not been 4465 * previously written is illegal and will result in unpredictable CSR read data. 4466 */ 4467 union cvmx_pko_mem_queue_ptrs { 4468 u64 u64; 4469 struct cvmx_pko_mem_queue_ptrs_s { 4470 u64 s_tail : 1; 4471 u64 static_p : 1; 4472 u64 static_q : 1; 4473 u64 qos_mask : 8; 4474 u64 buf_ptr : 36; 4475 u64 tail : 1; 4476 u64 index : 3; 4477 u64 port : 6; 4478 u64 queue : 7; 4479 } s; 4480 struct cvmx_pko_mem_queue_ptrs_s cn30xx; 4481 struct cvmx_pko_mem_queue_ptrs_s cn31xx; 4482 struct cvmx_pko_mem_queue_ptrs_s cn38xx; 4483 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; 4484 struct cvmx_pko_mem_queue_ptrs_s cn50xx; 4485 struct cvmx_pko_mem_queue_ptrs_s cn52xx; 4486 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; 4487 struct cvmx_pko_mem_queue_ptrs_s cn56xx; 4488 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; 4489 struct cvmx_pko_mem_queue_ptrs_s cn58xx; 4490 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; 4491 struct cvmx_pko_mem_queue_ptrs_s cn61xx; 4492 struct cvmx_pko_mem_queue_ptrs_s cn63xx; 4493 struct cvmx_pko_mem_queue_ptrs_s cn63xxp1; 4494 struct cvmx_pko_mem_queue_ptrs_s cn66xx; 4495 struct cvmx_pko_mem_queue_ptrs_s cn70xx; 4496 struct cvmx_pko_mem_queue_ptrs_s cn70xxp1; 4497 struct cvmx_pko_mem_queue_ptrs_s cnf71xx; 4498 }; 4499 4500 typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t; 4501 4502 /** 4503 * cvmx_pko_mem_queue_qos 4504 * 4505 * Notes: 4506 * Sets the QOS mask, per queue. These QOS_MASK bits are logically and physically the same QOS_MASK 4507 * bits in PKO_MEM_QUEUE_PTRS. This CSR address allows the QOS_MASK bits to be written during PKO 4508 * operation without affecting any other queue state. The port to which queue QID is mapped is port 4509 * PID. Note that the queue to port mapping must be the same as was previously programmed via the 4510 * PKO_MEM_QUEUE_PTRS CSR. 4511 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4512 * CSR read operations to this address can be performed. A read of any entry that has not been 4513 * previously written is illegal and will result in unpredictable CSR read data. 4514 */ 4515 union cvmx_pko_mem_queue_qos { 4516 u64 u64; 4517 struct cvmx_pko_mem_queue_qos_s { 4518 u64 reserved_61_63 : 3; 4519 u64 qos_mask : 8; 4520 u64 reserved_13_52 : 40; 4521 u64 pid : 6; 4522 u64 qid : 7; 4523 } s; 4524 struct cvmx_pko_mem_queue_qos_s cn30xx; 4525 struct cvmx_pko_mem_queue_qos_s cn31xx; 4526 struct cvmx_pko_mem_queue_qos_s cn38xx; 4527 struct cvmx_pko_mem_queue_qos_s cn38xxp2; 4528 struct cvmx_pko_mem_queue_qos_s cn50xx; 4529 struct cvmx_pko_mem_queue_qos_s cn52xx; 4530 struct cvmx_pko_mem_queue_qos_s cn52xxp1; 4531 struct cvmx_pko_mem_queue_qos_s cn56xx; 4532 struct cvmx_pko_mem_queue_qos_s cn56xxp1; 4533 struct cvmx_pko_mem_queue_qos_s cn58xx; 4534 struct cvmx_pko_mem_queue_qos_s cn58xxp1; 4535 struct cvmx_pko_mem_queue_qos_s cn61xx; 4536 struct cvmx_pko_mem_queue_qos_s cn63xx; 4537 struct cvmx_pko_mem_queue_qos_s cn63xxp1; 4538 struct cvmx_pko_mem_queue_qos_s cn66xx; 4539 struct cvmx_pko_mem_queue_qos_s cn70xx; 4540 struct cvmx_pko_mem_queue_qos_s cn70xxp1; 4541 struct cvmx_pko_mem_queue_qos_s cnf71xx; 4542 }; 4543 4544 typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t; 4545 4546 /** 4547 * cvmx_pko_mem_throttle_int 4548 * 4549 * Notes: 4550 * Writing PACKET and WORD with 0 resets both counts for INT to 0 rather than add 0. 4551 * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the interface INT. 4552 * 4553 * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 4554 * and the interface MAC) on the interface. (When PKO first selects a packet from a PKO queue, it 4555 * increments the counts appropriately. When the interface MAC has (largely) completed sending 4556 * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 4557 * is set and the most-significant bit of the WORD or packet count for a interface is set, 4558 * PKO will not transfer any packets over the interface. Software can limit the amount of 4559 * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 4560 * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 4561 * For example, to limit the number of packets outstanding in the interface to N, preset PACKET for 4562 * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 4563 * 4564 * This CSR is a memory of 32 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4565 * CSR read operations to this address can be performed. The index to this CSR is an INTERFACE. A read of any 4566 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4567 */ 4568 union cvmx_pko_mem_throttle_int { 4569 u64 u64; 4570 struct cvmx_pko_mem_throttle_int_s { 4571 u64 reserved_47_63 : 17; 4572 u64 word : 15; 4573 u64 reserved_14_31 : 18; 4574 u64 packet : 6; 4575 u64 reserved_5_7 : 3; 4576 u64 intr : 5; 4577 } s; 4578 struct cvmx_pko_mem_throttle_int_s cn68xx; 4579 struct cvmx_pko_mem_throttle_int_s cn68xxp1; 4580 }; 4581 4582 typedef union cvmx_pko_mem_throttle_int cvmx_pko_mem_throttle_int_t; 4583 4584 /** 4585 * cvmx_pko_mem_throttle_pipe 4586 * 4587 * Notes: 4588 * Writing PACKET and WORD with 0 resets both counts for PIPE to 0 rather than add 0. 4589 * Otherwise, writes to this CSR add to the existing WORD/PACKET counts for the PKO pipe PIPE. 4590 * 4591 * PKO tracks the number of (8-byte) WORD's and PACKET's in-flight (sum total in both PKO 4592 * and the interface MAC) on the pipe. (When PKO first selects a packet from a PKO queue, it 4593 * increments the counts appropriately. When the interface MAC has (largely) completed sending 4594 * the words/packet, PKO decrements the count appropriately.) When PKO_REG_FLAGS[ENA_THROTTLE] 4595 * is set and the most-significant bit of the WORD or packet count for a PKO pipe is set, 4596 * PKO will not transfer any packets over the PKO pipe. Software can limit the amount of 4597 * packet data and/or the number of packets that OCTEON can send out the chip after receiving backpressure 4598 * from the interface/pipe via these per-pipe throttle counts when PKO_REG_FLAGS[ENA_THROTTLE]=1. 4599 * For example, to limit the number of packets outstanding in the pipe to N, preset PACKET for 4600 * the pipe to the value 0x20-N (0x20 is the smallest PACKET value with the most-significant bit set). 4601 * 4602 * This CSR is a memory of 128 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any 4603 * CSR read operations to this address can be performed. The index to this CSR is a PIPE. A read of any 4604 * entry that has not been previously written is illegal and will result in unpredictable CSR read data. 4605 */ 4606 union cvmx_pko_mem_throttle_pipe { 4607 u64 u64; 4608 struct cvmx_pko_mem_throttle_pipe_s { 4609 u64 reserved_47_63 : 17; 4610 u64 word : 15; 4611 u64 reserved_14_31 : 18; 4612 u64 packet : 6; 4613 u64 reserved_7_7 : 1; 4614 u64 pipe : 7; 4615 } s; 4616 struct cvmx_pko_mem_throttle_pipe_s cn68xx; 4617 struct cvmx_pko_mem_throttle_pipe_s cn68xxp1; 4618 }; 4619 4620 typedef union cvmx_pko_mem_throttle_pipe cvmx_pko_mem_throttle_pipe_t; 4621 4622 /** 4623 * cvmx_pko_ncb_bist_status 4624 * 4625 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 4626 * 4627 */ 4628 union cvmx_pko_ncb_bist_status { 4629 u64 u64; 4630 struct cvmx_pko_ncb_bist_status_s { 4631 u64 ncbi_l2_out_ram_bist_status : 1; 4632 u64 ncbi_pp_out_ram_bist_status : 1; 4633 u64 ncbo_pdm_cmd_dat_ram_bist_status : 1; 4634 u64 ncbi_l2_pdm_pref_ram_bist_status : 1; 4635 u64 ncbo_pp_fif_ram_bist_status : 1; 4636 u64 ncbo_skid_fif_ram_bist_status : 1; 4637 u64 reserved_0_57 : 58; 4638 } s; 4639 struct cvmx_pko_ncb_bist_status_s cn73xx; 4640 struct cvmx_pko_ncb_bist_status_s cn78xx; 4641 struct cvmx_pko_ncb_bist_status_s cn78xxp1; 4642 struct cvmx_pko_ncb_bist_status_s cnf75xx; 4643 }; 4644 4645 typedef union cvmx_pko_ncb_bist_status cvmx_pko_ncb_bist_status_t; 4646 4647 /** 4648 * cvmx_pko_ncb_ecc_ctl0 4649 */ 4650 union cvmx_pko_ncb_ecc_ctl0 { 4651 u64 u64; 4652 struct cvmx_pko_ncb_ecc_ctl0_s { 4653 u64 ncbi_l2_out_ram_flip : 2; 4654 u64 ncbi_l2_out_ram_cdis : 1; 4655 u64 ncbi_pp_out_ram_flip : 2; 4656 u64 ncbi_pp_out_ram_cdis : 1; 4657 u64 ncbo_pdm_cmd_dat_ram_flip : 2; 4658 u64 ncbo_pdm_cmd_dat_ram_cdis : 1; 4659 u64 ncbi_l2_pdm_pref_ram_flip : 2; 4660 u64 ncbi_l2_pdm_pref_ram_cdis : 1; 4661 u64 ncbo_pp_fif_ram_flip : 2; 4662 u64 ncbo_pp_fif_ram_cdis : 1; 4663 u64 ncbo_skid_fif_ram_flip : 2; 4664 u64 ncbo_skid_fif_ram_cdis : 1; 4665 u64 reserved_0_45 : 46; 4666 } s; 4667 struct cvmx_pko_ncb_ecc_ctl0_s cn73xx; 4668 struct cvmx_pko_ncb_ecc_ctl0_s cn78xx; 4669 struct cvmx_pko_ncb_ecc_ctl0_s cn78xxp1; 4670 struct cvmx_pko_ncb_ecc_ctl0_s cnf75xx; 4671 }; 4672 4673 typedef union cvmx_pko_ncb_ecc_ctl0 cvmx_pko_ncb_ecc_ctl0_t; 4674 4675 /** 4676 * cvmx_pko_ncb_ecc_dbe_sts0 4677 */ 4678 union cvmx_pko_ncb_ecc_dbe_sts0 { 4679 u64 u64; 4680 struct cvmx_pko_ncb_ecc_dbe_sts0_s { 4681 u64 ncbi_l2_out_ram_dbe : 1; 4682 u64 ncbi_pp_out_ram_dbe : 1; 4683 u64 ncbo_pdm_cmd_dat_ram_dbe : 1; 4684 u64 ncbi_l2_pdm_pref_ram_dbe : 1; 4685 u64 ncbo_pp_fif_ram_dbe : 1; 4686 u64 ncbo_skid_fif_ram_dbe : 1; 4687 u64 reserved_0_57 : 58; 4688 } s; 4689 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn73xx; 4690 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn78xx; 4691 struct cvmx_pko_ncb_ecc_dbe_sts0_s cn78xxp1; 4692 struct cvmx_pko_ncb_ecc_dbe_sts0_s cnf75xx; 4693 }; 4694 4695 typedef union cvmx_pko_ncb_ecc_dbe_sts0 cvmx_pko_ncb_ecc_dbe_sts0_t; 4696 4697 /** 4698 * cvmx_pko_ncb_ecc_dbe_sts_cmb0 4699 */ 4700 union cvmx_pko_ncb_ecc_dbe_sts_cmb0 { 4701 u64 u64; 4702 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s { 4703 u64 ncb_dbe_cmb0 : 1; 4704 u64 reserved_0_62 : 63; 4705 } s; 4706 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn73xx; 4707 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn78xx; 4708 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cn78xxp1; 4709 struct cvmx_pko_ncb_ecc_dbe_sts_cmb0_s cnf75xx; 4710 }; 4711 4712 typedef union cvmx_pko_ncb_ecc_dbe_sts_cmb0 cvmx_pko_ncb_ecc_dbe_sts_cmb0_t; 4713 4714 /** 4715 * cvmx_pko_ncb_ecc_sbe_sts0 4716 */ 4717 union cvmx_pko_ncb_ecc_sbe_sts0 { 4718 u64 u64; 4719 struct cvmx_pko_ncb_ecc_sbe_sts0_s { 4720 u64 ncbi_l2_out_ram_sbe : 1; 4721 u64 ncbi_pp_out_ram_sbe : 1; 4722 u64 ncbo_pdm_cmd_dat_ram_sbe : 1; 4723 u64 ncbi_l2_pdm_pref_ram_sbe : 1; 4724 u64 ncbo_pp_fif_ram_sbe : 1; 4725 u64 ncbo_skid_fif_ram_sbe : 1; 4726 u64 reserved_0_57 : 58; 4727 } s; 4728 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn73xx; 4729 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn78xx; 4730 struct cvmx_pko_ncb_ecc_sbe_sts0_s cn78xxp1; 4731 struct cvmx_pko_ncb_ecc_sbe_sts0_s cnf75xx; 4732 }; 4733 4734 typedef union cvmx_pko_ncb_ecc_sbe_sts0 cvmx_pko_ncb_ecc_sbe_sts0_t; 4735 4736 /** 4737 * cvmx_pko_ncb_ecc_sbe_sts_cmb0 4738 */ 4739 union cvmx_pko_ncb_ecc_sbe_sts_cmb0 { 4740 u64 u64; 4741 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s { 4742 u64 ncb_sbe_cmb0 : 1; 4743 u64 reserved_0_62 : 63; 4744 } s; 4745 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn73xx; 4746 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn78xx; 4747 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cn78xxp1; 4748 struct cvmx_pko_ncb_ecc_sbe_sts_cmb0_s cnf75xx; 4749 }; 4750 4751 typedef union cvmx_pko_ncb_ecc_sbe_sts_cmb0 cvmx_pko_ncb_ecc_sbe_sts_cmb0_t; 4752 4753 /** 4754 * cvmx_pko_ncb_int 4755 */ 4756 union cvmx_pko_ncb_int { 4757 u64 u64; 4758 struct cvmx_pko_ncb_int_s { 4759 u64 reserved_2_63 : 62; 4760 u64 tso_segment_cnt : 1; 4761 u64 ncb_tx_error : 1; 4762 } s; 4763 struct cvmx_pko_ncb_int_s cn73xx; 4764 struct cvmx_pko_ncb_int_s cn78xx; 4765 struct cvmx_pko_ncb_int_s cn78xxp1; 4766 struct cvmx_pko_ncb_int_s cnf75xx; 4767 }; 4768 4769 typedef union cvmx_pko_ncb_int cvmx_pko_ncb_int_t; 4770 4771 /** 4772 * cvmx_pko_ncb_tx_err_info 4773 */ 4774 union cvmx_pko_ncb_tx_err_info { 4775 u64 u64; 4776 struct cvmx_pko_ncb_tx_err_info_s { 4777 u64 reserved_32_63 : 32; 4778 u64 wcnt : 5; 4779 u64 src : 12; 4780 u64 dst : 8; 4781 u64 tag : 4; 4782 u64 eot : 1; 4783 u64 sot : 1; 4784 u64 valid : 1; 4785 } s; 4786 struct cvmx_pko_ncb_tx_err_info_s cn73xx; 4787 struct cvmx_pko_ncb_tx_err_info_s cn78xx; 4788 struct cvmx_pko_ncb_tx_err_info_s cn78xxp1; 4789 struct cvmx_pko_ncb_tx_err_info_s cnf75xx; 4790 }; 4791 4792 typedef union cvmx_pko_ncb_tx_err_info cvmx_pko_ncb_tx_err_info_t; 4793 4794 /** 4795 * cvmx_pko_ncb_tx_err_word 4796 */ 4797 union cvmx_pko_ncb_tx_err_word { 4798 u64 u64; 4799 struct cvmx_pko_ncb_tx_err_word_s { 4800 u64 err_word : 64; 4801 } s; 4802 struct cvmx_pko_ncb_tx_err_word_s cn73xx; 4803 struct cvmx_pko_ncb_tx_err_word_s cn78xx; 4804 struct cvmx_pko_ncb_tx_err_word_s cn78xxp1; 4805 struct cvmx_pko_ncb_tx_err_word_s cnf75xx; 4806 }; 4807 4808 typedef union cvmx_pko_ncb_tx_err_word cvmx_pko_ncb_tx_err_word_t; 4809 4810 /** 4811 * cvmx_pko_pdm_bist_status 4812 * 4813 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 4814 * 4815 */ 4816 union cvmx_pko_pdm_bist_status { 4817 u64 u64; 4818 struct cvmx_pko_pdm_bist_status_s { 4819 u64 flshb_cache_lo_ram_bist_status : 1; 4820 u64 flshb_cache_hi_ram_bist_status : 1; 4821 u64 isrm_ca_iinst_ram_bist_status : 1; 4822 u64 isrm_ca_cm_ram_bist_status : 1; 4823 u64 isrm_st_ram2_bist_status : 1; 4824 u64 isrm_st_ram1_bist_status : 1; 4825 u64 isrm_st_ram0_bist_status : 1; 4826 u64 isrd_st_ram3_bist_status : 1; 4827 u64 isrd_st_ram2_bist_status : 1; 4828 u64 isrd_st_ram1_bist_status : 1; 4829 u64 isrd_st_ram0_bist_status : 1; 4830 u64 drp_hi_ram_bist_status : 1; 4831 u64 drp_lo_ram_bist_status : 1; 4832 u64 dwp_hi_ram_bist_status : 1; 4833 u64 dwp_lo_ram_bist_status : 1; 4834 u64 mwp_hi_ram_bist_status : 1; 4835 u64 mwp_lo_ram_bist_status : 1; 4836 u64 fillb_m_rsp_ram_hi_bist_status : 1; 4837 u64 fillb_m_rsp_ram_lo_bist_status : 1; 4838 u64 fillb_d_rsp_ram_hi_bist_status : 1; 4839 u64 fillb_d_rsp_ram_lo_bist_status : 1; 4840 u64 fillb_d_rsp_dat_fifo_bist_status : 1; 4841 u64 fillb_m_rsp_dat_fifo_bist_status : 1; 4842 u64 flshb_m_dat_ram_bist_status : 1; 4843 u64 flshb_d_dat_ram_bist_status : 1; 4844 u64 minpad_ram_bist_status : 1; 4845 u64 mwp_hi_spt_ram_bist_status : 1; 4846 u64 mwp_lo_spt_ram_bist_status : 1; 4847 u64 buf_wm_ram_bist_status : 1; 4848 u64 reserved_0_34 : 35; 4849 } s; 4850 struct cvmx_pko_pdm_bist_status_s cn73xx; 4851 struct cvmx_pko_pdm_bist_status_s cn78xx; 4852 struct cvmx_pko_pdm_bist_status_s cn78xxp1; 4853 struct cvmx_pko_pdm_bist_status_s cnf75xx; 4854 }; 4855 4856 typedef union cvmx_pko_pdm_bist_status cvmx_pko_pdm_bist_status_t; 4857 4858 /** 4859 * cvmx_pko_pdm_cfg 4860 */ 4861 union cvmx_pko_pdm_cfg { 4862 u64 u64; 4863 struct cvmx_pko_pdm_cfg_s { 4864 u64 reserved_13_63 : 51; 4865 u64 dis_lpd_w2r_fill : 1; 4866 u64 en_fr_w2r_ptr_swp : 1; 4867 u64 dis_flsh_cache : 1; 4868 u64 pko_pad_minlen : 7; 4869 u64 diag_mode : 1; 4870 u64 alloc_lds : 1; 4871 u64 alloc_sts : 1; 4872 } s; 4873 struct cvmx_pko_pdm_cfg_s cn73xx; 4874 struct cvmx_pko_pdm_cfg_s cn78xx; 4875 struct cvmx_pko_pdm_cfg_s cn78xxp1; 4876 struct cvmx_pko_pdm_cfg_s cnf75xx; 4877 }; 4878 4879 typedef union cvmx_pko_pdm_cfg cvmx_pko_pdm_cfg_t; 4880 4881 /** 4882 * cvmx_pko_pdm_cfg_dbg 4883 */ 4884 union cvmx_pko_pdm_cfg_dbg { 4885 u64 u64; 4886 struct cvmx_pko_pdm_cfg_dbg_s { 4887 u64 reserved_32_63 : 32; 4888 u64 cp_stall_thrshld : 32; 4889 } s; 4890 struct cvmx_pko_pdm_cfg_dbg_s cn73xx; 4891 struct cvmx_pko_pdm_cfg_dbg_s cn78xx; 4892 struct cvmx_pko_pdm_cfg_dbg_s cn78xxp1; 4893 struct cvmx_pko_pdm_cfg_dbg_s cnf75xx; 4894 }; 4895 4896 typedef union cvmx_pko_pdm_cfg_dbg cvmx_pko_pdm_cfg_dbg_t; 4897 4898 /** 4899 * cvmx_pko_pdm_cp_dbg 4900 */ 4901 union cvmx_pko_pdm_cp_dbg { 4902 u64 u64; 4903 struct cvmx_pko_pdm_cp_dbg_s { 4904 u64 reserved_16_63 : 48; 4905 u64 stateless_fif_cnt : 6; 4906 u64 reserved_5_9 : 5; 4907 u64 op_fif_not_full : 5; 4908 } s; 4909 struct cvmx_pko_pdm_cp_dbg_s cn73xx; 4910 struct cvmx_pko_pdm_cp_dbg_s cn78xx; 4911 struct cvmx_pko_pdm_cp_dbg_s cn78xxp1; 4912 struct cvmx_pko_pdm_cp_dbg_s cnf75xx; 4913 }; 4914 4915 typedef union cvmx_pko_pdm_cp_dbg cvmx_pko_pdm_cp_dbg_t; 4916 4917 /** 4918 * cvmx_pko_pdm_dq#_minpad 4919 */ 4920 union cvmx_pko_pdm_dqx_minpad { 4921 u64 u64; 4922 struct cvmx_pko_pdm_dqx_minpad_s { 4923 u64 reserved_1_63 : 63; 4924 u64 minpad : 1; 4925 } s; 4926 struct cvmx_pko_pdm_dqx_minpad_s cn73xx; 4927 struct cvmx_pko_pdm_dqx_minpad_s cn78xx; 4928 struct cvmx_pko_pdm_dqx_minpad_s cn78xxp1; 4929 struct cvmx_pko_pdm_dqx_minpad_s cnf75xx; 4930 }; 4931 4932 typedef union cvmx_pko_pdm_dqx_minpad cvmx_pko_pdm_dqx_minpad_t; 4933 4934 /** 4935 * cvmx_pko_pdm_drpbuf_dbg 4936 */ 4937 union cvmx_pko_pdm_drpbuf_dbg { 4938 u64 u64; 4939 struct cvmx_pko_pdm_drpbuf_dbg_s { 4940 u64 reserved_43_63 : 21; 4941 u64 sel_nxt_ptr : 1; 4942 u64 load_val : 1; 4943 u64 rdy : 1; 4944 u64 cur_state : 3; 4945 u64 reserved_33_36 : 4; 4946 u64 track_rd_cnt : 6; 4947 u64 track_wr_cnt : 6; 4948 u64 reserved_17_20 : 4; 4949 u64 mem_addr : 13; 4950 u64 mem_en : 4; 4951 } s; 4952 struct cvmx_pko_pdm_drpbuf_dbg_s cn73xx; 4953 struct cvmx_pko_pdm_drpbuf_dbg_s cn78xx; 4954 struct cvmx_pko_pdm_drpbuf_dbg_s cn78xxp1; 4955 struct cvmx_pko_pdm_drpbuf_dbg_s cnf75xx; 4956 }; 4957 4958 typedef union cvmx_pko_pdm_drpbuf_dbg cvmx_pko_pdm_drpbuf_dbg_t; 4959 4960 /** 4961 * cvmx_pko_pdm_dwpbuf_dbg 4962 */ 4963 union cvmx_pko_pdm_dwpbuf_dbg { 4964 u64 u64; 4965 struct cvmx_pko_pdm_dwpbuf_dbg_s { 4966 u64 reserved_48_63 : 16; 4967 u64 cmd_proc : 1; 4968 u64 reserved_46_46 : 1; 4969 u64 mem_data_val : 1; 4970 u64 insert_np : 1; 4971 u64 reserved_43_43 : 1; 4972 u64 sel_nxt_ptr : 1; 4973 u64 load_val : 1; 4974 u64 rdy : 1; 4975 u64 cur_state : 3; 4976 u64 mem_rdy : 1; 4977 u64 reserved_33_35 : 3; 4978 u64 track_rd_cnt : 6; 4979 u64 track_wr_cnt : 6; 4980 u64 reserved_19_20 : 2; 4981 u64 insert_dp : 2; 4982 u64 mem_addr : 13; 4983 u64 mem_en : 4; 4984 } s; 4985 struct cvmx_pko_pdm_dwpbuf_dbg_cn73xx { 4986 u64 reserved_48_63 : 16; 4987 u64 cmd_proc : 1; 4988 u64 reserved_46_46 : 1; 4989 u64 mem_data_val : 1; 4990 u64 insert_np : 1; 4991 u64 reserved_43_43 : 1; 4992 u64 sel_nxt_ptr : 1; 4993 u64 load_val : 1; 4994 u64 rdy : 1; 4995 u64 reserved_37_39 : 3; 4996 u64 mem_rdy : 1; 4997 u64 reserved_19_35 : 17; 4998 u64 insert_dp : 2; 4999 u64 reserved_15_16 : 2; 5000 u64 mem_addr : 11; 5001 u64 mem_en : 4; 5002 } cn73xx; 5003 struct cvmx_pko_pdm_dwpbuf_dbg_s cn78xx; 5004 struct cvmx_pko_pdm_dwpbuf_dbg_s cn78xxp1; 5005 struct cvmx_pko_pdm_dwpbuf_dbg_cn73xx cnf75xx; 5006 }; 5007 5008 typedef union cvmx_pko_pdm_dwpbuf_dbg cvmx_pko_pdm_dwpbuf_dbg_t; 5009 5010 /** 5011 * cvmx_pko_pdm_ecc_ctl0 5012 */ 5013 union cvmx_pko_pdm_ecc_ctl0 { 5014 u64 u64; 5015 struct cvmx_pko_pdm_ecc_ctl0_s { 5016 u64 flshb_cache_lo_ram_flip : 2; 5017 u64 flshb_cache_lo_ram_cdis : 1; 5018 u64 flshb_cache_hi_ram_flip : 2; 5019 u64 flshb_cache_hi_ram_cdis : 1; 5020 u64 isrm_ca_iinst_ram_flip : 2; 5021 u64 isrm_ca_iinst_ram_cdis : 1; 5022 u64 isrm_ca_cm_ram_flip : 2; 5023 u64 isrm_ca_cm_ram_cdis : 1; 5024 u64 isrm_st_ram2_flip : 2; 5025 u64 isrm_st_ram2_cdis : 1; 5026 u64 isrm_st_ram1_flip : 2; 5027 u64 isrm_st_ram1_cdis : 1; 5028 u64 isrm_st_ram0_flip : 2; 5029 u64 isrm_st_ram0_cdis : 1; 5030 u64 isrd_st_ram3_flip : 2; 5031 u64 isrd_st_ram3_cdis : 1; 5032 u64 isrd_st_ram2_flip : 2; 5033 u64 isrd_st_ram2_cdis : 1; 5034 u64 isrd_st_ram1_flip : 2; 5035 u64 isrd_st_ram1_cdis : 1; 5036 u64 isrd_st_ram0_flip : 2; 5037 u64 isrd_st_ram0_cdis : 1; 5038 u64 drp_hi_ram_flip : 2; 5039 u64 drp_hi_ram_cdis : 1; 5040 u64 drp_lo_ram_flip : 2; 5041 u64 drp_lo_ram_cdis : 1; 5042 u64 dwp_hi_ram_flip : 2; 5043 u64 dwp_hi_ram_cdis : 1; 5044 u64 dwp_lo_ram_flip : 2; 5045 u64 dwp_lo_ram_cdis : 1; 5046 u64 mwp_hi_ram_flip : 2; 5047 u64 mwp_hi_ram_cdis : 1; 5048 u64 mwp_lo_ram_flip : 2; 5049 u64 mwp_lo_ram_cdis : 1; 5050 u64 fillb_m_rsp_ram_hi_flip : 2; 5051 u64 fillb_m_rsp_ram_hi_cdis : 1; 5052 u64 fillb_m_rsp_ram_lo_flip : 2; 5053 u64 fillb_m_rsp_ram_lo_cdis : 1; 5054 u64 fillb_d_rsp_ram_hi_flip : 2; 5055 u64 fillb_d_rsp_ram_hi_cdis : 1; 5056 u64 fillb_d_rsp_ram_lo_flip : 2; 5057 u64 fillb_d_rsp_ram_lo_cdis : 1; 5058 u64 reserved_0_0 : 1; 5059 } s; 5060 struct cvmx_pko_pdm_ecc_ctl0_cn73xx { 5061 u64 flshb_cache_lo_ram_flip : 2; 5062 u64 flshb_cache_lo_ram_cdis : 1; 5063 u64 flshb_cache_hi_ram_flip : 2; 5064 u64 flshb_cache_hi_ram_cdis : 1; 5065 u64 isrm_ca_iinst_ram_flip : 2; 5066 u64 isrm_ca_iinst_ram_cdis : 1; 5067 u64 isrm_ca_cm_ram_flip : 2; 5068 u64 isrm_ca_cm_ram_cdis : 1; 5069 u64 isrm_st_ram2_flip : 2; 5070 u64 isrm_st_ram2_cdis : 1; 5071 u64 isrm_st_ram1_flip : 2; 5072 u64 isrm_st_ram1_cdis : 1; 5073 u64 isrm_st_ram0_flip : 2; 5074 u64 isrm_st_ram0_cdis : 1; 5075 u64 isrd_st_ram3_flip : 2; 5076 u64 isrd_st_ram3_cdis : 1; 5077 u64 isrd_st_ram2_flip : 2; 5078 u64 isrd_st_ram2_cdis : 1; 5079 u64 isrd_st_ram1_flip : 2; 5080 u64 isrd_st_ram1_cdis : 1; 5081 u64 isrd_st_ram0_flip : 2; 5082 u64 isrd_st_ram0_cdis : 1; 5083 u64 drp_hi_ram_flip : 2; 5084 u64 drp_hi_ram_cdis : 1; 5085 u64 drp_lo_ram_flip : 2; 5086 u64 drp_lo_ram_cdis : 1; 5087 u64 dwp_hi_ram_flip : 2; 5088 u64 dwp_hi_ram_cdis : 1; 5089 u64 dwp_lo_ram_flip : 2; 5090 u64 dwp_lo_ram_cdis : 1; 5091 u64 reserved_13_18 : 6; 5092 u64 fillb_m_rsp_ram_hi_flip : 2; 5093 u64 fillb_m_rsp_ram_hi_cdis : 1; 5094 u64 fillb_m_rsp_ram_lo_flip : 2; 5095 u64 fillb_m_rsp_ram_lo_cdis : 1; 5096 u64 fillb_d_rsp_ram_hi_flip : 2; 5097 u64 fillb_d_rsp_ram_hi_cdis : 1; 5098 u64 fillb_d_rsp_ram_lo_flip : 2; 5099 u64 fillb_d_rsp_ram_lo_cdis : 1; 5100 u64 reserved_0_0 : 1; 5101 } cn73xx; 5102 struct cvmx_pko_pdm_ecc_ctl0_s cn78xx; 5103 struct cvmx_pko_pdm_ecc_ctl0_s cn78xxp1; 5104 struct cvmx_pko_pdm_ecc_ctl0_cn73xx cnf75xx; 5105 }; 5106 5107 typedef union cvmx_pko_pdm_ecc_ctl0 cvmx_pko_pdm_ecc_ctl0_t; 5108 5109 /** 5110 * cvmx_pko_pdm_ecc_ctl1 5111 */ 5112 union cvmx_pko_pdm_ecc_ctl1 { 5113 u64 u64; 5114 struct cvmx_pko_pdm_ecc_ctl1_s { 5115 u64 reserved_15_63 : 49; 5116 u64 buf_wm_ram_flip : 2; 5117 u64 buf_wm_ram_cdis : 1; 5118 u64 mwp_mem0_ram_flip : 2; 5119 u64 mwp_mem1_ram_flip : 2; 5120 u64 mwp_mem2_ram_flip : 2; 5121 u64 mwp_mem3_ram_flip : 2; 5122 u64 mwp_ram_cdis : 1; 5123 u64 minpad_ram_flip : 2; 5124 u64 minpad_ram_cdis : 1; 5125 } s; 5126 struct cvmx_pko_pdm_ecc_ctl1_s cn73xx; 5127 struct cvmx_pko_pdm_ecc_ctl1_s cn78xx; 5128 struct cvmx_pko_pdm_ecc_ctl1_s cn78xxp1; 5129 struct cvmx_pko_pdm_ecc_ctl1_s cnf75xx; 5130 }; 5131 5132 typedef union cvmx_pko_pdm_ecc_ctl1 cvmx_pko_pdm_ecc_ctl1_t; 5133 5134 /** 5135 * cvmx_pko_pdm_ecc_dbe_sts0 5136 */ 5137 union cvmx_pko_pdm_ecc_dbe_sts0 { 5138 u64 u64; 5139 struct cvmx_pko_pdm_ecc_dbe_sts0_s { 5140 u64 flshb_cache_lo_ram_dbe : 1; 5141 u64 flshb_cache_hi_ram_dbe : 1; 5142 u64 isrm_ca_iinst_ram_dbe : 1; 5143 u64 isrm_ca_cm_ram_dbe : 1; 5144 u64 isrm_st_ram2_dbe : 1; 5145 u64 isrm_st_ram1_dbe : 1; 5146 u64 isrm_st_ram0_dbe : 1; 5147 u64 isrd_st_ram3_dbe : 1; 5148 u64 isrd_st_ram2_dbe : 1; 5149 u64 isrd_st_ram1_dbe : 1; 5150 u64 isrd_st_ram0_dbe : 1; 5151 u64 drp_hi_ram_dbe : 1; 5152 u64 drp_lo_ram_dbe : 1; 5153 u64 dwp_hi_ram_dbe : 1; 5154 u64 dwp_lo_ram_dbe : 1; 5155 u64 mwp_hi_ram_dbe : 1; 5156 u64 mwp_lo_ram_dbe : 1; 5157 u64 fillb_m_rsp_ram_hi_dbe : 1; 5158 u64 fillb_m_rsp_ram_lo_dbe : 1; 5159 u64 fillb_d_rsp_ram_hi_dbe : 1; 5160 u64 fillb_d_rsp_ram_lo_dbe : 1; 5161 u64 minpad_ram_dbe : 1; 5162 u64 mwp_hi_spt_ram_dbe : 1; 5163 u64 mwp_lo_spt_ram_dbe : 1; 5164 u64 buf_wm_ram_dbe : 1; 5165 u64 reserved_0_38 : 39; 5166 } s; 5167 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn73xx; 5168 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn78xx; 5169 struct cvmx_pko_pdm_ecc_dbe_sts0_s cn78xxp1; 5170 struct cvmx_pko_pdm_ecc_dbe_sts0_s cnf75xx; 5171 }; 5172 5173 typedef union cvmx_pko_pdm_ecc_dbe_sts0 cvmx_pko_pdm_ecc_dbe_sts0_t; 5174 5175 /** 5176 * cvmx_pko_pdm_ecc_dbe_sts_cmb0 5177 */ 5178 union cvmx_pko_pdm_ecc_dbe_sts_cmb0 { 5179 u64 u64; 5180 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s { 5181 u64 pdm_dbe_cmb0 : 1; 5182 u64 reserved_0_62 : 63; 5183 } s; 5184 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn73xx; 5185 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn78xx; 5186 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cn78xxp1; 5187 struct cvmx_pko_pdm_ecc_dbe_sts_cmb0_s cnf75xx; 5188 }; 5189 5190 typedef union cvmx_pko_pdm_ecc_dbe_sts_cmb0 cvmx_pko_pdm_ecc_dbe_sts_cmb0_t; 5191 5192 /** 5193 * cvmx_pko_pdm_ecc_sbe_sts0 5194 */ 5195 union cvmx_pko_pdm_ecc_sbe_sts0 { 5196 u64 u64; 5197 struct cvmx_pko_pdm_ecc_sbe_sts0_s { 5198 u64 flshb_cache_lo_ram_sbe : 1; 5199 u64 flshb_cache_hi_ram_sbe : 1; 5200 u64 isrm_ca_iinst_ram_sbe : 1; 5201 u64 isrm_ca_cm_ram_sbe : 1; 5202 u64 isrm_st_ram2_sbe : 1; 5203 u64 isrm_st_ram1_sbe : 1; 5204 u64 isrm_st_ram0_sbe : 1; 5205 u64 isrd_st_ram3_sbe : 1; 5206 u64 isrd_st_ram2_sbe : 1; 5207 u64 isrd_st_ram1_sbe : 1; 5208 u64 isrd_st_ram0_sbe : 1; 5209 u64 drp_hi_ram_sbe : 1; 5210 u64 drp_lo_ram_sbe : 1; 5211 u64 dwp_hi_ram_sbe : 1; 5212 u64 dwp_lo_ram_sbe : 1; 5213 u64 mwp_hi_ram_sbe : 1; 5214 u64 mwp_lo_ram_sbe : 1; 5215 u64 fillb_m_rsp_ram_hi_sbe : 1; 5216 u64 fillb_m_rsp_ram_lo_sbe : 1; 5217 u64 fillb_d_rsp_ram_hi_sbe : 1; 5218 u64 fillb_d_rsp_ram_lo_sbe : 1; 5219 u64 minpad_ram_sbe : 1; 5220 u64 mwp_hi_spt_ram_sbe : 1; 5221 u64 mwp_lo_spt_ram_sbe : 1; 5222 u64 buf_wm_ram_sbe : 1; 5223 u64 reserved_0_38 : 39; 5224 } s; 5225 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn73xx; 5226 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn78xx; 5227 struct cvmx_pko_pdm_ecc_sbe_sts0_s cn78xxp1; 5228 struct cvmx_pko_pdm_ecc_sbe_sts0_s cnf75xx; 5229 }; 5230 5231 typedef union cvmx_pko_pdm_ecc_sbe_sts0 cvmx_pko_pdm_ecc_sbe_sts0_t; 5232 5233 /** 5234 * cvmx_pko_pdm_ecc_sbe_sts_cmb0 5235 */ 5236 union cvmx_pko_pdm_ecc_sbe_sts_cmb0 { 5237 u64 u64; 5238 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s { 5239 u64 pdm_sbe_cmb0 : 1; 5240 u64 reserved_0_62 : 63; 5241 } s; 5242 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn73xx; 5243 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn78xx; 5244 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cn78xxp1; 5245 struct cvmx_pko_pdm_ecc_sbe_sts_cmb0_s cnf75xx; 5246 }; 5247 5248 typedef union cvmx_pko_pdm_ecc_sbe_sts_cmb0 cvmx_pko_pdm_ecc_sbe_sts_cmb0_t; 5249 5250 /** 5251 * cvmx_pko_pdm_fillb_dbg0 5252 */ 5253 union cvmx_pko_pdm_fillb_dbg0 { 5254 u64 u64; 5255 struct cvmx_pko_pdm_fillb_dbg0_s { 5256 u64 reserved_57_63 : 7; 5257 u64 pd_seq : 5; 5258 u64 resp_pd_seq : 5; 5259 u64 d_rsp_lo_ram_addr_sel : 2; 5260 u64 d_rsp_hi_ram_addr_sel : 2; 5261 u64 d_rsp_rd_seq : 5; 5262 u64 d_rsp_fifo_rd_seq : 5; 5263 u64 d_fill_req_fifo_val : 1; 5264 u64 d_rsp_ram_valid : 32; 5265 } s; 5266 struct cvmx_pko_pdm_fillb_dbg0_s cn73xx; 5267 struct cvmx_pko_pdm_fillb_dbg0_s cn78xx; 5268 struct cvmx_pko_pdm_fillb_dbg0_s cn78xxp1; 5269 struct cvmx_pko_pdm_fillb_dbg0_s cnf75xx; 5270 }; 5271 5272 typedef union cvmx_pko_pdm_fillb_dbg0 cvmx_pko_pdm_fillb_dbg0_t; 5273 5274 /** 5275 * cvmx_pko_pdm_fillb_dbg1 5276 */ 5277 union cvmx_pko_pdm_fillb_dbg1 { 5278 u64 u64; 5279 struct cvmx_pko_pdm_fillb_dbg1_s { 5280 u64 reserved_57_63 : 7; 5281 u64 mp_seq : 5; 5282 u64 resp_mp_seq : 5; 5283 u64 m_rsp_lo_ram_addr_sel : 2; 5284 u64 m_rsp_hi_ram_addr_sel : 2; 5285 u64 m_rsp_rd_seq : 5; 5286 u64 m_rsp_fifo_rd_seq : 5; 5287 u64 m_fill_req_fifo_val : 1; 5288 u64 m_rsp_ram_valid : 32; 5289 } s; 5290 struct cvmx_pko_pdm_fillb_dbg1_s cn73xx; 5291 struct cvmx_pko_pdm_fillb_dbg1_s cn78xx; 5292 struct cvmx_pko_pdm_fillb_dbg1_s cn78xxp1; 5293 struct cvmx_pko_pdm_fillb_dbg1_s cnf75xx; 5294 }; 5295 5296 typedef union cvmx_pko_pdm_fillb_dbg1 cvmx_pko_pdm_fillb_dbg1_t; 5297 5298 /** 5299 * cvmx_pko_pdm_fillb_dbg2 5300 */ 5301 union cvmx_pko_pdm_fillb_dbg2 { 5302 u64 u64; 5303 struct cvmx_pko_pdm_fillb_dbg2_s { 5304 u64 reserved_9_63 : 55; 5305 u64 fillb_sm : 5; 5306 u64 reserved_3_3 : 1; 5307 u64 iobp0_credit_cntr : 3; 5308 } s; 5309 struct cvmx_pko_pdm_fillb_dbg2_s cn73xx; 5310 struct cvmx_pko_pdm_fillb_dbg2_s cn78xx; 5311 struct cvmx_pko_pdm_fillb_dbg2_s cn78xxp1; 5312 struct cvmx_pko_pdm_fillb_dbg2_s cnf75xx; 5313 }; 5314 5315 typedef union cvmx_pko_pdm_fillb_dbg2 cvmx_pko_pdm_fillb_dbg2_t; 5316 5317 /** 5318 * cvmx_pko_pdm_flshb_dbg0 5319 */ 5320 union cvmx_pko_pdm_flshb_dbg0 { 5321 u64 u64; 5322 struct cvmx_pko_pdm_flshb_dbg0_s { 5323 u64 reserved_44_63 : 20; 5324 u64 flshb_sm : 7; 5325 u64 flshb_ctl_sm : 9; 5326 u64 cam_hptr : 5; 5327 u64 cam_tptr : 5; 5328 u64 expected_stdns : 6; 5329 u64 d_flshb_eot_cntr : 3; 5330 u64 m_flshb_eot_cntr : 3; 5331 u64 ncbi_credit_cntr : 6; 5332 } s; 5333 struct cvmx_pko_pdm_flshb_dbg0_s cn73xx; 5334 struct cvmx_pko_pdm_flshb_dbg0_s cn78xx; 5335 struct cvmx_pko_pdm_flshb_dbg0_s cn78xxp1; 5336 struct cvmx_pko_pdm_flshb_dbg0_s cnf75xx; 5337 }; 5338 5339 typedef union cvmx_pko_pdm_flshb_dbg0 cvmx_pko_pdm_flshb_dbg0_t; 5340 5341 /** 5342 * cvmx_pko_pdm_flshb_dbg1 5343 */ 5344 union cvmx_pko_pdm_flshb_dbg1 { 5345 u64 u64; 5346 struct cvmx_pko_pdm_flshb_dbg1_s { 5347 u64 cam_stdn : 32; 5348 u64 cam_valid : 32; 5349 } s; 5350 struct cvmx_pko_pdm_flshb_dbg1_s cn73xx; 5351 struct cvmx_pko_pdm_flshb_dbg1_s cn78xx; 5352 struct cvmx_pko_pdm_flshb_dbg1_s cn78xxp1; 5353 struct cvmx_pko_pdm_flshb_dbg1_s cnf75xx; 5354 }; 5355 5356 typedef union cvmx_pko_pdm_flshb_dbg1 cvmx_pko_pdm_flshb_dbg1_t; 5357 5358 /** 5359 * cvmx_pko_pdm_intf_dbg_rd 5360 * 5361 * For diagnostic use only. 5362 * 5363 */ 5364 union cvmx_pko_pdm_intf_dbg_rd { 5365 u64 u64; 5366 struct cvmx_pko_pdm_intf_dbg_rd_s { 5367 u64 reserved_48_63 : 16; 5368 u64 in_flight : 8; 5369 u64 pdm_req_cred_cnt : 8; 5370 u64 pse_buf_waddr : 8; 5371 u64 pse_buf_raddr : 8; 5372 u64 resp_buf_waddr : 8; 5373 u64 resp_buf_raddr : 8; 5374 } s; 5375 struct cvmx_pko_pdm_intf_dbg_rd_s cn73xx; 5376 struct cvmx_pko_pdm_intf_dbg_rd_s cn78xx; 5377 struct cvmx_pko_pdm_intf_dbg_rd_s cn78xxp1; 5378 struct cvmx_pko_pdm_intf_dbg_rd_s cnf75xx; 5379 }; 5380 5381 typedef union cvmx_pko_pdm_intf_dbg_rd cvmx_pko_pdm_intf_dbg_rd_t; 5382 5383 /** 5384 * cvmx_pko_pdm_isrd_dbg 5385 */ 5386 union cvmx_pko_pdm_isrd_dbg { 5387 u64 u64; 5388 struct cvmx_pko_pdm_isrd_dbg_s { 5389 u64 isrd_vals_in : 4; 5390 u64 reserved_59_59 : 1; 5391 u64 req_hptr : 6; 5392 u64 rdy_hptr : 6; 5393 u64 reserved_44_46 : 3; 5394 u64 in_arb_reqs : 8; 5395 u64 in_arb_gnts : 7; 5396 u64 cmt_arb_reqs : 7; 5397 u64 cmt_arb_gnts : 7; 5398 u64 in_use : 4; 5399 u64 has_cred : 4; 5400 u64 val_exec : 7; 5401 } s; 5402 struct cvmx_pko_pdm_isrd_dbg_s cn73xx; 5403 struct cvmx_pko_pdm_isrd_dbg_s cn78xx; 5404 struct cvmx_pko_pdm_isrd_dbg_cn78xxp1 { 5405 u64 reserved_44_63 : 20; 5406 u64 in_arb_reqs : 8; 5407 u64 in_arb_gnts : 7; 5408 u64 cmt_arb_reqs : 7; 5409 u64 cmt_arb_gnts : 7; 5410 u64 in_use : 4; 5411 u64 has_cred : 4; 5412 u64 val_exec : 7; 5413 } cn78xxp1; 5414 struct cvmx_pko_pdm_isrd_dbg_s cnf75xx; 5415 }; 5416 5417 typedef union cvmx_pko_pdm_isrd_dbg cvmx_pko_pdm_isrd_dbg_t; 5418 5419 /** 5420 * cvmx_pko_pdm_isrd_dbg_dq 5421 */ 5422 union cvmx_pko_pdm_isrd_dbg_dq { 5423 u64 u64; 5424 struct cvmx_pko_pdm_isrd_dbg_dq_s { 5425 u64 reserved_46_63 : 18; 5426 u64 pebrd_sic_dq : 10; 5427 u64 reserved_34_35 : 2; 5428 u64 pebfill_sic_dq : 10; 5429 u64 reserved_22_23 : 2; 5430 u64 fr_sic_dq : 10; 5431 u64 reserved_10_11 : 2; 5432 u64 cp_sic_dq : 10; 5433 } s; 5434 struct cvmx_pko_pdm_isrd_dbg_dq_s cn73xx; 5435 struct cvmx_pko_pdm_isrd_dbg_dq_s cn78xx; 5436 struct cvmx_pko_pdm_isrd_dbg_dq_s cn78xxp1; 5437 struct cvmx_pko_pdm_isrd_dbg_dq_s cnf75xx; 5438 }; 5439 5440 typedef union cvmx_pko_pdm_isrd_dbg_dq cvmx_pko_pdm_isrd_dbg_dq_t; 5441 5442 /** 5443 * cvmx_pko_pdm_isrm_dbg 5444 */ 5445 union cvmx_pko_pdm_isrm_dbg { 5446 u64 u64; 5447 struct cvmx_pko_pdm_isrm_dbg_s { 5448 u64 val_in : 3; 5449 u64 reserved_34_60 : 27; 5450 u64 in_arb_reqs : 7; 5451 u64 in_arb_gnts : 6; 5452 u64 cmt_arb_reqs : 6; 5453 u64 cmt_arb_gnts : 6; 5454 u64 in_use : 3; 5455 u64 has_cred : 3; 5456 u64 val_exec : 3; 5457 } s; 5458 struct cvmx_pko_pdm_isrm_dbg_s cn73xx; 5459 struct cvmx_pko_pdm_isrm_dbg_s cn78xx; 5460 struct cvmx_pko_pdm_isrm_dbg_cn78xxp1 { 5461 u64 reserved_34_63 : 30; 5462 u64 in_arb_reqs : 7; 5463 u64 in_arb_gnts : 6; 5464 u64 cmt_arb_reqs : 6; 5465 u64 cmt_arb_gnts : 6; 5466 u64 in_use : 3; 5467 u64 has_cred : 3; 5468 u64 val_exec : 3; 5469 } cn78xxp1; 5470 struct cvmx_pko_pdm_isrm_dbg_s cnf75xx; 5471 }; 5472 5473 typedef union cvmx_pko_pdm_isrm_dbg cvmx_pko_pdm_isrm_dbg_t; 5474 5475 /** 5476 * cvmx_pko_pdm_isrm_dbg_dq 5477 */ 5478 union cvmx_pko_pdm_isrm_dbg_dq { 5479 u64 u64; 5480 struct cvmx_pko_pdm_isrm_dbg_dq_s { 5481 u64 reserved_34_63 : 30; 5482 u64 ack_sic_dq : 10; 5483 u64 reserved_22_23 : 2; 5484 u64 fr_sic_dq : 10; 5485 u64 reserved_10_11 : 2; 5486 u64 cp_sic_dq : 10; 5487 } s; 5488 struct cvmx_pko_pdm_isrm_dbg_dq_s cn73xx; 5489 struct cvmx_pko_pdm_isrm_dbg_dq_s cn78xx; 5490 struct cvmx_pko_pdm_isrm_dbg_dq_s cn78xxp1; 5491 struct cvmx_pko_pdm_isrm_dbg_dq_s cnf75xx; 5492 }; 5493 5494 typedef union cvmx_pko_pdm_isrm_dbg_dq cvmx_pko_pdm_isrm_dbg_dq_t; 5495 5496 /** 5497 * cvmx_pko_pdm_mem_addr 5498 */ 5499 union cvmx_pko_pdm_mem_addr { 5500 u64 u64; 5501 struct cvmx_pko_pdm_mem_addr_s { 5502 u64 memsel : 3; 5503 u64 reserved_17_60 : 44; 5504 u64 memaddr : 14; 5505 u64 reserved_2_2 : 1; 5506 u64 membanksel : 2; 5507 } s; 5508 struct cvmx_pko_pdm_mem_addr_s cn73xx; 5509 struct cvmx_pko_pdm_mem_addr_s cn78xx; 5510 struct cvmx_pko_pdm_mem_addr_s cn78xxp1; 5511 struct cvmx_pko_pdm_mem_addr_s cnf75xx; 5512 }; 5513 5514 typedef union cvmx_pko_pdm_mem_addr cvmx_pko_pdm_mem_addr_t; 5515 5516 /** 5517 * cvmx_pko_pdm_mem_data 5518 */ 5519 union cvmx_pko_pdm_mem_data { 5520 u64 u64; 5521 struct cvmx_pko_pdm_mem_data_s { 5522 u64 data : 64; 5523 } s; 5524 struct cvmx_pko_pdm_mem_data_s cn73xx; 5525 struct cvmx_pko_pdm_mem_data_s cn78xx; 5526 struct cvmx_pko_pdm_mem_data_s cn78xxp1; 5527 struct cvmx_pko_pdm_mem_data_s cnf75xx; 5528 }; 5529 5530 typedef union cvmx_pko_pdm_mem_data cvmx_pko_pdm_mem_data_t; 5531 5532 /** 5533 * cvmx_pko_pdm_mem_rw_ctl 5534 */ 5535 union cvmx_pko_pdm_mem_rw_ctl { 5536 u64 u64; 5537 struct cvmx_pko_pdm_mem_rw_ctl_s { 5538 u64 reserved_2_63 : 62; 5539 u64 read : 1; 5540 u64 write : 1; 5541 } s; 5542 struct cvmx_pko_pdm_mem_rw_ctl_s cn73xx; 5543 struct cvmx_pko_pdm_mem_rw_ctl_s cn78xx; 5544 struct cvmx_pko_pdm_mem_rw_ctl_s cn78xxp1; 5545 struct cvmx_pko_pdm_mem_rw_ctl_s cnf75xx; 5546 }; 5547 5548 typedef union cvmx_pko_pdm_mem_rw_ctl cvmx_pko_pdm_mem_rw_ctl_t; 5549 5550 /** 5551 * cvmx_pko_pdm_mem_rw_sts 5552 */ 5553 union cvmx_pko_pdm_mem_rw_sts { 5554 u64 u64; 5555 struct cvmx_pko_pdm_mem_rw_sts_s { 5556 u64 reserved_1_63 : 63; 5557 u64 readdone : 1; 5558 } s; 5559 struct cvmx_pko_pdm_mem_rw_sts_s cn73xx; 5560 struct cvmx_pko_pdm_mem_rw_sts_s cn78xx; 5561 struct cvmx_pko_pdm_mem_rw_sts_s cn78xxp1; 5562 struct cvmx_pko_pdm_mem_rw_sts_s cnf75xx; 5563 }; 5564 5565 typedef union cvmx_pko_pdm_mem_rw_sts cvmx_pko_pdm_mem_rw_sts_t; 5566 5567 /** 5568 * cvmx_pko_pdm_mwpbuf_dbg 5569 */ 5570 union cvmx_pko_pdm_mwpbuf_dbg { 5571 u64 u64; 5572 struct cvmx_pko_pdm_mwpbuf_dbg_s { 5573 u64 reserved_49_63 : 15; 5574 u64 str_proc : 1; 5575 u64 cmd_proc : 1; 5576 u64 str_val : 1; 5577 u64 mem_data_val : 1; 5578 u64 insert_np : 1; 5579 u64 insert_mp : 1; 5580 u64 sel_nxt_ptr : 1; 5581 u64 load_val : 1; 5582 u64 rdy : 1; 5583 u64 cur_state : 3; 5584 u64 mem_rdy : 1; 5585 u64 str_rdy : 1; 5586 u64 contention_type : 2; 5587 u64 track_rd_cnt : 6; 5588 u64 track_wr_cnt : 6; 5589 u64 mem_wen : 4; 5590 u64 mem_addr : 13; 5591 u64 mem_en : 4; 5592 } s; 5593 struct cvmx_pko_pdm_mwpbuf_dbg_cn73xx { 5594 u64 reserved_49_63 : 15; 5595 u64 str_proc : 1; 5596 u64 cmd_proc : 1; 5597 u64 str_val : 1; 5598 u64 mem_data_val : 1; 5599 u64 insert_np : 1; 5600 u64 insert_mp : 1; 5601 u64 sel_nxt_ptr : 1; 5602 u64 load_val : 1; 5603 u64 rdy : 1; 5604 u64 cur_state : 3; 5605 u64 mem_rdy : 1; 5606 u64 str_rdy : 1; 5607 u64 contention_type : 2; 5608 u64 reserved_21_32 : 12; 5609 u64 mem_wen : 4; 5610 u64 reserved_15_16 : 2; 5611 u64 mem_addr : 11; 5612 u64 mem_en : 4; 5613 } cn73xx; 5614 struct cvmx_pko_pdm_mwpbuf_dbg_s cn78xx; 5615 struct cvmx_pko_pdm_mwpbuf_dbg_s cn78xxp1; 5616 struct cvmx_pko_pdm_mwpbuf_dbg_cn73xx cnf75xx; 5617 }; 5618 5619 typedef union cvmx_pko_pdm_mwpbuf_dbg cvmx_pko_pdm_mwpbuf_dbg_t; 5620 5621 /** 5622 * cvmx_pko_pdm_sts 5623 */ 5624 union cvmx_pko_pdm_sts { 5625 u64 u64; 5626 struct cvmx_pko_pdm_sts_s { 5627 u64 reserved_38_63 : 26; 5628 u64 cp_stalled_thrshld_hit : 1; 5629 u64 reserved_35_36 : 2; 5630 u64 mwpbuf_data_val_err : 1; 5631 u64 drpbuf_data_val_err : 1; 5632 u64 dwpbuf_data_val_err : 1; 5633 u64 reserved_30_31 : 2; 5634 u64 qcmd_iobx_err_sts : 4; 5635 u64 qcmd_iobx_err : 1; 5636 u64 sendpkt_lmtdma_err_sts : 4; 5637 u64 sendpkt_lmtdma_err : 1; 5638 u64 sendpkt_lmtst_err_sts : 4; 5639 u64 sendpkt_lmtst_err : 1; 5640 u64 fpa_no_ptrs : 1; 5641 u64 reserved_12_13 : 2; 5642 u64 cp_sendpkt_err_no_drp_code : 2; 5643 u64 cp_sendpkt_err_no_drp : 1; 5644 u64 reserved_7_8 : 2; 5645 u64 cp_sendpkt_err_drop_code : 3; 5646 u64 cp_sendpkt_err_drop : 1; 5647 u64 reserved_1_2 : 2; 5648 u64 desc_crc_err : 1; 5649 } s; 5650 struct cvmx_pko_pdm_sts_s cn73xx; 5651 struct cvmx_pko_pdm_sts_s cn78xx; 5652 struct cvmx_pko_pdm_sts_s cn78xxp1; 5653 struct cvmx_pko_pdm_sts_s cnf75xx; 5654 }; 5655 5656 typedef union cvmx_pko_pdm_sts cvmx_pko_pdm_sts_t; 5657 5658 /** 5659 * cvmx_pko_peb_bist_status 5660 * 5661 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 5662 * 5663 */ 5664 union cvmx_pko_peb_bist_status { 5665 u64 u64; 5666 struct cvmx_pko_peb_bist_status_s { 5667 u64 reserved_26_63 : 38; 5668 u64 add_work_fifo : 1; 5669 u64 pdm_pse_buf_ram : 1; 5670 u64 iobp0_fifo_ram : 1; 5671 u64 iobp1_fifo_ram : 1; 5672 u64 state_mem0 : 1; 5673 u64 reserved_19_20 : 2; 5674 u64 state_mem3 : 1; 5675 u64 iobp1_uid_fifo_ram : 1; 5676 u64 nxt_link_ptr_ram : 1; 5677 u64 pd_bank0_ram : 1; 5678 u64 pd_bank1_ram : 1; 5679 u64 pd_bank2_ram : 1; 5680 u64 pd_bank3_ram : 1; 5681 u64 pd_var_bank_ram : 1; 5682 u64 pdm_resp_buf_ram : 1; 5683 u64 tx_fifo_pkt_ram : 1; 5684 u64 tx_fifo_hdr_ram : 1; 5685 u64 tx_fifo_crc_ram : 1; 5686 u64 ts_addwork_ram : 1; 5687 u64 send_mem_ts_fifo : 1; 5688 u64 send_mem_stdn_fifo : 1; 5689 u64 send_mem_fifo : 1; 5690 u64 pkt_mrk_ram : 1; 5691 u64 peb_st_inf_ram : 1; 5692 u64 peb_sm_jmp_ram : 1; 5693 } s; 5694 struct cvmx_pko_peb_bist_status_cn73xx { 5695 u64 reserved_26_63 : 38; 5696 u64 add_work_fifo : 1; 5697 u64 pdm_pse_buf_ram : 1; 5698 u64 iobp0_fifo_ram : 1; 5699 u64 iobp1_fifo_ram : 1; 5700 u64 state_mem0 : 1; 5701 u64 reserved_19_20 : 2; 5702 u64 state_mem3 : 1; 5703 u64 iobp1_uid_fifo_ram : 1; 5704 u64 nxt_link_ptr_ram : 1; 5705 u64 pd_bank0_ram : 1; 5706 u64 reserved_13_14 : 2; 5707 u64 pd_bank3_ram : 1; 5708 u64 pd_var_bank_ram : 1; 5709 u64 pdm_resp_buf_ram : 1; 5710 u64 tx_fifo_pkt_ram : 1; 5711 u64 tx_fifo_hdr_ram : 1; 5712 u64 tx_fifo_crc_ram : 1; 5713 u64 ts_addwork_ram : 1; 5714 u64 send_mem_ts_fifo : 1; 5715 u64 send_mem_stdn_fifo : 1; 5716 u64 send_mem_fifo : 1; 5717 u64 pkt_mrk_ram : 1; 5718 u64 peb_st_inf_ram : 1; 5719 u64 reserved_0_0 : 1; 5720 } cn73xx; 5721 struct cvmx_pko_peb_bist_status_cn73xx cn78xx; 5722 struct cvmx_pko_peb_bist_status_s cn78xxp1; 5723 struct cvmx_pko_peb_bist_status_cn73xx cnf75xx; 5724 }; 5725 5726 typedef union cvmx_pko_peb_bist_status cvmx_pko_peb_bist_status_t; 5727 5728 /** 5729 * cvmx_pko_peb_ecc_ctl0 5730 */ 5731 union cvmx_pko_peb_ecc_ctl0 { 5732 u64 u64; 5733 struct cvmx_pko_peb_ecc_ctl0_s { 5734 u64 iobp1_uid_fifo_ram_flip : 2; 5735 u64 iobp1_uid_fifo_ram_cdis : 1; 5736 u64 iobp0_fifo_ram_flip : 2; 5737 u64 iobp0_fifo_ram_cdis : 1; 5738 u64 iobp1_fifo_ram_flip : 2; 5739 u64 iobp1_fifo_ram_cdis : 1; 5740 u64 pdm_resp_buf_ram_flip : 2; 5741 u64 pdm_resp_buf_ram_cdis : 1; 5742 u64 pdm_pse_buf_ram_flip : 2; 5743 u64 pdm_pse_buf_ram_cdis : 1; 5744 u64 peb_sm_jmp_ram_flip : 2; 5745 u64 peb_sm_jmp_ram_cdis : 1; 5746 u64 peb_st_inf_ram_flip : 2; 5747 u64 peb_st_inf_ram_cdis : 1; 5748 u64 pd_bank3_ram_flip : 2; 5749 u64 pd_bank3_ram_cdis : 1; 5750 u64 pd_bank2_ram_flip : 2; 5751 u64 pd_bank2_ram_cdis : 1; 5752 u64 pd_bank1_ram_flip : 2; 5753 u64 pd_bank1_ram_cdis : 1; 5754 u64 pd_bank0_ram_flip : 2; 5755 u64 pd_bank0_ram_cdis : 1; 5756 u64 pd_var_bank_ram_flip : 2; 5757 u64 pd_var_bank_ram_cdis : 1; 5758 u64 tx_fifo_crc_ram_flip : 2; 5759 u64 tx_fifo_crc_ram_cdis : 1; 5760 u64 tx_fifo_hdr_ram_flip : 2; 5761 u64 tx_fifo_hdr_ram_cdis : 1; 5762 u64 tx_fifo_pkt_ram_flip : 2; 5763 u64 tx_fifo_pkt_ram_cdis : 1; 5764 u64 add_work_fifo_flip : 2; 5765 u64 add_work_fifo_cdis : 1; 5766 u64 send_mem_fifo_flip : 2; 5767 u64 send_mem_fifo_cdis : 1; 5768 u64 send_mem_stdn_fifo_flip : 2; 5769 u64 send_mem_stdn_fifo_cdis : 1; 5770 u64 send_mem_ts_fifo_flip : 2; 5771 u64 send_mem_ts_fifo_cdis : 1; 5772 u64 nxt_link_ptr_ram_flip : 2; 5773 u64 nxt_link_ptr_ram_cdis : 1; 5774 u64 pkt_mrk_ram_flip : 2; 5775 u64 pkt_mrk_ram_cdis : 1; 5776 u64 reserved_0_0 : 1; 5777 } s; 5778 struct cvmx_pko_peb_ecc_ctl0_cn73xx { 5779 u64 iobp1_uid_fifo_ram_flip : 2; 5780 u64 iobp1_uid_fifo_ram_cdis : 1; 5781 u64 iobp0_fifo_ram_flip : 2; 5782 u64 iobp0_fifo_ram_cdis : 1; 5783 u64 iobp1_fifo_ram_flip : 2; 5784 u64 iobp1_fifo_ram_cdis : 1; 5785 u64 pdm_resp_buf_ram_flip : 2; 5786 u64 pdm_resp_buf_ram_cdis : 1; 5787 u64 pdm_pse_buf_ram_flip : 2; 5788 u64 pdm_pse_buf_ram_cdis : 1; 5789 u64 reserved_46_48 : 3; 5790 u64 peb_st_inf_ram_flip : 2; 5791 u64 peb_st_inf_ram_cdis : 1; 5792 u64 pd_bank3_ram_flip : 2; 5793 u64 pd_bank3_ram_cdis : 1; 5794 u64 reserved_34_39 : 6; 5795 u64 pd_bank0_ram_flip : 2; 5796 u64 pd_bank0_ram_cdis : 1; 5797 u64 pd_var_bank_ram_flip : 2; 5798 u64 pd_var_bank_ram_cdis : 1; 5799 u64 tx_fifo_crc_ram_flip : 2; 5800 u64 tx_fifo_crc_ram_cdis : 1; 5801 u64 tx_fifo_hdr_ram_flip : 2; 5802 u64 tx_fifo_hdr_ram_cdis : 1; 5803 u64 tx_fifo_pkt_ram_flip : 2; 5804 u64 tx_fifo_pkt_ram_cdis : 1; 5805 u64 add_work_fifo_flip : 2; 5806 u64 add_work_fifo_cdis : 1; 5807 u64 send_mem_fifo_flip : 2; 5808 u64 send_mem_fifo_cdis : 1; 5809 u64 send_mem_stdn_fifo_flip : 2; 5810 u64 send_mem_stdn_fifo_cdis : 1; 5811 u64 send_mem_ts_fifo_flip : 2; 5812 u64 send_mem_ts_fifo_cdis : 1; 5813 u64 nxt_link_ptr_ram_flip : 2; 5814 u64 nxt_link_ptr_ram_cdis : 1; 5815 u64 pkt_mrk_ram_flip : 2; 5816 u64 pkt_mrk_ram_cdis : 1; 5817 u64 reserved_0_0 : 1; 5818 } cn73xx; 5819 struct cvmx_pko_peb_ecc_ctl0_cn73xx cn78xx; 5820 struct cvmx_pko_peb_ecc_ctl0_s cn78xxp1; 5821 struct cvmx_pko_peb_ecc_ctl0_cn73xx cnf75xx; 5822 }; 5823 5824 typedef union cvmx_pko_peb_ecc_ctl0 cvmx_pko_peb_ecc_ctl0_t; 5825 5826 /** 5827 * cvmx_pko_peb_ecc_ctl1 5828 */ 5829 union cvmx_pko_peb_ecc_ctl1 { 5830 u64 u64; 5831 struct cvmx_pko_peb_ecc_ctl1_s { 5832 u64 ts_addwork_ram_flip : 2; 5833 u64 ts_addwork_ram_cdis : 1; 5834 u64 state_mem0_flip : 2; 5835 u64 state_mem0_cdis : 1; 5836 u64 reserved_52_57 : 6; 5837 u64 state_mem3_flip : 2; 5838 u64 state_mem3_cdis : 1; 5839 u64 reserved_0_48 : 49; 5840 } s; 5841 struct cvmx_pko_peb_ecc_ctl1_s cn73xx; 5842 struct cvmx_pko_peb_ecc_ctl1_cn78xx { 5843 u64 ts_addwork_ram_flip : 2; 5844 u64 ts_addwork_ram_cdis : 1; 5845 u64 reserved_0_60 : 61; 5846 } cn78xx; 5847 struct cvmx_pko_peb_ecc_ctl1_cn78xx cn78xxp1; 5848 struct cvmx_pko_peb_ecc_ctl1_s cnf75xx; 5849 }; 5850 5851 typedef union cvmx_pko_peb_ecc_ctl1 cvmx_pko_peb_ecc_ctl1_t; 5852 5853 /** 5854 * cvmx_pko_peb_ecc_dbe_sts0 5855 */ 5856 union cvmx_pko_peb_ecc_dbe_sts0 { 5857 u64 u64; 5858 struct cvmx_pko_peb_ecc_dbe_sts0_s { 5859 u64 iobp1_uid_fifo_ram_dbe : 1; 5860 u64 iobp0_fifo_ram_dbe : 1; 5861 u64 iobp1_fifo_ram_dbe : 1; 5862 u64 pdm_resp_buf_ram_dbe : 1; 5863 u64 pdm_pse_buf_ram_dbe : 1; 5864 u64 peb_sm_jmp_ram_dbe : 1; 5865 u64 peb_st_inf_ram_dbe : 1; 5866 u64 pd_bank3_ram_dbe : 1; 5867 u64 pd_bank2_ram_dbe : 1; 5868 u64 pd_bank1_ram_dbe : 1; 5869 u64 pd_bank0_ram_dbe : 1; 5870 u64 pd_var_bank_ram_dbe : 1; 5871 u64 tx_fifo_crc_ram_dbe : 1; 5872 u64 tx_fifo_hdr_ram_dbe : 1; 5873 u64 tx_fifo_pkt_ram_dbe : 1; 5874 u64 add_work_fifo_dbe : 1; 5875 u64 send_mem_fifo_dbe : 1; 5876 u64 send_mem_stdn_fifo_dbe : 1; 5877 u64 send_mem_ts_fifo_dbe : 1; 5878 u64 nxt_link_ptr_ram_dbe : 1; 5879 u64 pkt_mrk_ram_dbe : 1; 5880 u64 ts_addwork_ram_dbe : 1; 5881 u64 state_mem0_dbe : 1; 5882 u64 reserved_39_40 : 2; 5883 u64 state_mem3_dbe : 1; 5884 u64 reserved_0_37 : 38; 5885 } s; 5886 struct cvmx_pko_peb_ecc_dbe_sts0_cn73xx { 5887 u64 iobp1_uid_fifo_ram_dbe : 1; 5888 u64 iobp0_fifo_ram_dbe : 1; 5889 u64 iobp1_fifo_ram_dbe : 1; 5890 u64 pdm_resp_buf_ram_dbe : 1; 5891 u64 pdm_pse_buf_ram_dbe : 1; 5892 u64 reserved_58_58 : 1; 5893 u64 peb_st_inf_ram_dbe : 1; 5894 u64 pd_bank3_ram_dbe : 1; 5895 u64 reserved_54_55 : 2; 5896 u64 pd_bank0_ram_dbe : 1; 5897 u64 pd_var_bank_ram_dbe : 1; 5898 u64 tx_fifo_crc_ram_dbe : 1; 5899 u64 tx_fifo_hdr_ram_dbe : 1; 5900 u64 tx_fifo_pkt_ram_dbe : 1; 5901 u64 add_work_fifo_dbe : 1; 5902 u64 send_mem_fifo_dbe : 1; 5903 u64 send_mem_stdn_fifo_dbe : 1; 5904 u64 send_mem_ts_fifo_dbe : 1; 5905 u64 nxt_link_ptr_ram_dbe : 1; 5906 u64 pkt_mrk_ram_dbe : 1; 5907 u64 ts_addwork_ram_dbe : 1; 5908 u64 state_mem0_dbe : 1; 5909 u64 reserved_39_40 : 2; 5910 u64 state_mem3_dbe : 1; 5911 u64 reserved_0_37 : 38; 5912 } cn73xx; 5913 struct cvmx_pko_peb_ecc_dbe_sts0_cn78xx { 5914 u64 iobp1_uid_fifo_ram_dbe : 1; 5915 u64 iobp0_fifo_ram_dbe : 1; 5916 u64 iobp1_fifo_ram_dbe : 1; 5917 u64 pdm_resp_buf_ram_dbe : 1; 5918 u64 pdm_pse_buf_ram_dbe : 1; 5919 u64 reserved_58_58 : 1; 5920 u64 peb_st_inf_ram_dbe : 1; 5921 u64 pd_bank3_ram_dbe : 1; 5922 u64 reserved_54_55 : 2; 5923 u64 pd_bank0_ram_dbe : 1; 5924 u64 pd_var_bank_ram_dbe : 1; 5925 u64 tx_fifo_crc_ram_dbe : 1; 5926 u64 tx_fifo_hdr_ram_dbe : 1; 5927 u64 tx_fifo_pkt_ram_dbe : 1; 5928 u64 add_work_fifo_dbe : 1; 5929 u64 send_mem_fifo_dbe : 1; 5930 u64 send_mem_stdn_fifo_dbe : 1; 5931 u64 send_mem_ts_fifo_dbe : 1; 5932 u64 nxt_link_ptr_ram_dbe : 1; 5933 u64 pkt_mrk_ram_dbe : 1; 5934 u64 ts_addwork_ram_dbe : 1; 5935 u64 reserved_0_41 : 42; 5936 } cn78xx; 5937 struct cvmx_pko_peb_ecc_dbe_sts0_cn78xxp1 { 5938 u64 iobp1_uid_fifo_ram_dbe : 1; 5939 u64 iobp0_fifo_ram_dbe : 1; 5940 u64 iobp1_fifo_ram_dbe : 1; 5941 u64 pdm_resp_buf_ram_dbe : 1; 5942 u64 pdm_pse_buf_ram_dbe : 1; 5943 u64 peb_sm_jmp_ram_dbe : 1; 5944 u64 peb_st_inf_ram_dbe : 1; 5945 u64 pd_bank3_ram_dbe : 1; 5946 u64 pd_bank2_ram_dbe : 1; 5947 u64 pd_bank1_ram_dbe : 1; 5948 u64 pd_bank0_ram_dbe : 1; 5949 u64 pd_var_bank_ram_dbe : 1; 5950 u64 tx_fifo_crc_ram_dbe : 1; 5951 u64 tx_fifo_hdr_ram_dbe : 1; 5952 u64 tx_fifo_pkt_ram_dbe : 1; 5953 u64 add_work_fifo_dbe : 1; 5954 u64 send_mem_fifo_dbe : 1; 5955 u64 send_mem_stdn_fifo_dbe : 1; 5956 u64 send_mem_ts_fifo_dbe : 1; 5957 u64 nxt_link_ptr_ram_dbe : 1; 5958 u64 pkt_mrk_ram_dbe : 1; 5959 u64 ts_addwork_ram_dbe : 1; 5960 u64 reserved_0_41 : 42; 5961 } cn78xxp1; 5962 struct cvmx_pko_peb_ecc_dbe_sts0_cn73xx cnf75xx; 5963 }; 5964 5965 typedef union cvmx_pko_peb_ecc_dbe_sts0 cvmx_pko_peb_ecc_dbe_sts0_t; 5966 5967 /** 5968 * cvmx_pko_peb_ecc_dbe_sts_cmb0 5969 */ 5970 union cvmx_pko_peb_ecc_dbe_sts_cmb0 { 5971 u64 u64; 5972 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s { 5973 u64 peb_dbe_cmb0 : 1; 5974 u64 reserved_0_62 : 63; 5975 } s; 5976 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn73xx; 5977 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn78xx; 5978 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cn78xxp1; 5979 struct cvmx_pko_peb_ecc_dbe_sts_cmb0_s cnf75xx; 5980 }; 5981 5982 typedef union cvmx_pko_peb_ecc_dbe_sts_cmb0 cvmx_pko_peb_ecc_dbe_sts_cmb0_t; 5983 5984 /** 5985 * cvmx_pko_peb_ecc_sbe_sts0 5986 */ 5987 union cvmx_pko_peb_ecc_sbe_sts0 { 5988 u64 u64; 5989 struct cvmx_pko_peb_ecc_sbe_sts0_s { 5990 u64 iobp1_uid_fifo_ram_sbe : 1; 5991 u64 iobp0_fifo_ram_sbe : 1; 5992 u64 iobp1_fifo_ram_sbe : 1; 5993 u64 pdm_resp_buf_ram_sbe : 1; 5994 u64 pdm_pse_buf_ram_sbe : 1; 5995 u64 peb_sm_jmp_ram_sbe : 1; 5996 u64 peb_st_inf_ram_sbe : 1; 5997 u64 pd_bank3_ram_sbe : 1; 5998 u64 pd_bank2_ram_sbe : 1; 5999 u64 pd_bank1_ram_sbe : 1; 6000 u64 pd_bank0_ram_sbe : 1; 6001 u64 pd_var_bank_ram_sbe : 1; 6002 u64 tx_fifo_crc_ram_sbe : 1; 6003 u64 tx_fifo_hdr_ram_sbe : 1; 6004 u64 tx_fifo_pkt_ram_sbe : 1; 6005 u64 add_work_fifo_sbe : 1; 6006 u64 send_mem_fifo_sbe : 1; 6007 u64 send_mem_stdn_fifo_sbe : 1; 6008 u64 send_mem_ts_fifo_sbe : 1; 6009 u64 nxt_link_ptr_ram_sbe : 1; 6010 u64 pkt_mrk_ram_sbe : 1; 6011 u64 ts_addwork_ram_sbe : 1; 6012 u64 state_mem0_sbe : 1; 6013 u64 reserved_39_40 : 2; 6014 u64 state_mem3_sbe : 1; 6015 u64 reserved_0_37 : 38; 6016 } s; 6017 struct cvmx_pko_peb_ecc_sbe_sts0_cn73xx { 6018 u64 iobp1_uid_fifo_ram_sbe : 1; 6019 u64 iobp0_fifo_ram_sbe : 1; 6020 u64 iobp1_fifo_ram_sbe : 1; 6021 u64 pdm_resp_buf_ram_sbe : 1; 6022 u64 pdm_pse_buf_ram_sbe : 1; 6023 u64 reserved_58_58 : 1; 6024 u64 peb_st_inf_ram_sbe : 1; 6025 u64 pd_bank3_ram_sbe : 1; 6026 u64 reserved_54_55 : 2; 6027 u64 pd_bank0_ram_sbe : 1; 6028 u64 pd_var_bank_ram_sbe : 1; 6029 u64 tx_fifo_crc_ram_sbe : 1; 6030 u64 tx_fifo_hdr_ram_sbe : 1; 6031 u64 tx_fifo_pkt_ram_sbe : 1; 6032 u64 add_work_fifo_sbe : 1; 6033 u64 send_mem_fifo_sbe : 1; 6034 u64 send_mem_stdn_fifo_sbe : 1; 6035 u64 send_mem_ts_fifo_sbe : 1; 6036 u64 nxt_link_ptr_ram_sbe : 1; 6037 u64 pkt_mrk_ram_sbe : 1; 6038 u64 ts_addwork_ram_sbe : 1; 6039 u64 state_mem0_sbe : 1; 6040 u64 reserved_39_40 : 2; 6041 u64 state_mem3_sbe : 1; 6042 u64 reserved_0_37 : 38; 6043 } cn73xx; 6044 struct cvmx_pko_peb_ecc_sbe_sts0_cn78xx { 6045 u64 iobp1_uid_fifo_ram_sbe : 1; 6046 u64 iobp0_fifo_ram_sbe : 1; 6047 u64 iobp1_fifo_ram_sbe : 1; 6048 u64 pdm_resp_buf_ram_sbe : 1; 6049 u64 pdm_pse_buf_ram_sbe : 1; 6050 u64 reserved_58_58 : 1; 6051 u64 peb_st_inf_ram_sbe : 1; 6052 u64 pd_bank3_ram_sbe : 1; 6053 u64 reserved_54_55 : 2; 6054 u64 pd_bank0_ram_sbe : 1; 6055 u64 pd_var_bank_ram_sbe : 1; 6056 u64 tx_fifo_crc_ram_sbe : 1; 6057 u64 tx_fifo_hdr_ram_sbe : 1; 6058 u64 tx_fifo_pkt_ram_sbe : 1; 6059 u64 add_work_fifo_sbe : 1; 6060 u64 send_mem_fifo_sbe : 1; 6061 u64 send_mem_stdn_fifo_sbe : 1; 6062 u64 send_mem_ts_fifo_sbe : 1; 6063 u64 nxt_link_ptr_ram_sbe : 1; 6064 u64 pkt_mrk_ram_sbe : 1; 6065 u64 ts_addwork_ram_sbe : 1; 6066 u64 reserved_0_41 : 42; 6067 } cn78xx; 6068 struct cvmx_pko_peb_ecc_sbe_sts0_cn78xxp1 { 6069 u64 iobp1_uid_fifo_ram_sbe : 1; 6070 u64 iobp0_fifo_ram_sbe : 1; 6071 u64 iobp1_fifo_ram_sbe : 1; 6072 u64 pdm_resp_buf_ram_sbe : 1; 6073 u64 pdm_pse_buf_ram_sbe : 1; 6074 u64 peb_sm_jmp_ram_sbe : 1; 6075 u64 peb_st_inf_ram_sbe : 1; 6076 u64 pd_bank3_ram_sbe : 1; 6077 u64 pd_bank2_ram_sbe : 1; 6078 u64 pd_bank1_ram_sbe : 1; 6079 u64 pd_bank0_ram_sbe : 1; 6080 u64 pd_var_bank_ram_sbe : 1; 6081 u64 tx_fifo_crc_ram_sbe : 1; 6082 u64 tx_fifo_hdr_ram_sbe : 1; 6083 u64 tx_fifo_pkt_ram_sbe : 1; 6084 u64 add_work_fifo_sbe : 1; 6085 u64 send_mem_fifo_sbe : 1; 6086 u64 send_mem_stdn_fifo_sbe : 1; 6087 u64 send_mem_ts_fifo_sbe : 1; 6088 u64 nxt_link_ptr_ram_sbe : 1; 6089 u64 pkt_mrk_ram_sbe : 1; 6090 u64 ts_addwork_ram_sbe : 1; 6091 u64 reserved_0_41 : 42; 6092 } cn78xxp1; 6093 struct cvmx_pko_peb_ecc_sbe_sts0_cn73xx cnf75xx; 6094 }; 6095 6096 typedef union cvmx_pko_peb_ecc_sbe_sts0 cvmx_pko_peb_ecc_sbe_sts0_t; 6097 6098 /** 6099 * cvmx_pko_peb_ecc_sbe_sts_cmb0 6100 */ 6101 union cvmx_pko_peb_ecc_sbe_sts_cmb0 { 6102 u64 u64; 6103 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s { 6104 u64 peb_sbe_cmb0 : 1; 6105 u64 reserved_0_62 : 63; 6106 } s; 6107 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn73xx; 6108 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn78xx; 6109 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cn78xxp1; 6110 struct cvmx_pko_peb_ecc_sbe_sts_cmb0_s cnf75xx; 6111 }; 6112 6113 typedef union cvmx_pko_peb_ecc_sbe_sts_cmb0 cvmx_pko_peb_ecc_sbe_sts_cmb0_t; 6114 6115 /** 6116 * cvmx_pko_peb_eco 6117 */ 6118 union cvmx_pko_peb_eco { 6119 u64 u64; 6120 struct cvmx_pko_peb_eco_s { 6121 u64 reserved_32_63 : 32; 6122 u64 eco_rw : 32; 6123 } s; 6124 struct cvmx_pko_peb_eco_s cn73xx; 6125 struct cvmx_pko_peb_eco_s cn78xx; 6126 struct cvmx_pko_peb_eco_s cnf75xx; 6127 }; 6128 6129 typedef union cvmx_pko_peb_eco cvmx_pko_peb_eco_t; 6130 6131 /** 6132 * cvmx_pko_peb_err_int 6133 */ 6134 union cvmx_pko_peb_err_int { 6135 u64 u64; 6136 struct cvmx_pko_peb_err_int_s { 6137 u64 reserved_10_63 : 54; 6138 u64 peb_macx_cfg_wr_err : 1; 6139 u64 peb_max_link_err : 1; 6140 u64 peb_subd_size_err : 1; 6141 u64 peb_subd_addr_err : 1; 6142 u64 peb_trunc_err : 1; 6143 u64 peb_pad_err : 1; 6144 u64 peb_pse_fifo_err : 1; 6145 u64 peb_fcs_sop_err : 1; 6146 u64 peb_jump_def_err : 1; 6147 u64 peb_ext_hdr_def_err : 1; 6148 } s; 6149 struct cvmx_pko_peb_err_int_s cn73xx; 6150 struct cvmx_pko_peb_err_int_s cn78xx; 6151 struct cvmx_pko_peb_err_int_s cn78xxp1; 6152 struct cvmx_pko_peb_err_int_s cnf75xx; 6153 }; 6154 6155 typedef union cvmx_pko_peb_err_int cvmx_pko_peb_err_int_t; 6156 6157 /** 6158 * cvmx_pko_peb_ext_hdr_def_err_info 6159 */ 6160 union cvmx_pko_peb_ext_hdr_def_err_info { 6161 u64 u64; 6162 struct cvmx_pko_peb_ext_hdr_def_err_info_s { 6163 u64 reserved_20_63 : 44; 6164 u64 val : 1; 6165 u64 fifo : 7; 6166 u64 chan : 12; 6167 } s; 6168 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn73xx; 6169 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn78xx; 6170 struct cvmx_pko_peb_ext_hdr_def_err_info_s cn78xxp1; 6171 struct cvmx_pko_peb_ext_hdr_def_err_info_s cnf75xx; 6172 }; 6173 6174 typedef union cvmx_pko_peb_ext_hdr_def_err_info cvmx_pko_peb_ext_hdr_def_err_info_t; 6175 6176 /** 6177 * cvmx_pko_peb_fcs_sop_err_info 6178 */ 6179 union cvmx_pko_peb_fcs_sop_err_info { 6180 u64 u64; 6181 struct cvmx_pko_peb_fcs_sop_err_info_s { 6182 u64 reserved_20_63 : 44; 6183 u64 val : 1; 6184 u64 fifo : 7; 6185 u64 chan : 12; 6186 } s; 6187 struct cvmx_pko_peb_fcs_sop_err_info_s cn73xx; 6188 struct cvmx_pko_peb_fcs_sop_err_info_s cn78xx; 6189 struct cvmx_pko_peb_fcs_sop_err_info_s cn78xxp1; 6190 struct cvmx_pko_peb_fcs_sop_err_info_s cnf75xx; 6191 }; 6192 6193 typedef union cvmx_pko_peb_fcs_sop_err_info cvmx_pko_peb_fcs_sop_err_info_t; 6194 6195 /** 6196 * cvmx_pko_peb_jump_def_err_info 6197 */ 6198 union cvmx_pko_peb_jump_def_err_info { 6199 u64 u64; 6200 struct cvmx_pko_peb_jump_def_err_info_s { 6201 u64 reserved_20_63 : 44; 6202 u64 val : 1; 6203 u64 fifo : 7; 6204 u64 chan : 12; 6205 } s; 6206 struct cvmx_pko_peb_jump_def_err_info_s cn73xx; 6207 struct cvmx_pko_peb_jump_def_err_info_s cn78xx; 6208 struct cvmx_pko_peb_jump_def_err_info_s cn78xxp1; 6209 struct cvmx_pko_peb_jump_def_err_info_s cnf75xx; 6210 }; 6211 6212 typedef union cvmx_pko_peb_jump_def_err_info cvmx_pko_peb_jump_def_err_info_t; 6213 6214 /** 6215 * cvmx_pko_peb_macx_cfg_wr_err_info 6216 */ 6217 union cvmx_pko_peb_macx_cfg_wr_err_info { 6218 u64 u64; 6219 struct cvmx_pko_peb_macx_cfg_wr_err_info_s { 6220 u64 reserved_8_63 : 56; 6221 u64 val : 1; 6222 u64 mac : 7; 6223 } s; 6224 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn73xx; 6225 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn78xx; 6226 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cn78xxp1; 6227 struct cvmx_pko_peb_macx_cfg_wr_err_info_s cnf75xx; 6228 }; 6229 6230 typedef union cvmx_pko_peb_macx_cfg_wr_err_info cvmx_pko_peb_macx_cfg_wr_err_info_t; 6231 6232 /** 6233 * cvmx_pko_peb_max_link_err_info 6234 */ 6235 union cvmx_pko_peb_max_link_err_info { 6236 u64 u64; 6237 struct cvmx_pko_peb_max_link_err_info_s { 6238 u64 reserved_20_63 : 44; 6239 u64 val : 1; 6240 u64 fifo : 7; 6241 u64 chan : 12; 6242 } s; 6243 struct cvmx_pko_peb_max_link_err_info_s cn73xx; 6244 struct cvmx_pko_peb_max_link_err_info_s cn78xx; 6245 struct cvmx_pko_peb_max_link_err_info_s cn78xxp1; 6246 struct cvmx_pko_peb_max_link_err_info_s cnf75xx; 6247 }; 6248 6249 typedef union cvmx_pko_peb_max_link_err_info cvmx_pko_peb_max_link_err_info_t; 6250 6251 /** 6252 * cvmx_pko_peb_ncb_cfg 6253 */ 6254 union cvmx_pko_peb_ncb_cfg { 6255 u64 u64; 6256 struct cvmx_pko_peb_ncb_cfg_s { 6257 u64 reserved_1_63 : 63; 6258 u64 rstp : 1; 6259 } s; 6260 struct cvmx_pko_peb_ncb_cfg_s cn73xx; 6261 struct cvmx_pko_peb_ncb_cfg_s cn78xx; 6262 struct cvmx_pko_peb_ncb_cfg_s cn78xxp1; 6263 struct cvmx_pko_peb_ncb_cfg_s cnf75xx; 6264 }; 6265 6266 typedef union cvmx_pko_peb_ncb_cfg cvmx_pko_peb_ncb_cfg_t; 6267 6268 /** 6269 * cvmx_pko_peb_pad_err_info 6270 */ 6271 union cvmx_pko_peb_pad_err_info { 6272 u64 u64; 6273 struct cvmx_pko_peb_pad_err_info_s { 6274 u64 reserved_20_63 : 44; 6275 u64 val : 1; 6276 u64 fifo : 7; 6277 u64 chan : 12; 6278 } s; 6279 struct cvmx_pko_peb_pad_err_info_s cn73xx; 6280 struct cvmx_pko_peb_pad_err_info_s cn78xx; 6281 struct cvmx_pko_peb_pad_err_info_s cn78xxp1; 6282 struct cvmx_pko_peb_pad_err_info_s cnf75xx; 6283 }; 6284 6285 typedef union cvmx_pko_peb_pad_err_info cvmx_pko_peb_pad_err_info_t; 6286 6287 /** 6288 * cvmx_pko_peb_pse_fifo_err_info 6289 */ 6290 union cvmx_pko_peb_pse_fifo_err_info { 6291 u64 u64; 6292 struct cvmx_pko_peb_pse_fifo_err_info_s { 6293 u64 reserved_25_63 : 39; 6294 u64 link : 5; 6295 u64 val : 1; 6296 u64 fifo : 7; 6297 u64 chan : 12; 6298 } s; 6299 struct cvmx_pko_peb_pse_fifo_err_info_cn73xx { 6300 u64 reserved_20_63 : 44; 6301 u64 val : 1; 6302 u64 fifo : 7; 6303 u64 chan : 12; 6304 } cn73xx; 6305 struct cvmx_pko_peb_pse_fifo_err_info_s cn78xx; 6306 struct cvmx_pko_peb_pse_fifo_err_info_cn73xx cn78xxp1; 6307 struct cvmx_pko_peb_pse_fifo_err_info_s cnf75xx; 6308 }; 6309 6310 typedef union cvmx_pko_peb_pse_fifo_err_info cvmx_pko_peb_pse_fifo_err_info_t; 6311 6312 /** 6313 * cvmx_pko_peb_subd_addr_err_info 6314 */ 6315 union cvmx_pko_peb_subd_addr_err_info { 6316 u64 u64; 6317 struct cvmx_pko_peb_subd_addr_err_info_s { 6318 u64 reserved_20_63 : 44; 6319 u64 val : 1; 6320 u64 fifo : 7; 6321 u64 chan : 12; 6322 } s; 6323 struct cvmx_pko_peb_subd_addr_err_info_s cn73xx; 6324 struct cvmx_pko_peb_subd_addr_err_info_s cn78xx; 6325 struct cvmx_pko_peb_subd_addr_err_info_s cn78xxp1; 6326 struct cvmx_pko_peb_subd_addr_err_info_s cnf75xx; 6327 }; 6328 6329 typedef union cvmx_pko_peb_subd_addr_err_info cvmx_pko_peb_subd_addr_err_info_t; 6330 6331 /** 6332 * cvmx_pko_peb_subd_size_err_info 6333 */ 6334 union cvmx_pko_peb_subd_size_err_info { 6335 u64 u64; 6336 struct cvmx_pko_peb_subd_size_err_info_s { 6337 u64 reserved_20_63 : 44; 6338 u64 val : 1; 6339 u64 fifo : 7; 6340 u64 chan : 12; 6341 } s; 6342 struct cvmx_pko_peb_subd_size_err_info_s cn73xx; 6343 struct cvmx_pko_peb_subd_size_err_info_s cn78xx; 6344 struct cvmx_pko_peb_subd_size_err_info_s cn78xxp1; 6345 struct cvmx_pko_peb_subd_size_err_info_s cnf75xx; 6346 }; 6347 6348 typedef union cvmx_pko_peb_subd_size_err_info cvmx_pko_peb_subd_size_err_info_t; 6349 6350 /** 6351 * cvmx_pko_peb_trunc_err_info 6352 */ 6353 union cvmx_pko_peb_trunc_err_info { 6354 u64 u64; 6355 struct cvmx_pko_peb_trunc_err_info_s { 6356 u64 reserved_20_63 : 44; 6357 u64 val : 1; 6358 u64 fifo : 7; 6359 u64 chan : 12; 6360 } s; 6361 struct cvmx_pko_peb_trunc_err_info_s cn73xx; 6362 struct cvmx_pko_peb_trunc_err_info_s cn78xx; 6363 struct cvmx_pko_peb_trunc_err_info_s cn78xxp1; 6364 struct cvmx_pko_peb_trunc_err_info_s cnf75xx; 6365 }; 6366 6367 typedef union cvmx_pko_peb_trunc_err_info cvmx_pko_peb_trunc_err_info_t; 6368 6369 /** 6370 * cvmx_pko_peb_tso_cfg 6371 */ 6372 union cvmx_pko_peb_tso_cfg { 6373 u64 u64; 6374 struct cvmx_pko_peb_tso_cfg_s { 6375 u64 reserved_44_63 : 20; 6376 u64 fsf : 12; 6377 u64 reserved_28_31 : 4; 6378 u64 msf : 12; 6379 u64 reserved_12_15 : 4; 6380 u64 lsf : 12; 6381 } s; 6382 struct cvmx_pko_peb_tso_cfg_s cn73xx; 6383 struct cvmx_pko_peb_tso_cfg_s cn78xx; 6384 struct cvmx_pko_peb_tso_cfg_s cn78xxp1; 6385 struct cvmx_pko_peb_tso_cfg_s cnf75xx; 6386 }; 6387 6388 typedef union cvmx_pko_peb_tso_cfg cvmx_pko_peb_tso_cfg_t; 6389 6390 /** 6391 * cvmx_pko_pq_csr_bus_debug 6392 */ 6393 union cvmx_pko_pq_csr_bus_debug { 6394 u64 u64; 6395 struct cvmx_pko_pq_csr_bus_debug_s { 6396 u64 csr_bus_debug : 64; 6397 } s; 6398 struct cvmx_pko_pq_csr_bus_debug_s cn73xx; 6399 struct cvmx_pko_pq_csr_bus_debug_s cn78xx; 6400 struct cvmx_pko_pq_csr_bus_debug_s cn78xxp1; 6401 struct cvmx_pko_pq_csr_bus_debug_s cnf75xx; 6402 }; 6403 6404 typedef union cvmx_pko_pq_csr_bus_debug cvmx_pko_pq_csr_bus_debug_t; 6405 6406 /** 6407 * cvmx_pko_pq_debug_green 6408 */ 6409 union cvmx_pko_pq_debug_green { 6410 u64 u64; 6411 struct cvmx_pko_pq_debug_green_s { 6412 u64 g_valid : 32; 6413 u64 cred_ok_n : 32; 6414 } s; 6415 struct cvmx_pko_pq_debug_green_s cn73xx; 6416 struct cvmx_pko_pq_debug_green_s cn78xx; 6417 struct cvmx_pko_pq_debug_green_s cn78xxp1; 6418 struct cvmx_pko_pq_debug_green_s cnf75xx; 6419 }; 6420 6421 typedef union cvmx_pko_pq_debug_green cvmx_pko_pq_debug_green_t; 6422 6423 /** 6424 * cvmx_pko_pq_debug_links 6425 */ 6426 union cvmx_pko_pq_debug_links { 6427 u64 u64; 6428 struct cvmx_pko_pq_debug_links_s { 6429 u64 links_ready : 32; 6430 u64 peb_lnk_rdy_ir : 32; 6431 } s; 6432 struct cvmx_pko_pq_debug_links_s cn73xx; 6433 struct cvmx_pko_pq_debug_links_s cn78xx; 6434 struct cvmx_pko_pq_debug_links_s cn78xxp1; 6435 struct cvmx_pko_pq_debug_links_s cnf75xx; 6436 }; 6437 6438 typedef union cvmx_pko_pq_debug_links cvmx_pko_pq_debug_links_t; 6439 6440 /** 6441 * cvmx_pko_pq_debug_yellow 6442 */ 6443 union cvmx_pko_pq_debug_yellow { 6444 u64 u64; 6445 struct cvmx_pko_pq_debug_yellow_s { 6446 u64 y_valid : 32; 6447 u64 reserved_28_31 : 4; 6448 u64 link_vv : 28; 6449 } s; 6450 struct cvmx_pko_pq_debug_yellow_s cn73xx; 6451 struct cvmx_pko_pq_debug_yellow_s cn78xx; 6452 struct cvmx_pko_pq_debug_yellow_s cn78xxp1; 6453 struct cvmx_pko_pq_debug_yellow_s cnf75xx; 6454 }; 6455 6456 typedef union cvmx_pko_pq_debug_yellow cvmx_pko_pq_debug_yellow_t; 6457 6458 /** 6459 * cvmx_pko_pqa_debug 6460 */ 6461 union cvmx_pko_pqa_debug { 6462 u64 u64; 6463 struct cvmx_pko_pqa_debug_s { 6464 u64 dbg_vec : 64; 6465 } s; 6466 struct cvmx_pko_pqa_debug_s cn73xx; 6467 struct cvmx_pko_pqa_debug_s cn78xx; 6468 struct cvmx_pko_pqa_debug_s cn78xxp1; 6469 struct cvmx_pko_pqa_debug_s cnf75xx; 6470 }; 6471 6472 typedef union cvmx_pko_pqa_debug cvmx_pko_pqa_debug_t; 6473 6474 /** 6475 * cvmx_pko_pqb_debug 6476 * 6477 * This register has the same bit fields as PKO_PQA_DEBUG. 6478 * 6479 */ 6480 union cvmx_pko_pqb_debug { 6481 u64 u64; 6482 struct cvmx_pko_pqb_debug_s { 6483 u64 dbg_vec : 64; 6484 } s; 6485 struct cvmx_pko_pqb_debug_s cn73xx; 6486 struct cvmx_pko_pqb_debug_s cn78xx; 6487 struct cvmx_pko_pqb_debug_s cn78xxp1; 6488 struct cvmx_pko_pqb_debug_s cnf75xx; 6489 }; 6490 6491 typedef union cvmx_pko_pqb_debug cvmx_pko_pqb_debug_t; 6492 6493 /** 6494 * cvmx_pko_pse_dq_bist_status 6495 * 6496 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 6497 * 6498 */ 6499 union cvmx_pko_pse_dq_bist_status { 6500 u64 u64; 6501 struct cvmx_pko_pse_dq_bist_status_s { 6502 u64 reserved_8_63 : 56; 6503 u64 rt7_sram : 1; 6504 u64 rt6_sram : 1; 6505 u64 rt5_sram : 1; 6506 u64 reserved_4_4 : 1; 6507 u64 rt3_sram : 1; 6508 u64 rt2_sram : 1; 6509 u64 rt1_sram : 1; 6510 u64 rt0_sram : 1; 6511 } s; 6512 struct cvmx_pko_pse_dq_bist_status_cn73xx { 6513 u64 reserved_5_63 : 59; 6514 u64 wt_sram : 1; 6515 u64 reserved_2_3 : 2; 6516 u64 rt1_sram : 1; 6517 u64 rt0_sram : 1; 6518 } cn73xx; 6519 struct cvmx_pko_pse_dq_bist_status_cn78xx { 6520 u64 reserved_9_63 : 55; 6521 u64 wt_sram : 1; 6522 u64 rt7_sram : 1; 6523 u64 rt6_sram : 1; 6524 u64 rt5_sram : 1; 6525 u64 rt4_sram : 1; 6526 u64 rt3_sram : 1; 6527 u64 rt2_sram : 1; 6528 u64 rt1_sram : 1; 6529 u64 rt0_sram : 1; 6530 } cn78xx; 6531 struct cvmx_pko_pse_dq_bist_status_cn78xx cn78xxp1; 6532 struct cvmx_pko_pse_dq_bist_status_cn73xx cnf75xx; 6533 }; 6534 6535 typedef union cvmx_pko_pse_dq_bist_status cvmx_pko_pse_dq_bist_status_t; 6536 6537 /** 6538 * cvmx_pko_pse_dq_ecc_ctl0 6539 */ 6540 union cvmx_pko_pse_dq_ecc_ctl0 { 6541 u64 u64; 6542 struct cvmx_pko_pse_dq_ecc_ctl0_s { 6543 u64 dq_wt_ram_flip : 2; 6544 u64 dq_wt_ram_cdis : 1; 6545 u64 dq_rt7_flip : 2; 6546 u64 dq_rt7_cdis : 1; 6547 u64 dq_rt6_flip : 2; 6548 u64 dq_rt6_cdis : 1; 6549 u64 dq_rt5_flip : 2; 6550 u64 dq_rt5_cdis : 1; 6551 u64 dq_rt4_flip : 2; 6552 u64 dq_rt4_cdis : 1; 6553 u64 dq_rt3_flip : 2; 6554 u64 dq_rt3_cdis : 1; 6555 u64 dq_rt2_flip : 2; 6556 u64 dq_rt2_cdis : 1; 6557 u64 dq_rt1_flip : 2; 6558 u64 dq_rt1_cdis : 1; 6559 u64 dq_rt0_flip : 2; 6560 u64 dq_rt0_cdis : 1; 6561 u64 reserved_0_36 : 37; 6562 } s; 6563 struct cvmx_pko_pse_dq_ecc_ctl0_cn73xx { 6564 u64 dq_wt_ram_flip : 2; 6565 u64 dq_wt_ram_cdis : 1; 6566 u64 reserved_43_60 : 18; 6567 u64 dq_rt1_flip : 2; 6568 u64 dq_rt1_cdis : 1; 6569 u64 dq_rt0_flip : 2; 6570 u64 dq_rt0_cdis : 1; 6571 u64 reserved_0_36 : 37; 6572 } cn73xx; 6573 struct cvmx_pko_pse_dq_ecc_ctl0_s cn78xx; 6574 struct cvmx_pko_pse_dq_ecc_ctl0_s cn78xxp1; 6575 struct cvmx_pko_pse_dq_ecc_ctl0_cn73xx cnf75xx; 6576 }; 6577 6578 typedef union cvmx_pko_pse_dq_ecc_ctl0 cvmx_pko_pse_dq_ecc_ctl0_t; 6579 6580 /** 6581 * cvmx_pko_pse_dq_ecc_dbe_sts0 6582 */ 6583 union cvmx_pko_pse_dq_ecc_dbe_sts0 { 6584 u64 u64; 6585 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s { 6586 u64 dq_wt_ram_dbe : 1; 6587 u64 dq_rt7_dbe : 1; 6588 u64 dq_rt6_dbe : 1; 6589 u64 dq_rt5_dbe : 1; 6590 u64 dq_rt4_dbe : 1; 6591 u64 dq_rt3_dbe : 1; 6592 u64 dq_rt2_dbe : 1; 6593 u64 dq_rt1_dbe : 1; 6594 u64 dq_rt0_dbe : 1; 6595 u64 reserved_0_54 : 55; 6596 } s; 6597 struct cvmx_pko_pse_dq_ecc_dbe_sts0_cn73xx { 6598 u64 dq_wt_ram_dbe : 1; 6599 u64 reserved_57_62 : 6; 6600 u64 dq_rt1_dbe : 1; 6601 u64 dq_rt0_dbe : 1; 6602 u64 reserved_0_54 : 55; 6603 } cn73xx; 6604 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s cn78xx; 6605 struct cvmx_pko_pse_dq_ecc_dbe_sts0_s cn78xxp1; 6606 struct cvmx_pko_pse_dq_ecc_dbe_sts0_cn73xx cnf75xx; 6607 }; 6608 6609 typedef union cvmx_pko_pse_dq_ecc_dbe_sts0 cvmx_pko_pse_dq_ecc_dbe_sts0_t; 6610 6611 /** 6612 * cvmx_pko_pse_dq_ecc_dbe_sts_cmb0 6613 */ 6614 union cvmx_pko_pse_dq_ecc_dbe_sts_cmb0 { 6615 u64 u64; 6616 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s { 6617 u64 pse_dq_dbe_cmb0 : 1; 6618 u64 reserved_0_62 : 63; 6619 } s; 6620 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn73xx; 6621 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn78xx; 6622 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cn78xxp1; 6623 struct cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_s cnf75xx; 6624 }; 6625 6626 typedef union cvmx_pko_pse_dq_ecc_dbe_sts_cmb0 cvmx_pko_pse_dq_ecc_dbe_sts_cmb0_t; 6627 6628 /** 6629 * cvmx_pko_pse_dq_ecc_sbe_sts0 6630 */ 6631 union cvmx_pko_pse_dq_ecc_sbe_sts0 { 6632 u64 u64; 6633 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s { 6634 u64 dq_wt_ram_sbe : 1; 6635 u64 dq_rt7_sbe : 1; 6636 u64 dq_rt6_sbe : 1; 6637 u64 dq_rt5_sbe : 1; 6638 u64 dq_rt4_sbe : 1; 6639 u64 dq_rt3_sbe : 1; 6640 u64 dq_rt2_sbe : 1; 6641 u64 dq_rt1_sbe : 1; 6642 u64 dq_rt0_sbe : 1; 6643 u64 reserved_0_54 : 55; 6644 } s; 6645 struct cvmx_pko_pse_dq_ecc_sbe_sts0_cn73xx { 6646 u64 dq_wt_ram_sbe : 1; 6647 u64 reserved_57_62 : 6; 6648 u64 dq_rt1_sbe : 1; 6649 u64 dq_rt0_sbe : 1; 6650 u64 reserved_0_54 : 55; 6651 } cn73xx; 6652 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s cn78xx; 6653 struct cvmx_pko_pse_dq_ecc_sbe_sts0_s cn78xxp1; 6654 struct cvmx_pko_pse_dq_ecc_sbe_sts0_cn73xx cnf75xx; 6655 }; 6656 6657 typedef union cvmx_pko_pse_dq_ecc_sbe_sts0 cvmx_pko_pse_dq_ecc_sbe_sts0_t; 6658 6659 /** 6660 * cvmx_pko_pse_dq_ecc_sbe_sts_cmb0 6661 */ 6662 union cvmx_pko_pse_dq_ecc_sbe_sts_cmb0 { 6663 u64 u64; 6664 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s { 6665 u64 pse_dq_sbe_cmb0 : 1; 6666 u64 reserved_0_62 : 63; 6667 } s; 6668 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn73xx; 6669 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn78xx; 6670 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cn78xxp1; 6671 struct cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_s cnf75xx; 6672 }; 6673 6674 typedef union cvmx_pko_pse_dq_ecc_sbe_sts_cmb0 cvmx_pko_pse_dq_ecc_sbe_sts_cmb0_t; 6675 6676 /** 6677 * cvmx_pko_pse_pq_bist_status 6678 * 6679 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 6680 * 6681 */ 6682 union cvmx_pko_pse_pq_bist_status { 6683 u64 u64; 6684 struct cvmx_pko_pse_pq_bist_status_s { 6685 u64 reserved_15_63 : 49; 6686 u64 tp_sram : 1; 6687 u64 irq_fifo_sram : 1; 6688 u64 wmd_sram : 1; 6689 u64 wms_sram : 1; 6690 u64 cxd_sram : 1; 6691 u64 dqd_sram : 1; 6692 u64 dqs_sram : 1; 6693 u64 pqd_sram : 1; 6694 u64 pqr_sram : 1; 6695 u64 pqy_sram : 1; 6696 u64 pqg_sram : 1; 6697 u64 std_sram : 1; 6698 u64 st_sram : 1; 6699 u64 reserved_1_1 : 1; 6700 u64 cxs_sram : 1; 6701 } s; 6702 struct cvmx_pko_pse_pq_bist_status_cn73xx { 6703 u64 reserved_15_63 : 49; 6704 u64 tp_sram : 1; 6705 u64 reserved_13_13 : 1; 6706 u64 wmd_sram : 1; 6707 u64 reserved_11_11 : 1; 6708 u64 cxd_sram : 1; 6709 u64 dqd_sram : 1; 6710 u64 dqs_sram : 1; 6711 u64 pqd_sram : 1; 6712 u64 pqr_sram : 1; 6713 u64 pqy_sram : 1; 6714 u64 pqg_sram : 1; 6715 u64 std_sram : 1; 6716 u64 st_sram : 1; 6717 u64 reserved_1_1 : 1; 6718 u64 cxs_sram : 1; 6719 } cn73xx; 6720 struct cvmx_pko_pse_pq_bist_status_s cn78xx; 6721 struct cvmx_pko_pse_pq_bist_status_s cn78xxp1; 6722 struct cvmx_pko_pse_pq_bist_status_cn73xx cnf75xx; 6723 }; 6724 6725 typedef union cvmx_pko_pse_pq_bist_status cvmx_pko_pse_pq_bist_status_t; 6726 6727 /** 6728 * cvmx_pko_pse_pq_ecc_ctl0 6729 */ 6730 union cvmx_pko_pse_pq_ecc_ctl0 { 6731 u64 u64; 6732 struct cvmx_pko_pse_pq_ecc_ctl0_s { 6733 u64 pq_cxs_ram_flip : 2; 6734 u64 pq_cxs_ram_cdis : 1; 6735 u64 pq_cxd_ram_flip : 2; 6736 u64 pq_cxd_ram_cdis : 1; 6737 u64 irq_fifo_sram_flip : 2; 6738 u64 irq_fifo_sram_cdis : 1; 6739 u64 tp_sram_flip : 2; 6740 u64 tp_sram_cdis : 1; 6741 u64 pq_std_ram_flip : 2; 6742 u64 pq_std_ram_cdis : 1; 6743 u64 pq_st_ram_flip : 2; 6744 u64 pq_st_ram_cdis : 1; 6745 u64 pq_wmd_ram_flip : 2; 6746 u64 pq_wmd_ram_cdis : 1; 6747 u64 pq_wms_ram_flip : 2; 6748 u64 pq_wms_ram_cdis : 1; 6749 u64 reserved_0_39 : 40; 6750 } s; 6751 struct cvmx_pko_pse_pq_ecc_ctl0_cn73xx { 6752 u64 pq_cxs_ram_flip : 2; 6753 u64 pq_cxs_ram_cdis : 1; 6754 u64 pq_cxd_ram_flip : 2; 6755 u64 pq_cxd_ram_cdis : 1; 6756 u64 reserved_55_57 : 3; 6757 u64 tp_sram_flip : 2; 6758 u64 tp_sram_cdis : 1; 6759 u64 pq_std_ram_flip : 2; 6760 u64 pq_std_ram_cdis : 1; 6761 u64 pq_st_ram_flip : 2; 6762 u64 pq_st_ram_cdis : 1; 6763 u64 pq_wmd_ram_flip : 2; 6764 u64 pq_wmd_ram_cdis : 1; 6765 u64 reserved_0_42 : 43; 6766 } cn73xx; 6767 struct cvmx_pko_pse_pq_ecc_ctl0_s cn78xx; 6768 struct cvmx_pko_pse_pq_ecc_ctl0_s cn78xxp1; 6769 struct cvmx_pko_pse_pq_ecc_ctl0_cn73xx cnf75xx; 6770 }; 6771 6772 typedef union cvmx_pko_pse_pq_ecc_ctl0 cvmx_pko_pse_pq_ecc_ctl0_t; 6773 6774 /** 6775 * cvmx_pko_pse_pq_ecc_dbe_sts0 6776 */ 6777 union cvmx_pko_pse_pq_ecc_dbe_sts0 { 6778 u64 u64; 6779 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s { 6780 u64 pq_cxs_ram_dbe : 1; 6781 u64 pq_cxd_ram_dbe : 1; 6782 u64 irq_fifo_sram_dbe : 1; 6783 u64 tp_sram_dbe : 1; 6784 u64 pq_std_ram_dbe : 1; 6785 u64 pq_st_ram_dbe : 1; 6786 u64 pq_wmd_ram_dbe : 1; 6787 u64 pq_wms_ram_dbe : 1; 6788 u64 reserved_0_55 : 56; 6789 } s; 6790 struct cvmx_pko_pse_pq_ecc_dbe_sts0_cn73xx { 6791 u64 pq_cxs_ram_dbe : 1; 6792 u64 pq_cxd_ram_dbe : 1; 6793 u64 reserved_61_61 : 1; 6794 u64 tp_sram_dbe : 1; 6795 u64 pq_std_ram_dbe : 1; 6796 u64 pq_st_ram_dbe : 1; 6797 u64 pq_wmd_ram_dbe : 1; 6798 u64 reserved_0_56 : 57; 6799 } cn73xx; 6800 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s cn78xx; 6801 struct cvmx_pko_pse_pq_ecc_dbe_sts0_s cn78xxp1; 6802 struct cvmx_pko_pse_pq_ecc_dbe_sts0_cn73xx cnf75xx; 6803 }; 6804 6805 typedef union cvmx_pko_pse_pq_ecc_dbe_sts0 cvmx_pko_pse_pq_ecc_dbe_sts0_t; 6806 6807 /** 6808 * cvmx_pko_pse_pq_ecc_dbe_sts_cmb0 6809 */ 6810 union cvmx_pko_pse_pq_ecc_dbe_sts_cmb0 { 6811 u64 u64; 6812 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s { 6813 u64 pse_pq_dbe_cmb0 : 1; 6814 u64 reserved_0_62 : 63; 6815 } s; 6816 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn73xx; 6817 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn78xx; 6818 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cn78xxp1; 6819 struct cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_s cnf75xx; 6820 }; 6821 6822 typedef union cvmx_pko_pse_pq_ecc_dbe_sts_cmb0 cvmx_pko_pse_pq_ecc_dbe_sts_cmb0_t; 6823 6824 /** 6825 * cvmx_pko_pse_pq_ecc_sbe_sts0 6826 */ 6827 union cvmx_pko_pse_pq_ecc_sbe_sts0 { 6828 u64 u64; 6829 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s { 6830 u64 pq_cxs_ram_sbe : 1; 6831 u64 pq_cxd_ram_sbe : 1; 6832 u64 irq_fifo_sram_sbe : 1; 6833 u64 tp_sram_sbe : 1; 6834 u64 pq_std_ram_sbe : 1; 6835 u64 pq_st_ram_sbe : 1; 6836 u64 pq_wmd_ram_sbe : 1; 6837 u64 pq_wms_ram_sbe : 1; 6838 u64 reserved_0_55 : 56; 6839 } s; 6840 struct cvmx_pko_pse_pq_ecc_sbe_sts0_cn73xx { 6841 u64 pq_cxs_ram_sbe : 1; 6842 u64 pq_cxd_ram_sbe : 1; 6843 u64 reserved_61_61 : 1; 6844 u64 tp_sram_sbe : 1; 6845 u64 pq_std_ram_sbe : 1; 6846 u64 pq_st_ram_sbe : 1; 6847 u64 pq_wmd_ram_sbe : 1; 6848 u64 reserved_0_56 : 57; 6849 } cn73xx; 6850 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s cn78xx; 6851 struct cvmx_pko_pse_pq_ecc_sbe_sts0_s cn78xxp1; 6852 struct cvmx_pko_pse_pq_ecc_sbe_sts0_cn73xx cnf75xx; 6853 }; 6854 6855 typedef union cvmx_pko_pse_pq_ecc_sbe_sts0 cvmx_pko_pse_pq_ecc_sbe_sts0_t; 6856 6857 /** 6858 * cvmx_pko_pse_pq_ecc_sbe_sts_cmb0 6859 */ 6860 union cvmx_pko_pse_pq_ecc_sbe_sts_cmb0 { 6861 u64 u64; 6862 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s { 6863 u64 pse_pq_sbe_cmb0 : 1; 6864 u64 reserved_0_62 : 63; 6865 } s; 6866 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn73xx; 6867 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn78xx; 6868 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cn78xxp1; 6869 struct cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_s cnf75xx; 6870 }; 6871 6872 typedef union cvmx_pko_pse_pq_ecc_sbe_sts_cmb0 cvmx_pko_pse_pq_ecc_sbe_sts_cmb0_t; 6873 6874 /** 6875 * cvmx_pko_pse_sq1_bist_status 6876 * 6877 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 6878 * 6879 */ 6880 union cvmx_pko_pse_sq1_bist_status { 6881 u64 u64; 6882 struct cvmx_pko_pse_sq1_bist_status_s { 6883 u64 reserved_29_63 : 35; 6884 u64 sc_sram : 1; 6885 u64 pc_sram : 1; 6886 u64 xon_sram : 1; 6887 u64 cc_sram : 1; 6888 u64 vc1_sram : 1; 6889 u64 vc0_sram : 1; 6890 u64 reserved_21_22 : 2; 6891 u64 tp1_sram : 1; 6892 u64 tp0_sram : 1; 6893 u64 xo_sram : 1; 6894 u64 rt_sram : 1; 6895 u64 reserved_9_16 : 8; 6896 u64 tw1_cmd_fifo : 1; 6897 u64 std_sram : 1; 6898 u64 sts_sram : 1; 6899 u64 tw0_cmd_fifo : 1; 6900 u64 cxd_sram : 1; 6901 u64 cxs_sram : 1; 6902 u64 nt_sram : 1; 6903 u64 pt_sram : 1; 6904 u64 wt_sram : 1; 6905 } s; 6906 struct cvmx_pko_pse_sq1_bist_status_cn73xx { 6907 u64 reserved_29_63 : 35; 6908 u64 sc_sram : 1; 6909 u64 pc_sram : 1; 6910 u64 xon_sram : 1; 6911 u64 cc_sram : 1; 6912 u64 vc1_sram : 1; 6913 u64 vc0_sram : 1; 6914 u64 reserved_20_22 : 3; 6915 u64 tp0_sram : 1; 6916 u64 xo_sram : 1; 6917 u64 rt_sram : 1; 6918 u64 reserved_9_16 : 8; 6919 u64 tw1_cmd_fifo : 1; 6920 u64 std_sram : 1; 6921 u64 sts_sram : 1; 6922 u64 tw0_cmd_fifo : 1; 6923 u64 cxd_sram : 1; 6924 u64 cxs_sram : 1; 6925 u64 nt_sram : 1; 6926 u64 pt_sram : 1; 6927 u64 wt_sram : 1; 6928 } cn73xx; 6929 struct cvmx_pko_pse_sq1_bist_status_s cn78xx; 6930 struct cvmx_pko_pse_sq1_bist_status_s cn78xxp1; 6931 struct cvmx_pko_pse_sq1_bist_status_cn73xx cnf75xx; 6932 }; 6933 6934 typedef union cvmx_pko_pse_sq1_bist_status cvmx_pko_pse_sq1_bist_status_t; 6935 6936 /** 6937 * cvmx_pko_pse_sq1_ecc_ctl0 6938 */ 6939 union cvmx_pko_pse_sq1_ecc_ctl0 { 6940 u64 u64; 6941 struct cvmx_pko_pse_sq1_ecc_ctl0_s { 6942 u64 cxs_ram_flip : 2; 6943 u64 cxs_ram_cdis : 1; 6944 u64 cxd_ram_flip : 2; 6945 u64 cxd_ram_cdis : 1; 6946 u64 vc1_sram_flip : 2; 6947 u64 vc1_sram_cdis : 1; 6948 u64 vc0_sram_flip : 2; 6949 u64 vc0_sram_cdis : 1; 6950 u64 sq_pt_ram_flip : 2; 6951 u64 sq_pt_ram_cdis : 1; 6952 u64 sq_nt_ram_flip : 2; 6953 u64 sq_nt_ram_cdis : 1; 6954 u64 rt_ram_flip : 2; 6955 u64 rt_ram_cdis : 1; 6956 u64 pc_ram_flip : 2; 6957 u64 pc_ram_cdis : 1; 6958 u64 tw1_cmd_fifo_ram_flip : 2; 6959 u64 tw1_cmd_fifo_ram_cdis : 1; 6960 u64 tw0_cmd_fifo_ram_flip : 2; 6961 u64 tw0_cmd_fifo_ram_cdis : 1; 6962 u64 tp1_sram_flip : 2; 6963 u64 tp1_sram_cdis : 1; 6964 u64 tp0_sram_flip : 2; 6965 u64 tp0_sram_cdis : 1; 6966 u64 sts1_ram_flip : 2; 6967 u64 sts1_ram_cdis : 1; 6968 u64 sts0_ram_flip : 2; 6969 u64 sts0_ram_cdis : 1; 6970 u64 std1_ram_flip : 2; 6971 u64 std1_ram_cdis : 1; 6972 u64 std0_ram_flip : 2; 6973 u64 std0_ram_cdis : 1; 6974 u64 wt_ram_flip : 2; 6975 u64 wt_ram_cdis : 1; 6976 u64 sc_ram_flip : 2; 6977 u64 sc_ram_cdis : 1; 6978 u64 reserved_0_9 : 10; 6979 } s; 6980 struct cvmx_pko_pse_sq1_ecc_ctl0_cn73xx { 6981 u64 cxs_ram_flip : 2; 6982 u64 cxs_ram_cdis : 1; 6983 u64 cxd_ram_flip : 2; 6984 u64 cxd_ram_cdis : 1; 6985 u64 reserved_55_57 : 3; 6986 u64 vc0_sram_flip : 2; 6987 u64 vc0_sram_cdis : 1; 6988 u64 sq_pt_ram_flip : 2; 6989 u64 sq_pt_ram_cdis : 1; 6990 u64 sq_nt_ram_flip : 2; 6991 u64 sq_nt_ram_cdis : 1; 6992 u64 rt_ram_flip : 2; 6993 u64 rt_ram_cdis : 1; 6994 u64 pc_ram_flip : 2; 6995 u64 pc_ram_cdis : 1; 6996 u64 reserved_37_39 : 3; 6997 u64 tw0_cmd_fifo_ram_flip : 2; 6998 u64 tw0_cmd_fifo_ram_cdis : 1; 6999 u64 reserved_31_33 : 3; 7000 u64 tp0_sram_flip : 2; 7001 u64 tp0_sram_cdis : 1; 7002 u64 reserved_25_27 : 3; 7003 u64 sts0_ram_flip : 2; 7004 u64 sts0_ram_cdis : 1; 7005 u64 reserved_19_21 : 3; 7006 u64 std0_ram_flip : 2; 7007 u64 std0_ram_cdis : 1; 7008 u64 wt_ram_flip : 2; 7009 u64 wt_ram_cdis : 1; 7010 u64 sc_ram_flip : 2; 7011 u64 sc_ram_cdis : 1; 7012 u64 reserved_0_9 : 10; 7013 } cn73xx; 7014 struct cvmx_pko_pse_sq1_ecc_ctl0_s cn78xx; 7015 struct cvmx_pko_pse_sq1_ecc_ctl0_s cn78xxp1; 7016 struct cvmx_pko_pse_sq1_ecc_ctl0_cn73xx cnf75xx; 7017 }; 7018 7019 typedef union cvmx_pko_pse_sq1_ecc_ctl0 cvmx_pko_pse_sq1_ecc_ctl0_t; 7020 7021 /** 7022 * cvmx_pko_pse_sq1_ecc_dbe_sts0 7023 */ 7024 union cvmx_pko_pse_sq1_ecc_dbe_sts0 { 7025 u64 u64; 7026 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s { 7027 u64 cxs_ram_dbe : 1; 7028 u64 cxd_ram_dbe : 1; 7029 u64 vc1_sram_dbe : 1; 7030 u64 vc0_sram_dbe : 1; 7031 u64 sq_pt_ram_dbe : 1; 7032 u64 sq_nt_ram_dbe : 1; 7033 u64 rt_ram_dbe : 1; 7034 u64 pc_ram_dbe : 1; 7035 u64 tw1_cmd_fifo_ram_dbe : 1; 7036 u64 tw0_cmd_fifo_ram_dbe : 1; 7037 u64 tp1_sram_dbe : 1; 7038 u64 tp0_sram_dbe : 1; 7039 u64 sts1_ram_dbe : 1; 7040 u64 sts0_ram_dbe : 1; 7041 u64 std1_ram_dbe : 1; 7042 u64 std0_ram_dbe : 1; 7043 u64 wt_ram_dbe : 1; 7044 u64 sc_ram_dbe : 1; 7045 u64 reserved_0_45 : 46; 7046 } s; 7047 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_cn73xx { 7048 u64 cxs_ram_dbe : 1; 7049 u64 cxd_ram_dbe : 1; 7050 u64 reserved_61_61 : 1; 7051 u64 vc0_sram_dbe : 1; 7052 u64 sq_pt_ram_dbe : 1; 7053 u64 sq_nt_ram_dbe : 1; 7054 u64 rt_ram_dbe : 1; 7055 u64 pc_ram_dbe : 1; 7056 u64 reserved_55_55 : 1; 7057 u64 tw0_cmd_fifo_ram_dbe : 1; 7058 u64 reserved_53_53 : 1; 7059 u64 tp0_sram_dbe : 1; 7060 u64 reserved_51_51 : 1; 7061 u64 sts0_ram_dbe : 1; 7062 u64 reserved_49_49 : 1; 7063 u64 std0_ram_dbe : 1; 7064 u64 wt_ram_dbe : 1; 7065 u64 sc_ram_dbe : 1; 7066 u64 reserved_0_45 : 46; 7067 } cn73xx; 7068 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s cn78xx; 7069 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_s cn78xxp1; 7070 struct cvmx_pko_pse_sq1_ecc_dbe_sts0_cn73xx cnf75xx; 7071 }; 7072 7073 typedef union cvmx_pko_pse_sq1_ecc_dbe_sts0 cvmx_pko_pse_sq1_ecc_dbe_sts0_t; 7074 7075 /** 7076 * cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0 7077 */ 7078 union cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0 { 7079 u64 u64; 7080 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s { 7081 u64 pse_sq1_dbe_cmb0 : 1; 7082 u64 reserved_0_62 : 63; 7083 } s; 7084 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn73xx; 7085 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn78xx; 7086 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cn78xxp1; 7087 struct cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_s cnf75xx; 7088 }; 7089 7090 typedef union cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq1_ecc_dbe_sts_cmb0_t; 7091 7092 /** 7093 * cvmx_pko_pse_sq1_ecc_sbe_sts0 7094 */ 7095 union cvmx_pko_pse_sq1_ecc_sbe_sts0 { 7096 u64 u64; 7097 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s { 7098 u64 cxs_ram_sbe : 1; 7099 u64 cxd_ram_sbe : 1; 7100 u64 vc1_sram_sbe : 1; 7101 u64 vc0_sram_sbe : 1; 7102 u64 sq_pt_ram_sbe : 1; 7103 u64 sq_nt_ram_sbe : 1; 7104 u64 rt_ram_sbe : 1; 7105 u64 pc_ram_sbe : 1; 7106 u64 tw1_cmd_fifo_ram_sbe : 1; 7107 u64 tw0_cmd_fifo_ram_sbe : 1; 7108 u64 tp1_sram_sbe : 1; 7109 u64 tp0_sram_sbe : 1; 7110 u64 sts1_ram_sbe : 1; 7111 u64 sts0_ram_sbe : 1; 7112 u64 std1_ram_sbe : 1; 7113 u64 std0_ram_sbe : 1; 7114 u64 wt_ram_sbe : 1; 7115 u64 sc_ram_sbe : 1; 7116 u64 reserved_0_45 : 46; 7117 } s; 7118 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_cn73xx { 7119 u64 cxs_ram_sbe : 1; 7120 u64 cxd_ram_sbe : 1; 7121 u64 reserved_61_61 : 1; 7122 u64 vc0_sram_sbe : 1; 7123 u64 sq_pt_ram_sbe : 1; 7124 u64 sq_nt_ram_sbe : 1; 7125 u64 rt_ram_sbe : 1; 7126 u64 pc_ram_sbe : 1; 7127 u64 reserved_55_55 : 1; 7128 u64 tw0_cmd_fifo_ram_sbe : 1; 7129 u64 reserved_53_53 : 1; 7130 u64 tp0_sram_sbe : 1; 7131 u64 reserved_51_51 : 1; 7132 u64 sts0_ram_sbe : 1; 7133 u64 reserved_49_49 : 1; 7134 u64 std0_ram_sbe : 1; 7135 u64 wt_ram_sbe : 1; 7136 u64 sc_ram_sbe : 1; 7137 u64 reserved_0_45 : 46; 7138 } cn73xx; 7139 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s cn78xx; 7140 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_s cn78xxp1; 7141 struct cvmx_pko_pse_sq1_ecc_sbe_sts0_cn73xx cnf75xx; 7142 }; 7143 7144 typedef union cvmx_pko_pse_sq1_ecc_sbe_sts0 cvmx_pko_pse_sq1_ecc_sbe_sts0_t; 7145 7146 /** 7147 * cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0 7148 */ 7149 union cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0 { 7150 u64 u64; 7151 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s { 7152 u64 pse_sq1_sbe_cmb0 : 1; 7153 u64 reserved_0_62 : 63; 7154 } s; 7155 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn73xx; 7156 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn78xx; 7157 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cn78xxp1; 7158 struct cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_s cnf75xx; 7159 }; 7160 7161 typedef union cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq1_ecc_sbe_sts_cmb0_t; 7162 7163 /** 7164 * cvmx_pko_pse_sq2_bist_status 7165 * 7166 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 7167 * 7168 */ 7169 union cvmx_pko_pse_sq2_bist_status { 7170 u64 u64; 7171 struct cvmx_pko_pse_sq2_bist_status_s { 7172 u64 reserved_29_63 : 35; 7173 u64 sc_sram : 1; 7174 u64 reserved_21_27 : 7; 7175 u64 tp1_sram : 1; 7176 u64 tp0_sram : 1; 7177 u64 reserved_18_18 : 1; 7178 u64 rt_sram : 1; 7179 u64 reserved_9_16 : 8; 7180 u64 tw1_cmd_fifo : 1; 7181 u64 std_sram : 1; 7182 u64 sts_sram : 1; 7183 u64 tw0_cmd_fifo : 1; 7184 u64 reserved_3_4 : 2; 7185 u64 nt_sram : 1; 7186 u64 pt_sram : 1; 7187 u64 wt_sram : 1; 7188 } s; 7189 struct cvmx_pko_pse_sq2_bist_status_cn73xx { 7190 u64 reserved_29_63 : 35; 7191 u64 sc_sram : 1; 7192 u64 reserved_20_27 : 8; 7193 u64 tp0_sram : 1; 7194 u64 reserved_18_18 : 1; 7195 u64 rt_sram : 1; 7196 u64 reserved_8_16 : 9; 7197 u64 std_sram : 1; 7198 u64 sts_sram : 1; 7199 u64 tw0_cmd_fifo : 1; 7200 u64 reserved_3_4 : 2; 7201 u64 nt_sram : 1; 7202 u64 pt_sram : 1; 7203 u64 wt_sram : 1; 7204 } cn73xx; 7205 struct cvmx_pko_pse_sq2_bist_status_s cn78xx; 7206 struct cvmx_pko_pse_sq2_bist_status_s cn78xxp1; 7207 struct cvmx_pko_pse_sq2_bist_status_cn73xx cnf75xx; 7208 }; 7209 7210 typedef union cvmx_pko_pse_sq2_bist_status cvmx_pko_pse_sq2_bist_status_t; 7211 7212 /** 7213 * cvmx_pko_pse_sq2_ecc_ctl0 7214 */ 7215 union cvmx_pko_pse_sq2_ecc_ctl0 { 7216 u64 u64; 7217 struct cvmx_pko_pse_sq2_ecc_ctl0_s { 7218 u64 sq_pt_ram_flip : 2; 7219 u64 sq_pt_ram_cdis : 1; 7220 u64 sq_nt_ram_flip : 2; 7221 u64 sq_nt_ram_cdis : 1; 7222 u64 rt_ram_flip : 2; 7223 u64 rt_ram_cdis : 1; 7224 u64 tw1_cmd_fifo_ram_flip : 2; 7225 u64 tw1_cmd_fifo_ram_cdis : 1; 7226 u64 tw0_cmd_fifo_ram_flip : 2; 7227 u64 tw0_cmd_fifo_ram_cdis : 1; 7228 u64 tp1_sram_flip : 2; 7229 u64 tp1_sram_cdis : 1; 7230 u64 tp0_sram_flip : 2; 7231 u64 tp0_sram_cdis : 1; 7232 u64 sts1_ram_flip : 2; 7233 u64 sts1_ram_cdis : 1; 7234 u64 sts0_ram_flip : 2; 7235 u64 sts0_ram_cdis : 1; 7236 u64 std1_ram_flip : 2; 7237 u64 std1_ram_cdis : 1; 7238 u64 std0_ram_flip : 2; 7239 u64 std0_ram_cdis : 1; 7240 u64 wt_ram_flip : 2; 7241 u64 wt_ram_cdis : 1; 7242 u64 sc_ram_flip : 2; 7243 u64 sc_ram_cdis : 1; 7244 u64 reserved_0_24 : 25; 7245 } s; 7246 struct cvmx_pko_pse_sq2_ecc_ctl0_cn73xx { 7247 u64 sq_pt_ram_flip : 2; 7248 u64 sq_pt_ram_cdis : 1; 7249 u64 sq_nt_ram_flip : 2; 7250 u64 sq_nt_ram_cdis : 1; 7251 u64 rt_ram_flip : 2; 7252 u64 rt_ram_cdis : 1; 7253 u64 reserved_52_54 : 3; 7254 u64 tw0_cmd_fifo_ram_flip : 2; 7255 u64 tw0_cmd_fifo_ram_cdis : 1; 7256 u64 reserved_46_48 : 3; 7257 u64 tp0_sram_flip : 2; 7258 u64 tp0_sram_cdis : 1; 7259 u64 reserved_40_42 : 3; 7260 u64 sts0_ram_flip : 2; 7261 u64 sts0_ram_cdis : 1; 7262 u64 reserved_34_36 : 3; 7263 u64 std0_ram_flip : 2; 7264 u64 std0_ram_cdis : 1; 7265 u64 wt_ram_flip : 2; 7266 u64 wt_ram_cdis : 1; 7267 u64 sc_ram_flip : 2; 7268 u64 sc_ram_cdis : 1; 7269 u64 reserved_0_24 : 25; 7270 } cn73xx; 7271 struct cvmx_pko_pse_sq2_ecc_ctl0_s cn78xx; 7272 struct cvmx_pko_pse_sq2_ecc_ctl0_s cn78xxp1; 7273 struct cvmx_pko_pse_sq2_ecc_ctl0_cn73xx cnf75xx; 7274 }; 7275 7276 typedef union cvmx_pko_pse_sq2_ecc_ctl0 cvmx_pko_pse_sq2_ecc_ctl0_t; 7277 7278 /** 7279 * cvmx_pko_pse_sq2_ecc_dbe_sts0 7280 */ 7281 union cvmx_pko_pse_sq2_ecc_dbe_sts0 { 7282 u64 u64; 7283 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s { 7284 u64 sq_pt_ram_dbe : 1; 7285 u64 sq_nt_ram_dbe : 1; 7286 u64 rt_ram_dbe : 1; 7287 u64 tw1_cmd_fifo_ram_dbe : 1; 7288 u64 tw0_cmd_fifo_ram_dbe : 1; 7289 u64 tp1_sram_dbe : 1; 7290 u64 tp0_sram_dbe : 1; 7291 u64 sts1_ram_dbe : 1; 7292 u64 sts0_ram_dbe : 1; 7293 u64 std1_ram_dbe : 1; 7294 u64 std0_ram_dbe : 1; 7295 u64 wt_ram_dbe : 1; 7296 u64 sc_ram_dbe : 1; 7297 u64 reserved_0_50 : 51; 7298 } s; 7299 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_cn73xx { 7300 u64 sq_pt_ram_dbe : 1; 7301 u64 sq_nt_ram_dbe : 1; 7302 u64 rt_ram_dbe : 1; 7303 u64 reserved_60_60 : 1; 7304 u64 tw0_cmd_fifo_ram_dbe : 1; 7305 u64 reserved_58_58 : 1; 7306 u64 tp0_sram_dbe : 1; 7307 u64 reserved_56_56 : 1; 7308 u64 sts0_ram_dbe : 1; 7309 u64 reserved_54_54 : 1; 7310 u64 std0_ram_dbe : 1; 7311 u64 wt_ram_dbe : 1; 7312 u64 sc_ram_dbe : 1; 7313 u64 reserved_0_50 : 51; 7314 } cn73xx; 7315 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s cn78xx; 7316 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_s cn78xxp1; 7317 struct cvmx_pko_pse_sq2_ecc_dbe_sts0_cn73xx cnf75xx; 7318 }; 7319 7320 typedef union cvmx_pko_pse_sq2_ecc_dbe_sts0 cvmx_pko_pse_sq2_ecc_dbe_sts0_t; 7321 7322 /** 7323 * cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0 7324 */ 7325 union cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0 { 7326 u64 u64; 7327 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s { 7328 u64 pse_sq2_dbe_cmb0 : 1; 7329 u64 reserved_0_62 : 63; 7330 } s; 7331 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn73xx; 7332 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn78xx; 7333 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cn78xxp1; 7334 struct cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_s cnf75xx; 7335 }; 7336 7337 typedef union cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq2_ecc_dbe_sts_cmb0_t; 7338 7339 /** 7340 * cvmx_pko_pse_sq2_ecc_sbe_sts0 7341 */ 7342 union cvmx_pko_pse_sq2_ecc_sbe_sts0 { 7343 u64 u64; 7344 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s { 7345 u64 sq_pt_ram_sbe : 1; 7346 u64 sq_nt_ram_sbe : 1; 7347 u64 rt_ram_sbe : 1; 7348 u64 tw1_cmd_fifo_ram_sbe : 1; 7349 u64 tw0_cmd_fifo_ram_sbe : 1; 7350 u64 tp1_sram_sbe : 1; 7351 u64 tp0_sram_sbe : 1; 7352 u64 sts1_ram_sbe : 1; 7353 u64 sts0_ram_sbe : 1; 7354 u64 std1_ram_sbe : 1; 7355 u64 std0_ram_sbe : 1; 7356 u64 wt_ram_sbe : 1; 7357 u64 sc_ram_sbe : 1; 7358 u64 reserved_0_50 : 51; 7359 } s; 7360 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_cn73xx { 7361 u64 sq_pt_ram_sbe : 1; 7362 u64 sq_nt_ram_sbe : 1; 7363 u64 rt_ram_sbe : 1; 7364 u64 reserved_60_60 : 1; 7365 u64 tw0_cmd_fifo_ram_sbe : 1; 7366 u64 reserved_58_58 : 1; 7367 u64 tp0_sram_sbe : 1; 7368 u64 reserved_56_56 : 1; 7369 u64 sts0_ram_sbe : 1; 7370 u64 reserved_54_54 : 1; 7371 u64 std0_ram_sbe : 1; 7372 u64 wt_ram_sbe : 1; 7373 u64 sc_ram_sbe : 1; 7374 u64 reserved_0_50 : 51; 7375 } cn73xx; 7376 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s cn78xx; 7377 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_s cn78xxp1; 7378 struct cvmx_pko_pse_sq2_ecc_sbe_sts0_cn73xx cnf75xx; 7379 }; 7380 7381 typedef union cvmx_pko_pse_sq2_ecc_sbe_sts0 cvmx_pko_pse_sq2_ecc_sbe_sts0_t; 7382 7383 /** 7384 * cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0 7385 */ 7386 union cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0 { 7387 u64 u64; 7388 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s { 7389 u64 pse_sq2_sbe_cmb0 : 1; 7390 u64 reserved_0_62 : 63; 7391 } s; 7392 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn73xx; 7393 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn78xx; 7394 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cn78xxp1; 7395 struct cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_s cnf75xx; 7396 }; 7397 7398 typedef union cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq2_ecc_sbe_sts_cmb0_t; 7399 7400 /** 7401 * cvmx_pko_pse_sq3_bist_status 7402 * 7403 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 7404 * 7405 */ 7406 union cvmx_pko_pse_sq3_bist_status { 7407 u64 u64; 7408 struct cvmx_pko_pse_sq3_bist_status_s { 7409 u64 reserved_29_63 : 35; 7410 u64 sc_sram : 1; 7411 u64 reserved_23_27 : 5; 7412 u64 tp3_sram : 1; 7413 u64 tp2_sram : 1; 7414 u64 tp1_sram : 1; 7415 u64 tp0_sram : 1; 7416 u64 reserved_18_18 : 1; 7417 u64 rt_sram : 1; 7418 u64 reserved_15_16 : 2; 7419 u64 tw3_cmd_fifo : 1; 7420 u64 reserved_12_13 : 2; 7421 u64 tw2_cmd_fifo : 1; 7422 u64 reserved_9_10 : 2; 7423 u64 tw1_cmd_fifo : 1; 7424 u64 std_sram : 1; 7425 u64 sts_sram : 1; 7426 u64 tw0_cmd_fifo : 1; 7427 u64 reserved_3_4 : 2; 7428 u64 nt_sram : 1; 7429 u64 pt_sram : 1; 7430 u64 wt_sram : 1; 7431 } s; 7432 struct cvmx_pko_pse_sq3_bist_status_cn73xx { 7433 u64 reserved_29_63 : 35; 7434 u64 sc_sram : 1; 7435 u64 reserved_20_27 : 8; 7436 u64 tp0_sram : 1; 7437 u64 reserved_18_18 : 1; 7438 u64 rt_sram : 1; 7439 u64 reserved_8_16 : 9; 7440 u64 std_sram : 1; 7441 u64 sts_sram : 1; 7442 u64 tw0_cmd_fifo : 1; 7443 u64 reserved_3_4 : 2; 7444 u64 nt_sram : 1; 7445 u64 pt_sram : 1; 7446 u64 wt_sram : 1; 7447 } cn73xx; 7448 struct cvmx_pko_pse_sq3_bist_status_s cn78xx; 7449 struct cvmx_pko_pse_sq3_bist_status_s cn78xxp1; 7450 struct cvmx_pko_pse_sq3_bist_status_cn73xx cnf75xx; 7451 }; 7452 7453 typedef union cvmx_pko_pse_sq3_bist_status cvmx_pko_pse_sq3_bist_status_t; 7454 7455 /** 7456 * cvmx_pko_pse_sq3_ecc_ctl0 7457 */ 7458 union cvmx_pko_pse_sq3_ecc_ctl0 { 7459 u64 u64; 7460 struct cvmx_pko_pse_sq3_ecc_ctl0_s { 7461 u64 sq_pt_ram_flip : 2; 7462 u64 sq_pt_ram_cdis : 1; 7463 u64 sq_nt_ram_flip : 2; 7464 u64 sq_nt_ram_cdis : 1; 7465 u64 rt_ram_flip : 2; 7466 u64 rt_ram_cdis : 1; 7467 u64 tw3_cmd_fifo_ram_flip : 2; 7468 u64 tw3_cmd_fifo_ram_cdis : 1; 7469 u64 tw2_cmd_fifo_ram_flip : 2; 7470 u64 tw2_cmd_fifo_ram_cdis : 1; 7471 u64 tw1_cmd_fifo_ram_flip : 2; 7472 u64 tw1_cmd_fifo_ram_cdis : 1; 7473 u64 tw0_cmd_fifo_ram_flip : 2; 7474 u64 tw0_cmd_fifo_ram_cdis : 1; 7475 u64 tp3_sram_flip : 2; 7476 u64 tp3_sram_cdis : 1; 7477 u64 tp2_sram_flip : 2; 7478 u64 tp2_sram_cdis : 1; 7479 u64 tp1_sram_flip : 2; 7480 u64 tp1_sram_cdis : 1; 7481 u64 tp0_sram_flip : 2; 7482 u64 tp0_sram_cdis : 1; 7483 u64 sts3_ram_flip : 2; 7484 u64 sts3_ram_cdis : 1; 7485 u64 sts2_ram_flip : 2; 7486 u64 sts2_ram_cdis : 1; 7487 u64 sts1_ram_flip : 2; 7488 u64 sts1_ram_cdis : 1; 7489 u64 sts0_ram_flip : 2; 7490 u64 sts0_ram_cdis : 1; 7491 u64 std3_ram_flip : 2; 7492 u64 std3_ram_cdis : 1; 7493 u64 std2_ram_flip : 2; 7494 u64 std2_ram_cdis : 1; 7495 u64 std1_ram_flip : 2; 7496 u64 std1_ram_cdis : 1; 7497 u64 std0_ram_flip : 2; 7498 u64 std0_ram_cdis : 1; 7499 u64 wt_ram_flip : 2; 7500 u64 wt_ram_cdis : 1; 7501 u64 sc_ram_flip : 2; 7502 u64 sc_ram_cdis : 1; 7503 u64 reserved_0_0 : 1; 7504 } s; 7505 struct cvmx_pko_pse_sq3_ecc_ctl0_cn73xx { 7506 u64 sq_pt_ram_flip : 2; 7507 u64 sq_pt_ram_cdis : 1; 7508 u64 sq_nt_ram_flip : 2; 7509 u64 sq_nt_ram_cdis : 1; 7510 u64 rt_ram_flip : 2; 7511 u64 rt_ram_cdis : 1; 7512 u64 reserved_46_54 : 9; 7513 u64 tw0_cmd_fifo_ram_flip : 2; 7514 u64 tw0_cmd_fifo_ram_cdis : 1; 7515 u64 reserved_34_42 : 9; 7516 u64 tp0_sram_flip : 2; 7517 u64 tp0_sram_cdis : 1; 7518 u64 reserved_22_30 : 9; 7519 u64 sts0_ram_flip : 2; 7520 u64 sts0_ram_cdis : 1; 7521 u64 reserved_10_18 : 9; 7522 u64 std0_ram_flip : 2; 7523 u64 std0_ram_cdis : 1; 7524 u64 wt_ram_flip : 2; 7525 u64 wt_ram_cdis : 1; 7526 u64 sc_ram_flip : 2; 7527 u64 sc_ram_cdis : 1; 7528 u64 reserved_0_0 : 1; 7529 } cn73xx; 7530 struct cvmx_pko_pse_sq3_ecc_ctl0_s cn78xx; 7531 struct cvmx_pko_pse_sq3_ecc_ctl0_s cn78xxp1; 7532 struct cvmx_pko_pse_sq3_ecc_ctl0_cn73xx cnf75xx; 7533 }; 7534 7535 typedef union cvmx_pko_pse_sq3_ecc_ctl0 cvmx_pko_pse_sq3_ecc_ctl0_t; 7536 7537 /** 7538 * cvmx_pko_pse_sq3_ecc_dbe_sts0 7539 */ 7540 union cvmx_pko_pse_sq3_ecc_dbe_sts0 { 7541 u64 u64; 7542 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s { 7543 u64 sq_pt_ram_dbe : 1; 7544 u64 sq_nt_ram_dbe : 1; 7545 u64 rt_ram_dbe : 1; 7546 u64 tw3_cmd_fifo_ram_dbe : 1; 7547 u64 tw2_cmd_fifo_ram_dbe : 1; 7548 u64 tw1_cmd_fifo_ram_dbe : 1; 7549 u64 tw0_cmd_fifo_ram_dbe : 1; 7550 u64 tp3_sram_dbe : 1; 7551 u64 tp2_sram_dbe : 1; 7552 u64 tp1_sram_dbe : 1; 7553 u64 tp0_sram_dbe : 1; 7554 u64 sts3_ram_dbe : 1; 7555 u64 sts2_ram_dbe : 1; 7556 u64 sts1_ram_dbe : 1; 7557 u64 sts0_ram_dbe : 1; 7558 u64 std3_ram_dbe : 1; 7559 u64 std2_ram_dbe : 1; 7560 u64 std1_ram_dbe : 1; 7561 u64 std0_ram_dbe : 1; 7562 u64 wt_ram_dbe : 1; 7563 u64 sc_ram_dbe : 1; 7564 u64 reserved_0_42 : 43; 7565 } s; 7566 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_cn73xx { 7567 u64 sq_pt_ram_dbe : 1; 7568 u64 sq_nt_ram_dbe : 1; 7569 u64 rt_ram_dbe : 1; 7570 u64 reserved_58_60 : 3; 7571 u64 tw0_cmd_fifo_ram_dbe : 1; 7572 u64 reserved_54_56 : 3; 7573 u64 tp0_sram_dbe : 1; 7574 u64 reserved_50_52 : 3; 7575 u64 sts0_ram_dbe : 1; 7576 u64 reserved_46_48 : 3; 7577 u64 std0_ram_dbe : 1; 7578 u64 wt_ram_dbe : 1; 7579 u64 sc_ram_dbe : 1; 7580 u64 reserved_0_42 : 43; 7581 } cn73xx; 7582 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s cn78xx; 7583 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_s cn78xxp1; 7584 struct cvmx_pko_pse_sq3_ecc_dbe_sts0_cn73xx cnf75xx; 7585 }; 7586 7587 typedef union cvmx_pko_pse_sq3_ecc_dbe_sts0 cvmx_pko_pse_sq3_ecc_dbe_sts0_t; 7588 7589 /** 7590 * cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0 7591 */ 7592 union cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0 { 7593 u64 u64; 7594 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s { 7595 u64 pse_sq3_dbe_cmb0 : 1; 7596 u64 reserved_0_62 : 63; 7597 } s; 7598 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn73xx; 7599 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn78xx; 7600 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cn78xxp1; 7601 struct cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_s cnf75xx; 7602 }; 7603 7604 typedef union cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq3_ecc_dbe_sts_cmb0_t; 7605 7606 /** 7607 * cvmx_pko_pse_sq3_ecc_sbe_sts0 7608 */ 7609 union cvmx_pko_pse_sq3_ecc_sbe_sts0 { 7610 u64 u64; 7611 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s { 7612 u64 sq_pt_ram_sbe : 1; 7613 u64 sq_nt_ram_sbe : 1; 7614 u64 rt_ram_sbe : 1; 7615 u64 tw3_cmd_fifo_ram_sbe : 1; 7616 u64 tw2_cmd_fifo_ram_sbe : 1; 7617 u64 tw1_cmd_fifo_ram_sbe : 1; 7618 u64 tw0_cmd_fifo_ram_sbe : 1; 7619 u64 tp3_sram_sbe : 1; 7620 u64 tp2_sram_sbe : 1; 7621 u64 tp1_sram_sbe : 1; 7622 u64 tp0_sram_sbe : 1; 7623 u64 sts3_ram_sbe : 1; 7624 u64 sts2_ram_sbe : 1; 7625 u64 sts1_ram_sbe : 1; 7626 u64 sts0_ram_sbe : 1; 7627 u64 std3_ram_sbe : 1; 7628 u64 std2_ram_sbe : 1; 7629 u64 std1_ram_sbe : 1; 7630 u64 std0_ram_sbe : 1; 7631 u64 wt_ram_sbe : 1; 7632 u64 sc_ram_sbe : 1; 7633 u64 reserved_0_42 : 43; 7634 } s; 7635 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_cn73xx { 7636 u64 sq_pt_ram_sbe : 1; 7637 u64 sq_nt_ram_sbe : 1; 7638 u64 rt_ram_sbe : 1; 7639 u64 reserved_58_60 : 3; 7640 u64 tw0_cmd_fifo_ram_sbe : 1; 7641 u64 reserved_54_56 : 3; 7642 u64 tp0_sram_sbe : 1; 7643 u64 reserved_50_52 : 3; 7644 u64 sts0_ram_sbe : 1; 7645 u64 reserved_46_48 : 3; 7646 u64 std0_ram_sbe : 1; 7647 u64 wt_ram_sbe : 1; 7648 u64 sc_ram_sbe : 1; 7649 u64 reserved_0_42 : 43; 7650 } cn73xx; 7651 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s cn78xx; 7652 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_s cn78xxp1; 7653 struct cvmx_pko_pse_sq3_ecc_sbe_sts0_cn73xx cnf75xx; 7654 }; 7655 7656 typedef union cvmx_pko_pse_sq3_ecc_sbe_sts0 cvmx_pko_pse_sq3_ecc_sbe_sts0_t; 7657 7658 /** 7659 * cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0 7660 */ 7661 union cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0 { 7662 u64 u64; 7663 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s { 7664 u64 pse_sq3_sbe_cmb0 : 1; 7665 u64 reserved_0_62 : 63; 7666 } s; 7667 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn73xx; 7668 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn78xx; 7669 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cn78xxp1; 7670 struct cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_s cnf75xx; 7671 }; 7672 7673 typedef union cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq3_ecc_sbe_sts_cmb0_t; 7674 7675 /** 7676 * cvmx_pko_pse_sq4_bist_status 7677 * 7678 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 7679 * 7680 */ 7681 union cvmx_pko_pse_sq4_bist_status { 7682 u64 u64; 7683 struct cvmx_pko_pse_sq4_bist_status_s { 7684 u64 reserved_29_63 : 35; 7685 u64 sc_sram : 1; 7686 u64 reserved_23_27 : 5; 7687 u64 tp3_sram : 1; 7688 u64 tp2_sram : 1; 7689 u64 tp1_sram : 1; 7690 u64 tp0_sram : 1; 7691 u64 reserved_18_18 : 1; 7692 u64 rt_sram : 1; 7693 u64 reserved_15_16 : 2; 7694 u64 tw3_cmd_fifo : 1; 7695 u64 reserved_12_13 : 2; 7696 u64 tw2_cmd_fifo : 1; 7697 u64 reserved_9_10 : 2; 7698 u64 tw1_cmd_fifo : 1; 7699 u64 std_sram : 1; 7700 u64 sts_sram : 1; 7701 u64 tw0_cmd_fifo : 1; 7702 u64 reserved_3_4 : 2; 7703 u64 nt_sram : 1; 7704 u64 pt_sram : 1; 7705 u64 wt_sram : 1; 7706 } s; 7707 struct cvmx_pko_pse_sq4_bist_status_s cn78xx; 7708 struct cvmx_pko_pse_sq4_bist_status_s cn78xxp1; 7709 }; 7710 7711 typedef union cvmx_pko_pse_sq4_bist_status cvmx_pko_pse_sq4_bist_status_t; 7712 7713 /** 7714 * cvmx_pko_pse_sq4_ecc_ctl0 7715 */ 7716 union cvmx_pko_pse_sq4_ecc_ctl0 { 7717 u64 u64; 7718 struct cvmx_pko_pse_sq4_ecc_ctl0_s { 7719 u64 sq_pt_ram_flip : 2; 7720 u64 sq_pt_ram_cdis : 1; 7721 u64 sq_nt_ram_flip : 2; 7722 u64 sq_nt_ram_cdis : 1; 7723 u64 rt_ram_flip : 2; 7724 u64 rt_ram_cdis : 1; 7725 u64 tw3_cmd_fifo_ram_flip : 2; 7726 u64 tw3_cmd_fifo_ram_cdis : 1; 7727 u64 tw2_cmd_fifo_ram_flip : 2; 7728 u64 tw2_cmd_fifo_ram_cdis : 1; 7729 u64 tw1_cmd_fifo_ram_flip : 2; 7730 u64 tw1_cmd_fifo_ram_cdis : 1; 7731 u64 tw0_cmd_fifo_ram_flip : 2; 7732 u64 tw0_cmd_fifo_ram_cdis : 1; 7733 u64 tp3_sram_flip : 2; 7734 u64 tp3_sram_cdis : 1; 7735 u64 tp2_sram_flip : 2; 7736 u64 tp2_sram_cdis : 1; 7737 u64 tp1_sram_flip : 2; 7738 u64 tp1_sram_cdis : 1; 7739 u64 tp0_sram_flip : 2; 7740 u64 tp0_sram_cdis : 1; 7741 u64 sts3_ram_flip : 2; 7742 u64 sts3_ram_cdis : 1; 7743 u64 sts2_ram_flip : 2; 7744 u64 sts2_ram_cdis : 1; 7745 u64 sts1_ram_flip : 2; 7746 u64 sts1_ram_cdis : 1; 7747 u64 sts0_ram_flip : 2; 7748 u64 sts0_ram_cdis : 1; 7749 u64 std3_ram_flip : 2; 7750 u64 std3_ram_cdis : 1; 7751 u64 std2_ram_flip : 2; 7752 u64 std2_ram_cdis : 1; 7753 u64 std1_ram_flip : 2; 7754 u64 std1_ram_cdis : 1; 7755 u64 std0_ram_flip : 2; 7756 u64 std0_ram_cdis : 1; 7757 u64 wt_ram_flip : 2; 7758 u64 wt_ram_cdis : 1; 7759 u64 sc_ram_flip : 2; 7760 u64 sc_ram_cdis : 1; 7761 u64 reserved_0_0 : 1; 7762 } s; 7763 struct cvmx_pko_pse_sq4_ecc_ctl0_s cn78xx; 7764 struct cvmx_pko_pse_sq4_ecc_ctl0_s cn78xxp1; 7765 }; 7766 7767 typedef union cvmx_pko_pse_sq4_ecc_ctl0 cvmx_pko_pse_sq4_ecc_ctl0_t; 7768 7769 /** 7770 * cvmx_pko_pse_sq4_ecc_dbe_sts0 7771 */ 7772 union cvmx_pko_pse_sq4_ecc_dbe_sts0 { 7773 u64 u64; 7774 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s { 7775 u64 sq_pt_ram_dbe : 1; 7776 u64 sq_nt_ram_dbe : 1; 7777 u64 rt_ram_dbe : 1; 7778 u64 tw3_cmd_fifo_ram_dbe : 1; 7779 u64 tw2_cmd_fifo_ram_dbe : 1; 7780 u64 tw1_cmd_fifo_ram_dbe : 1; 7781 u64 tw0_cmd_fifo_ram_dbe : 1; 7782 u64 tp3_sram_dbe : 1; 7783 u64 tp2_sram_dbe : 1; 7784 u64 tp1_sram_dbe : 1; 7785 u64 tp0_sram_dbe : 1; 7786 u64 sts3_ram_dbe : 1; 7787 u64 sts2_ram_dbe : 1; 7788 u64 sts1_ram_dbe : 1; 7789 u64 sts0_ram_dbe : 1; 7790 u64 std3_ram_dbe : 1; 7791 u64 std2_ram_dbe : 1; 7792 u64 std1_ram_dbe : 1; 7793 u64 std0_ram_dbe : 1; 7794 u64 wt_ram_dbe : 1; 7795 u64 sc_ram_dbe : 1; 7796 u64 reserved_0_42 : 43; 7797 } s; 7798 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s cn78xx; 7799 struct cvmx_pko_pse_sq4_ecc_dbe_sts0_s cn78xxp1; 7800 }; 7801 7802 typedef union cvmx_pko_pse_sq4_ecc_dbe_sts0 cvmx_pko_pse_sq4_ecc_dbe_sts0_t; 7803 7804 /** 7805 * cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0 7806 */ 7807 union cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0 { 7808 u64 u64; 7809 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s { 7810 u64 pse_sq4_dbe_cmb0 : 1; 7811 u64 reserved_0_62 : 63; 7812 } s; 7813 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s cn78xx; 7814 struct cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_s cn78xxp1; 7815 }; 7816 7817 typedef union cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq4_ecc_dbe_sts_cmb0_t; 7818 7819 /** 7820 * cvmx_pko_pse_sq4_ecc_sbe_sts0 7821 */ 7822 union cvmx_pko_pse_sq4_ecc_sbe_sts0 { 7823 u64 u64; 7824 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s { 7825 u64 sq_pt_ram_sbe : 1; 7826 u64 sq_nt_ram_sbe : 1; 7827 u64 rt_ram_sbe : 1; 7828 u64 tw3_cmd_fifo_ram_sbe : 1; 7829 u64 tw2_cmd_fifo_ram_sbe : 1; 7830 u64 tw1_cmd_fifo_ram_sbe : 1; 7831 u64 tw0_cmd_fifo_ram_sbe : 1; 7832 u64 tp3_sram_sbe : 1; 7833 u64 tp2_sram_sbe : 1; 7834 u64 tp1_sram_sbe : 1; 7835 u64 tp0_sram_sbe : 1; 7836 u64 sts3_ram_sbe : 1; 7837 u64 sts2_ram_sbe : 1; 7838 u64 sts1_ram_sbe : 1; 7839 u64 sts0_ram_sbe : 1; 7840 u64 std3_ram_sbe : 1; 7841 u64 std2_ram_sbe : 1; 7842 u64 std1_ram_sbe : 1; 7843 u64 std0_ram_sbe : 1; 7844 u64 wt_ram_sbe : 1; 7845 u64 sc_ram_sbe : 1; 7846 u64 reserved_0_42 : 43; 7847 } s; 7848 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s cn78xx; 7849 struct cvmx_pko_pse_sq4_ecc_sbe_sts0_s cn78xxp1; 7850 }; 7851 7852 typedef union cvmx_pko_pse_sq4_ecc_sbe_sts0 cvmx_pko_pse_sq4_ecc_sbe_sts0_t; 7853 7854 /** 7855 * cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0 7856 */ 7857 union cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0 { 7858 u64 u64; 7859 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s { 7860 u64 pse_sq4_sbe_cmb0 : 1; 7861 u64 reserved_0_62 : 63; 7862 } s; 7863 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s cn78xx; 7864 struct cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_s cn78xxp1; 7865 }; 7866 7867 typedef union cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq4_ecc_sbe_sts_cmb0_t; 7868 7869 /** 7870 * cvmx_pko_pse_sq5_bist_status 7871 * 7872 * Each bit is the BIST result of an individual memory (per bit, 0 = pass and 1 = fail). 7873 * 7874 */ 7875 union cvmx_pko_pse_sq5_bist_status { 7876 u64 u64; 7877 struct cvmx_pko_pse_sq5_bist_status_s { 7878 u64 reserved_29_63 : 35; 7879 u64 sc_sram : 1; 7880 u64 reserved_23_27 : 5; 7881 u64 tp3_sram : 1; 7882 u64 tp2_sram : 1; 7883 u64 tp1_sram : 1; 7884 u64 tp0_sram : 1; 7885 u64 reserved_18_18 : 1; 7886 u64 rt_sram : 1; 7887 u64 reserved_15_16 : 2; 7888 u64 tw3_cmd_fifo : 1; 7889 u64 reserved_12_13 : 2; 7890 u64 tw2_cmd_fifo : 1; 7891 u64 reserved_9_10 : 2; 7892 u64 tw1_cmd_fifo : 1; 7893 u64 std_sram : 1; 7894 u64 sts_sram : 1; 7895 u64 tw0_cmd_fifo : 1; 7896 u64 reserved_3_4 : 2; 7897 u64 nt_sram : 1; 7898 u64 pt_sram : 1; 7899 u64 wt_sram : 1; 7900 } s; 7901 struct cvmx_pko_pse_sq5_bist_status_s cn78xx; 7902 struct cvmx_pko_pse_sq5_bist_status_s cn78xxp1; 7903 }; 7904 7905 typedef union cvmx_pko_pse_sq5_bist_status cvmx_pko_pse_sq5_bist_status_t; 7906 7907 /** 7908 * cvmx_pko_pse_sq5_ecc_ctl0 7909 */ 7910 union cvmx_pko_pse_sq5_ecc_ctl0 { 7911 u64 u64; 7912 struct cvmx_pko_pse_sq5_ecc_ctl0_s { 7913 u64 sq_pt_ram_flip : 2; 7914 u64 sq_pt_ram_cdis : 1; 7915 u64 sq_nt_ram_flip : 2; 7916 u64 sq_nt_ram_cdis : 1; 7917 u64 rt_ram_flip : 2; 7918 u64 rt_ram_cdis : 1; 7919 u64 tw3_cmd_fifo_ram_flip : 2; 7920 u64 tw3_cmd_fifo_ram_cdis : 1; 7921 u64 tw2_cmd_fifo_ram_flip : 2; 7922 u64 tw2_cmd_fifo_ram_cdis : 1; 7923 u64 tw1_cmd_fifo_ram_flip : 2; 7924 u64 tw1_cmd_fifo_ram_cdis : 1; 7925 u64 tw0_cmd_fifo_ram_flip : 2; 7926 u64 tw0_cmd_fifo_ram_cdis : 1; 7927 u64 tp3_sram_flip : 2; 7928 u64 tp3_sram_cdis : 1; 7929 u64 tp2_sram_flip : 2; 7930 u64 tp2_sram_cdis : 1; 7931 u64 tp1_sram_flip : 2; 7932 u64 tp1_sram_cdis : 1; 7933 u64 tp0_sram_flip : 2; 7934 u64 tp0_sram_cdis : 1; 7935 u64 sts3_ram_flip : 2; 7936 u64 sts3_ram_cdis : 1; 7937 u64 sts2_ram_flip : 2; 7938 u64 sts2_ram_cdis : 1; 7939 u64 sts1_ram_flip : 2; 7940 u64 sts1_ram_cdis : 1; 7941 u64 sts0_ram_flip : 2; 7942 u64 sts0_ram_cdis : 1; 7943 u64 std3_ram_flip : 2; 7944 u64 std3_ram_cdis : 1; 7945 u64 std2_ram_flip : 2; 7946 u64 std2_ram_cdis : 1; 7947 u64 std1_ram_flip : 2; 7948 u64 std1_ram_cdis : 1; 7949 u64 std0_ram_flip : 2; 7950 u64 std0_ram_cdis : 1; 7951 u64 wt_ram_flip : 2; 7952 u64 wt_ram_cdis : 1; 7953 u64 sc_ram_flip : 2; 7954 u64 sc_ram_cdis : 1; 7955 u64 reserved_0_0 : 1; 7956 } s; 7957 struct cvmx_pko_pse_sq5_ecc_ctl0_s cn78xx; 7958 struct cvmx_pko_pse_sq5_ecc_ctl0_s cn78xxp1; 7959 }; 7960 7961 typedef union cvmx_pko_pse_sq5_ecc_ctl0 cvmx_pko_pse_sq5_ecc_ctl0_t; 7962 7963 /** 7964 * cvmx_pko_pse_sq5_ecc_dbe_sts0 7965 */ 7966 union cvmx_pko_pse_sq5_ecc_dbe_sts0 { 7967 u64 u64; 7968 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s { 7969 u64 sq_pt_ram_dbe : 1; 7970 u64 sq_nt_ram_dbe : 1; 7971 u64 rt_ram_dbe : 1; 7972 u64 tw3_cmd_fifo_ram_dbe : 1; 7973 u64 tw2_cmd_fifo_ram_dbe : 1; 7974 u64 tw1_cmd_fifo_ram_dbe : 1; 7975 u64 tw0_cmd_fifo_ram_dbe : 1; 7976 u64 tp3_sram_dbe : 1; 7977 u64 tp2_sram_dbe : 1; 7978 u64 tp1_sram_dbe : 1; 7979 u64 tp0_sram_dbe : 1; 7980 u64 sts3_ram_dbe : 1; 7981 u64 sts2_ram_dbe : 1; 7982 u64 sts1_ram_dbe : 1; 7983 u64 sts0_ram_dbe : 1; 7984 u64 std3_ram_dbe : 1; 7985 u64 std2_ram_dbe : 1; 7986 u64 std1_ram_dbe : 1; 7987 u64 std0_ram_dbe : 1; 7988 u64 wt_ram_dbe : 1; 7989 u64 sc_ram_dbe : 1; 7990 u64 reserved_0_42 : 43; 7991 } s; 7992 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s cn78xx; 7993 struct cvmx_pko_pse_sq5_ecc_dbe_sts0_s cn78xxp1; 7994 }; 7995 7996 typedef union cvmx_pko_pse_sq5_ecc_dbe_sts0 cvmx_pko_pse_sq5_ecc_dbe_sts0_t; 7997 7998 /** 7999 * cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0 8000 */ 8001 union cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0 { 8002 u64 u64; 8003 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s { 8004 u64 pse_sq5_dbe_cmb0 : 1; 8005 u64 reserved_0_62 : 63; 8006 } s; 8007 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s cn78xx; 8008 struct cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_s cn78xxp1; 8009 }; 8010 8011 typedef union cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0 cvmx_pko_pse_sq5_ecc_dbe_sts_cmb0_t; 8012 8013 /** 8014 * cvmx_pko_pse_sq5_ecc_sbe_sts0 8015 */ 8016 union cvmx_pko_pse_sq5_ecc_sbe_sts0 { 8017 u64 u64; 8018 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s { 8019 u64 sq_pt_ram_sbe : 1; 8020 u64 sq_nt_ram_sbe : 1; 8021 u64 rt_ram_sbe : 1; 8022 u64 tw3_cmd_fifo_ram_sbe : 1; 8023 u64 tw2_cmd_fifo_ram_sbe : 1; 8024 u64 tw1_cmd_fifo_ram_sbe : 1; 8025 u64 tw0_cmd_fifo_ram_sbe : 1; 8026 u64 tp3_sram_sbe : 1; 8027 u64 tp2_sram_sbe : 1; 8028 u64 tp1_sram_sbe : 1; 8029 u64 tp0_sram_sbe : 1; 8030 u64 sts3_ram_sbe : 1; 8031 u64 sts2_ram_sbe : 1; 8032 u64 sts1_ram_sbe : 1; 8033 u64 sts0_ram_sbe : 1; 8034 u64 std3_ram_sbe : 1; 8035 u64 std2_ram_sbe : 1; 8036 u64 std1_ram_sbe : 1; 8037 u64 std0_ram_sbe : 1; 8038 u64 wt_ram_sbe : 1; 8039 u64 sc_ram_sbe : 1; 8040 u64 reserved_0_42 : 43; 8041 } s; 8042 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s cn78xx; 8043 struct cvmx_pko_pse_sq5_ecc_sbe_sts0_s cn78xxp1; 8044 }; 8045 8046 typedef union cvmx_pko_pse_sq5_ecc_sbe_sts0 cvmx_pko_pse_sq5_ecc_sbe_sts0_t; 8047 8048 /** 8049 * cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0 8050 */ 8051 union cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0 { 8052 u64 u64; 8053 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s { 8054 u64 pse_sq5_sbe_cmb0 : 1; 8055 u64 reserved_0_62 : 63; 8056 } s; 8057 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s cn78xx; 8058 struct cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_s cn78xxp1; 8059 }; 8060 8061 typedef union cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0 cvmx_pko_pse_sq5_ecc_sbe_sts_cmb0_t; 8062 8063 /** 8064 * cvmx_pko_ptf#_status 8065 */ 8066 union cvmx_pko_ptfx_status { 8067 u64 u64; 8068 struct cvmx_pko_ptfx_status_s { 8069 u64 reserved_30_63 : 34; 8070 u64 tx_fifo_pkt_credit_cnt : 10; 8071 u64 total_in_flight_cnt : 8; 8072 u64 in_flight_cnt : 7; 8073 u64 mac_num : 5; 8074 } s; 8075 struct cvmx_pko_ptfx_status_s cn73xx; 8076 struct cvmx_pko_ptfx_status_s cn78xx; 8077 struct cvmx_pko_ptfx_status_s cn78xxp1; 8078 struct cvmx_pko_ptfx_status_s cnf75xx; 8079 }; 8080 8081 typedef union cvmx_pko_ptfx_status cvmx_pko_ptfx_status_t; 8082 8083 /** 8084 * cvmx_pko_ptf_iobp_cfg 8085 */ 8086 union cvmx_pko_ptf_iobp_cfg { 8087 u64 u64; 8088 struct cvmx_pko_ptf_iobp_cfg_s { 8089 u64 reserved_44_63 : 20; 8090 u64 iobp1_ds_opt : 1; 8091 u64 iobp0_l2_allocate : 1; 8092 u64 iobp1_magic_addr : 35; 8093 u64 max_read_size : 7; 8094 } s; 8095 struct cvmx_pko_ptf_iobp_cfg_s cn73xx; 8096 struct cvmx_pko_ptf_iobp_cfg_s cn78xx; 8097 struct cvmx_pko_ptf_iobp_cfg_s cn78xxp1; 8098 struct cvmx_pko_ptf_iobp_cfg_s cnf75xx; 8099 }; 8100 8101 typedef union cvmx_pko_ptf_iobp_cfg cvmx_pko_ptf_iobp_cfg_t; 8102 8103 /** 8104 * cvmx_pko_ptgf#_cfg 8105 * 8106 * This register configures a PKO TX FIFO group. PKO supports up to 17 independent 8107 * TX FIFOs, where 0-15 are physical and 16 is Virtual/NULL. (PKO drops packets 8108 * targeting the NULL FIFO, returning their buffers to the FPA.) PKO puts each 8109 * FIFO into one of five groups: 8110 * 8111 * <pre> 8112 * CSR Name FIFO's in FIFO Group 8113 * ------------------------------------ 8114 * PKO_PTGF0_CFG 0, 1, 2, 3 8115 * PKO_PTGF1_CFG 4, 5, 6, 7 8116 * PKO_PTGF2_CFG 8, 9, 10, 11 8117 * PKO_PTGF3_CFG 12, 13, 14, 15 8118 * PKO_PTGF4_CFG Virtual/NULL 8119 * </pre> 8120 */ 8121 union cvmx_pko_ptgfx_cfg { 8122 u64 u64; 8123 struct cvmx_pko_ptgfx_cfg_s { 8124 u64 reserved_7_63 : 57; 8125 u64 reset : 1; 8126 u64 rate : 3; 8127 u64 size : 3; 8128 } s; 8129 struct cvmx_pko_ptgfx_cfg_cn73xx { 8130 u64 reserved_7_63 : 57; 8131 u64 reset : 1; 8132 u64 reserved_5_5 : 1; 8133 u64 rate : 2; 8134 u64 size : 3; 8135 } cn73xx; 8136 struct cvmx_pko_ptgfx_cfg_s cn78xx; 8137 struct cvmx_pko_ptgfx_cfg_s cn78xxp1; 8138 struct cvmx_pko_ptgfx_cfg_cn73xx cnf75xx; 8139 }; 8140 8141 typedef union cvmx_pko_ptgfx_cfg cvmx_pko_ptgfx_cfg_t; 8142 8143 /** 8144 * cvmx_pko_reg_bist_result 8145 * 8146 * Notes: 8147 * Access to the internal BiST results 8148 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 8149 */ 8150 union cvmx_pko_reg_bist_result { 8151 u64 u64; 8152 struct cvmx_pko_reg_bist_result_s { 8153 u64 reserved_0_63 : 64; 8154 } s; 8155 struct cvmx_pko_reg_bist_result_cn30xx { 8156 u64 reserved_27_63 : 37; 8157 u64 psb2 : 5; 8158 u64 count : 1; 8159 u64 rif : 1; 8160 u64 wif : 1; 8161 u64 ncb : 1; 8162 u64 out : 1; 8163 u64 crc : 1; 8164 u64 chk : 1; 8165 u64 qsb : 2; 8166 u64 qcb : 2; 8167 u64 pdb : 4; 8168 u64 psb : 7; 8169 } cn30xx; 8170 struct cvmx_pko_reg_bist_result_cn30xx cn31xx; 8171 struct cvmx_pko_reg_bist_result_cn30xx cn38xx; 8172 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; 8173 struct cvmx_pko_reg_bist_result_cn50xx { 8174 u64 reserved_33_63 : 31; 8175 u64 csr : 1; 8176 u64 iob : 1; 8177 u64 out_crc : 1; 8178 u64 out_ctl : 3; 8179 u64 out_sta : 1; 8180 u64 out_wif : 1; 8181 u64 prt_chk : 3; 8182 u64 prt_nxt : 1; 8183 u64 prt_psb : 6; 8184 u64 ncb_inb : 2; 8185 u64 prt_qcb : 2; 8186 u64 prt_qsb : 3; 8187 u64 dat_dat : 4; 8188 u64 dat_ptr : 4; 8189 } cn50xx; 8190 struct cvmx_pko_reg_bist_result_cn52xx { 8191 u64 reserved_35_63 : 29; 8192 u64 csr : 1; 8193 u64 iob : 1; 8194 u64 out_dat : 1; 8195 u64 out_ctl : 3; 8196 u64 out_sta : 1; 8197 u64 out_wif : 1; 8198 u64 prt_chk : 3; 8199 u64 prt_nxt : 1; 8200 u64 prt_psb : 8; 8201 u64 ncb_inb : 2; 8202 u64 prt_qcb : 2; 8203 u64 prt_qsb : 3; 8204 u64 prt_ctl : 2; 8205 u64 dat_dat : 2; 8206 u64 dat_ptr : 4; 8207 } cn52xx; 8208 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; 8209 struct cvmx_pko_reg_bist_result_cn52xx cn56xx; 8210 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; 8211 struct cvmx_pko_reg_bist_result_cn50xx cn58xx; 8212 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; 8213 struct cvmx_pko_reg_bist_result_cn52xx cn61xx; 8214 struct cvmx_pko_reg_bist_result_cn52xx cn63xx; 8215 struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1; 8216 struct cvmx_pko_reg_bist_result_cn52xx cn66xx; 8217 struct cvmx_pko_reg_bist_result_cn68xx { 8218 u64 reserved_36_63 : 28; 8219 u64 crc : 1; 8220 u64 csr : 1; 8221 u64 iob : 1; 8222 u64 out_dat : 1; 8223 u64 reserved_31_31 : 1; 8224 u64 out_ctl : 2; 8225 u64 out_sta : 1; 8226 u64 out_wif : 1; 8227 u64 prt_chk : 3; 8228 u64 prt_nxt : 1; 8229 u64 prt_psb7 : 1; 8230 u64 reserved_21_21 : 1; 8231 u64 prt_psb : 6; 8232 u64 ncb_inb : 2; 8233 u64 prt_qcb : 2; 8234 u64 prt_qsb : 3; 8235 u64 prt_ctl : 2; 8236 u64 dat_dat : 2; 8237 u64 dat_ptr : 4; 8238 } cn68xx; 8239 struct cvmx_pko_reg_bist_result_cn68xxp1 { 8240 u64 reserved_35_63 : 29; 8241 u64 csr : 1; 8242 u64 iob : 1; 8243 u64 out_dat : 1; 8244 u64 reserved_31_31 : 1; 8245 u64 out_ctl : 2; 8246 u64 out_sta : 1; 8247 u64 out_wif : 1; 8248 u64 prt_chk : 3; 8249 u64 prt_nxt : 1; 8250 u64 prt_psb7 : 1; 8251 u64 reserved_21_21 : 1; 8252 u64 prt_psb : 6; 8253 u64 ncb_inb : 2; 8254 u64 prt_qcb : 2; 8255 u64 prt_qsb : 3; 8256 u64 prt_ctl : 2; 8257 u64 dat_dat : 2; 8258 u64 dat_ptr : 4; 8259 } cn68xxp1; 8260 struct cvmx_pko_reg_bist_result_cn70xx { 8261 u64 reserved_30_63 : 34; 8262 u64 csr : 1; 8263 u64 iob : 1; 8264 u64 out_dat : 1; 8265 u64 out_ctl : 1; 8266 u64 out_sta : 1; 8267 u64 out_wif : 1; 8268 u64 prt_chk : 3; 8269 u64 prt_nxt : 1; 8270 u64 prt_psb : 8; 8271 u64 ncb_inb : 1; 8272 u64 prt_qcb : 1; 8273 u64 prt_qsb : 2; 8274 u64 prt_ctl : 2; 8275 u64 dat_dat : 2; 8276 u64 dat_ptr : 4; 8277 } cn70xx; 8278 struct cvmx_pko_reg_bist_result_cn70xx cn70xxp1; 8279 struct cvmx_pko_reg_bist_result_cn52xx cnf71xx; 8280 }; 8281 8282 typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t; 8283 8284 /** 8285 * cvmx_pko_reg_cmd_buf 8286 * 8287 * Notes: 8288 * Sets the command buffer parameters 8289 * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free 8290 * lists to be used when freeing command buffer segments. 8291 */ 8292 union cvmx_pko_reg_cmd_buf { 8293 u64 u64; 8294 struct cvmx_pko_reg_cmd_buf_s { 8295 u64 reserved_23_63 : 41; 8296 u64 pool : 3; 8297 u64 reserved_13_19 : 7; 8298 u64 size : 13; 8299 } s; 8300 struct cvmx_pko_reg_cmd_buf_s cn30xx; 8301 struct cvmx_pko_reg_cmd_buf_s cn31xx; 8302 struct cvmx_pko_reg_cmd_buf_s cn38xx; 8303 struct cvmx_pko_reg_cmd_buf_s cn38xxp2; 8304 struct cvmx_pko_reg_cmd_buf_s cn50xx; 8305 struct cvmx_pko_reg_cmd_buf_s cn52xx; 8306 struct cvmx_pko_reg_cmd_buf_s cn52xxp1; 8307 struct cvmx_pko_reg_cmd_buf_s cn56xx; 8308 struct cvmx_pko_reg_cmd_buf_s cn56xxp1; 8309 struct cvmx_pko_reg_cmd_buf_s cn58xx; 8310 struct cvmx_pko_reg_cmd_buf_s cn58xxp1; 8311 struct cvmx_pko_reg_cmd_buf_s cn61xx; 8312 struct cvmx_pko_reg_cmd_buf_s cn63xx; 8313 struct cvmx_pko_reg_cmd_buf_s cn63xxp1; 8314 struct cvmx_pko_reg_cmd_buf_s cn66xx; 8315 struct cvmx_pko_reg_cmd_buf_s cn68xx; 8316 struct cvmx_pko_reg_cmd_buf_s cn68xxp1; 8317 struct cvmx_pko_reg_cmd_buf_cn70xx { 8318 u64 reserved_23_63 : 41; 8319 u64 pool : 3; 8320 u64 reserved_19_13 : 7; 8321 u64 size : 13; 8322 } cn70xx; 8323 struct cvmx_pko_reg_cmd_buf_cn70xx cn70xxp1; 8324 struct cvmx_pko_reg_cmd_buf_s cnf71xx; 8325 }; 8326 8327 typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t; 8328 8329 /** 8330 * cvmx_pko_reg_crc_ctl# 8331 * 8332 * Notes: 8333 * Controls datapath reflection when calculating CRC 8334 * 8335 */ 8336 union cvmx_pko_reg_crc_ctlx { 8337 u64 u64; 8338 struct cvmx_pko_reg_crc_ctlx_s { 8339 u64 reserved_2_63 : 62; 8340 u64 invres : 1; 8341 u64 refin : 1; 8342 } s; 8343 struct cvmx_pko_reg_crc_ctlx_s cn38xx; 8344 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; 8345 struct cvmx_pko_reg_crc_ctlx_s cn58xx; 8346 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; 8347 }; 8348 8349 typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t; 8350 8351 /** 8352 * cvmx_pko_reg_crc_enable 8353 * 8354 * Notes: 8355 * Enables CRC for the GMX ports. 8356 * 8357 */ 8358 union cvmx_pko_reg_crc_enable { 8359 u64 u64; 8360 struct cvmx_pko_reg_crc_enable_s { 8361 u64 reserved_32_63 : 32; 8362 u64 enable : 32; 8363 } s; 8364 struct cvmx_pko_reg_crc_enable_s cn38xx; 8365 struct cvmx_pko_reg_crc_enable_s cn38xxp2; 8366 struct cvmx_pko_reg_crc_enable_s cn58xx; 8367 struct cvmx_pko_reg_crc_enable_s cn58xxp1; 8368 }; 8369 8370 typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t; 8371 8372 /** 8373 * cvmx_pko_reg_crc_iv# 8374 * 8375 * Notes: 8376 * Determines the IV used by the CRC algorithm 8377 * * PKO_CRC_IV 8378 * PKO_CRC_IV controls the initial state of the CRC algorithm. Octane can 8379 * support a wide range of CRC algorithms and as such, the IV must be 8380 * carefully constructed to meet the specific algorithm. The code below 8381 * determines the value to program into Octane based on the algorthim's IV 8382 * and width. In the case of Octane, the width should always be 32. 8383 * 8384 * PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for 8385 * ports 16-31. 8386 * 8387 * @verbatim 8388 * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w) 8389 * [ 8390 * int i; 8391 * int doit; 8392 * unsigned int current_val = algorithm_iv; 8393 * 8394 * for(i = 0; i < w; i++) [ 8395 * doit = current_val & 0x1; 8396 * 8397 * if(doit) current_val ^= poly; 8398 * assert(!(current_val & 0x1)); 8399 * 8400 * current_val = (current_val >> 1) | (doit << (w-1)); 8401 * ] 8402 * 8403 * return current_val; 8404 * ] 8405 * @endverbatim 8406 */ 8407 union cvmx_pko_reg_crc_ivx { 8408 u64 u64; 8409 struct cvmx_pko_reg_crc_ivx_s { 8410 u64 reserved_32_63 : 32; 8411 u64 iv : 32; 8412 } s; 8413 struct cvmx_pko_reg_crc_ivx_s cn38xx; 8414 struct cvmx_pko_reg_crc_ivx_s cn38xxp2; 8415 struct cvmx_pko_reg_crc_ivx_s cn58xx; 8416 struct cvmx_pko_reg_crc_ivx_s cn58xxp1; 8417 }; 8418 8419 typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t; 8420 8421 /** 8422 * cvmx_pko_reg_debug0 8423 * 8424 * Notes: 8425 * Note that this CSR is present only in chip revisions beginning with pass2. 8426 * 8427 */ 8428 union cvmx_pko_reg_debug0 { 8429 u64 u64; 8430 struct cvmx_pko_reg_debug0_s { 8431 u64 asserts : 64; 8432 } s; 8433 struct cvmx_pko_reg_debug0_cn30xx { 8434 u64 reserved_17_63 : 47; 8435 u64 asserts : 17; 8436 } cn30xx; 8437 struct cvmx_pko_reg_debug0_cn30xx cn31xx; 8438 struct cvmx_pko_reg_debug0_cn30xx cn38xx; 8439 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; 8440 struct cvmx_pko_reg_debug0_s cn50xx; 8441 struct cvmx_pko_reg_debug0_s cn52xx; 8442 struct cvmx_pko_reg_debug0_s cn52xxp1; 8443 struct cvmx_pko_reg_debug0_s cn56xx; 8444 struct cvmx_pko_reg_debug0_s cn56xxp1; 8445 struct cvmx_pko_reg_debug0_s cn58xx; 8446 struct cvmx_pko_reg_debug0_s cn58xxp1; 8447 struct cvmx_pko_reg_debug0_s cn61xx; 8448 struct cvmx_pko_reg_debug0_s cn63xx; 8449 struct cvmx_pko_reg_debug0_s cn63xxp1; 8450 struct cvmx_pko_reg_debug0_s cn66xx; 8451 struct cvmx_pko_reg_debug0_s cn68xx; 8452 struct cvmx_pko_reg_debug0_s cn68xxp1; 8453 struct cvmx_pko_reg_debug0_s cn70xx; 8454 struct cvmx_pko_reg_debug0_s cn70xxp1; 8455 struct cvmx_pko_reg_debug0_s cnf71xx; 8456 }; 8457 8458 typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t; 8459 8460 /** 8461 * cvmx_pko_reg_debug1 8462 */ 8463 union cvmx_pko_reg_debug1 { 8464 u64 u64; 8465 struct cvmx_pko_reg_debug1_s { 8466 u64 asserts : 64; 8467 } s; 8468 struct cvmx_pko_reg_debug1_s cn50xx; 8469 struct cvmx_pko_reg_debug1_s cn52xx; 8470 struct cvmx_pko_reg_debug1_s cn52xxp1; 8471 struct cvmx_pko_reg_debug1_s cn56xx; 8472 struct cvmx_pko_reg_debug1_s cn56xxp1; 8473 struct cvmx_pko_reg_debug1_s cn58xx; 8474 struct cvmx_pko_reg_debug1_s cn58xxp1; 8475 struct cvmx_pko_reg_debug1_s cn61xx; 8476 struct cvmx_pko_reg_debug1_s cn63xx; 8477 struct cvmx_pko_reg_debug1_s cn63xxp1; 8478 struct cvmx_pko_reg_debug1_s cn66xx; 8479 struct cvmx_pko_reg_debug1_s cn68xx; 8480 struct cvmx_pko_reg_debug1_s cn68xxp1; 8481 struct cvmx_pko_reg_debug1_s cn70xx; 8482 struct cvmx_pko_reg_debug1_s cn70xxp1; 8483 struct cvmx_pko_reg_debug1_s cnf71xx; 8484 }; 8485 8486 typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t; 8487 8488 /** 8489 * cvmx_pko_reg_debug2 8490 */ 8491 union cvmx_pko_reg_debug2 { 8492 u64 u64; 8493 struct cvmx_pko_reg_debug2_s { 8494 u64 asserts : 64; 8495 } s; 8496 struct cvmx_pko_reg_debug2_s cn50xx; 8497 struct cvmx_pko_reg_debug2_s cn52xx; 8498 struct cvmx_pko_reg_debug2_s cn52xxp1; 8499 struct cvmx_pko_reg_debug2_s cn56xx; 8500 struct cvmx_pko_reg_debug2_s cn56xxp1; 8501 struct cvmx_pko_reg_debug2_s cn58xx; 8502 struct cvmx_pko_reg_debug2_s cn58xxp1; 8503 struct cvmx_pko_reg_debug2_s cn61xx; 8504 struct cvmx_pko_reg_debug2_s cn63xx; 8505 struct cvmx_pko_reg_debug2_s cn63xxp1; 8506 struct cvmx_pko_reg_debug2_s cn66xx; 8507 struct cvmx_pko_reg_debug2_s cn68xx; 8508 struct cvmx_pko_reg_debug2_s cn68xxp1; 8509 struct cvmx_pko_reg_debug2_s cn70xx; 8510 struct cvmx_pko_reg_debug2_s cn70xxp1; 8511 struct cvmx_pko_reg_debug2_s cnf71xx; 8512 }; 8513 8514 typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t; 8515 8516 /** 8517 * cvmx_pko_reg_debug3 8518 */ 8519 union cvmx_pko_reg_debug3 { 8520 u64 u64; 8521 struct cvmx_pko_reg_debug3_s { 8522 u64 asserts : 64; 8523 } s; 8524 struct cvmx_pko_reg_debug3_s cn50xx; 8525 struct cvmx_pko_reg_debug3_s cn52xx; 8526 struct cvmx_pko_reg_debug3_s cn52xxp1; 8527 struct cvmx_pko_reg_debug3_s cn56xx; 8528 struct cvmx_pko_reg_debug3_s cn56xxp1; 8529 struct cvmx_pko_reg_debug3_s cn58xx; 8530 struct cvmx_pko_reg_debug3_s cn58xxp1; 8531 struct cvmx_pko_reg_debug3_s cn61xx; 8532 struct cvmx_pko_reg_debug3_s cn63xx; 8533 struct cvmx_pko_reg_debug3_s cn63xxp1; 8534 struct cvmx_pko_reg_debug3_s cn66xx; 8535 struct cvmx_pko_reg_debug3_s cn68xx; 8536 struct cvmx_pko_reg_debug3_s cn68xxp1; 8537 struct cvmx_pko_reg_debug3_s cn70xx; 8538 struct cvmx_pko_reg_debug3_s cn70xxp1; 8539 struct cvmx_pko_reg_debug3_s cnf71xx; 8540 }; 8541 8542 typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t; 8543 8544 /** 8545 * cvmx_pko_reg_debug4 8546 */ 8547 union cvmx_pko_reg_debug4 { 8548 u64 u64; 8549 struct cvmx_pko_reg_debug4_s { 8550 u64 asserts : 64; 8551 } s; 8552 struct cvmx_pko_reg_debug4_s cn68xx; 8553 struct cvmx_pko_reg_debug4_s cn68xxp1; 8554 }; 8555 8556 typedef union cvmx_pko_reg_debug4 cvmx_pko_reg_debug4_t; 8557 8558 /** 8559 * cvmx_pko_reg_engine_inflight 8560 * 8561 * Notes: 8562 * Sets the maximum number of inflight packets, per engine. Values greater than 4 are illegal. 8563 * Setting an engine's value to 0 effectively stops the engine. 8564 */ 8565 union cvmx_pko_reg_engine_inflight { 8566 u64 u64; 8567 struct cvmx_pko_reg_engine_inflight_s { 8568 u64 engine15 : 4; 8569 u64 engine14 : 4; 8570 u64 engine13 : 4; 8571 u64 engine12 : 4; 8572 u64 engine11 : 4; 8573 u64 engine10 : 4; 8574 u64 engine9 : 4; 8575 u64 engine8 : 4; 8576 u64 engine7 : 4; 8577 u64 engine6 : 4; 8578 u64 engine5 : 4; 8579 u64 engine4 : 4; 8580 u64 engine3 : 4; 8581 u64 engine2 : 4; 8582 u64 engine1 : 4; 8583 u64 engine0 : 4; 8584 } s; 8585 struct cvmx_pko_reg_engine_inflight_cn52xx { 8586 u64 reserved_40_63 : 24; 8587 u64 engine9 : 4; 8588 u64 engine8 : 4; 8589 u64 engine7 : 4; 8590 u64 engine6 : 4; 8591 u64 engine5 : 4; 8592 u64 engine4 : 4; 8593 u64 engine3 : 4; 8594 u64 engine2 : 4; 8595 u64 engine1 : 4; 8596 u64 engine0 : 4; 8597 } cn52xx; 8598 struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1; 8599 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx; 8600 struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1; 8601 struct cvmx_pko_reg_engine_inflight_cn61xx { 8602 u64 reserved_56_63 : 8; 8603 u64 engine13 : 4; 8604 u64 engine12 : 4; 8605 u64 engine11 : 4; 8606 u64 engine10 : 4; 8607 u64 engine9 : 4; 8608 u64 engine8 : 4; 8609 u64 engine7 : 4; 8610 u64 engine6 : 4; 8611 u64 engine5 : 4; 8612 u64 engine4 : 4; 8613 u64 engine3 : 4; 8614 u64 engine2 : 4; 8615 u64 engine1 : 4; 8616 u64 engine0 : 4; 8617 } cn61xx; 8618 struct cvmx_pko_reg_engine_inflight_cn63xx { 8619 u64 reserved_48_63 : 16; 8620 u64 engine11 : 4; 8621 u64 engine10 : 4; 8622 u64 engine9 : 4; 8623 u64 engine8 : 4; 8624 u64 engine7 : 4; 8625 u64 engine6 : 4; 8626 u64 engine5 : 4; 8627 u64 engine4 : 4; 8628 u64 engine3 : 4; 8629 u64 engine2 : 4; 8630 u64 engine1 : 4; 8631 u64 engine0 : 4; 8632 } cn63xx; 8633 struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1; 8634 struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx; 8635 struct cvmx_pko_reg_engine_inflight_s cn68xx; 8636 struct cvmx_pko_reg_engine_inflight_s cn68xxp1; 8637 struct cvmx_pko_reg_engine_inflight_cn61xx cn70xx; 8638 struct cvmx_pko_reg_engine_inflight_cn61xx cn70xxp1; 8639 struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx; 8640 }; 8641 8642 typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t; 8643 8644 /** 8645 * cvmx_pko_reg_engine_inflight1 8646 * 8647 * Notes: 8648 * Sets the maximum number of inflight packets, per engine. Values greater than 8 are illegal. 8649 * Setting an engine's value to 0 effectively stops the engine. 8650 */ 8651 union cvmx_pko_reg_engine_inflight1 { 8652 u64 u64; 8653 struct cvmx_pko_reg_engine_inflight1_s { 8654 u64 reserved_16_63 : 48; 8655 u64 engine19 : 4; 8656 u64 engine18 : 4; 8657 u64 engine17 : 4; 8658 u64 engine16 : 4; 8659 } s; 8660 struct cvmx_pko_reg_engine_inflight1_s cn68xx; 8661 struct cvmx_pko_reg_engine_inflight1_s cn68xxp1; 8662 }; 8663 8664 typedef union cvmx_pko_reg_engine_inflight1 cvmx_pko_reg_engine_inflight1_t; 8665 8666 /** 8667 * cvmx_pko_reg_engine_storage# 8668 * 8669 * Notes: 8670 * The PKO has 40KB of local storage, consisting of 20, 2KB chunks. Up to 15 contiguous chunks may be mapped per engine. 8671 * The total of all mapped storage must not exceed 40KB. 8672 */ 8673 union cvmx_pko_reg_engine_storagex { 8674 u64 u64; 8675 struct cvmx_pko_reg_engine_storagex_s { 8676 u64 engine15 : 4; 8677 u64 engine14 : 4; 8678 u64 engine13 : 4; 8679 u64 engine12 : 4; 8680 u64 engine11 : 4; 8681 u64 engine10 : 4; 8682 u64 engine9 : 4; 8683 u64 engine8 : 4; 8684 u64 engine7 : 4; 8685 u64 engine6 : 4; 8686 u64 engine5 : 4; 8687 u64 engine4 : 4; 8688 u64 engine3 : 4; 8689 u64 engine2 : 4; 8690 u64 engine1 : 4; 8691 u64 engine0 : 4; 8692 } s; 8693 struct cvmx_pko_reg_engine_storagex_s cn68xx; 8694 struct cvmx_pko_reg_engine_storagex_s cn68xxp1; 8695 }; 8696 8697 typedef union cvmx_pko_reg_engine_storagex cvmx_pko_reg_engine_storagex_t; 8698 8699 /** 8700 * cvmx_pko_reg_engine_thresh 8701 * 8702 * Notes: 8703 * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers. 8704 * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will 8705 * be sent until all of it has been written into the PKO's internal buffer. Note that a packet is 8706 * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8. When enabled and the 8707 * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until 8708 * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer 8709 * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above) 8710 */ 8711 union cvmx_pko_reg_engine_thresh { 8712 u64 u64; 8713 struct cvmx_pko_reg_engine_thresh_s { 8714 u64 reserved_20_63 : 44; 8715 u64 mask : 20; 8716 } s; 8717 struct cvmx_pko_reg_engine_thresh_cn52xx { 8718 u64 reserved_10_63 : 54; 8719 u64 mask : 10; 8720 } cn52xx; 8721 struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1; 8722 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx; 8723 struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1; 8724 struct cvmx_pko_reg_engine_thresh_cn61xx { 8725 u64 reserved_14_63 : 50; 8726 u64 mask : 14; 8727 } cn61xx; 8728 struct cvmx_pko_reg_engine_thresh_cn63xx { 8729 u64 reserved_12_63 : 52; 8730 u64 mask : 12; 8731 } cn63xx; 8732 struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1; 8733 struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx; 8734 struct cvmx_pko_reg_engine_thresh_s cn68xx; 8735 struct cvmx_pko_reg_engine_thresh_s cn68xxp1; 8736 struct cvmx_pko_reg_engine_thresh_cn61xx cn70xx; 8737 struct cvmx_pko_reg_engine_thresh_cn61xx cn70xxp1; 8738 struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx; 8739 }; 8740 8741 typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t; 8742 8743 /** 8744 * cvmx_pko_reg_error 8745 * 8746 * Notes: 8747 * Note that this CSR is present only in chip revisions beginning with pass2. 8748 * 8749 */ 8750 union cvmx_pko_reg_error { 8751 u64 u64; 8752 struct cvmx_pko_reg_error_s { 8753 u64 reserved_4_63 : 60; 8754 u64 loopback : 1; 8755 u64 currzero : 1; 8756 u64 doorbell : 1; 8757 u64 parity : 1; 8758 } s; 8759 struct cvmx_pko_reg_error_cn30xx { 8760 u64 reserved_2_63 : 62; 8761 u64 doorbell : 1; 8762 u64 parity : 1; 8763 } cn30xx; 8764 struct cvmx_pko_reg_error_cn30xx cn31xx; 8765 struct cvmx_pko_reg_error_cn30xx cn38xx; 8766 struct cvmx_pko_reg_error_cn30xx cn38xxp2; 8767 struct cvmx_pko_reg_error_cn50xx { 8768 u64 reserved_3_63 : 61; 8769 u64 currzero : 1; 8770 u64 doorbell : 1; 8771 u64 parity : 1; 8772 } cn50xx; 8773 struct cvmx_pko_reg_error_cn50xx cn52xx; 8774 struct cvmx_pko_reg_error_cn50xx cn52xxp1; 8775 struct cvmx_pko_reg_error_cn50xx cn56xx; 8776 struct cvmx_pko_reg_error_cn50xx cn56xxp1; 8777 struct cvmx_pko_reg_error_cn50xx cn58xx; 8778 struct cvmx_pko_reg_error_cn50xx cn58xxp1; 8779 struct cvmx_pko_reg_error_cn50xx cn61xx; 8780 struct cvmx_pko_reg_error_cn50xx cn63xx; 8781 struct cvmx_pko_reg_error_cn50xx cn63xxp1; 8782 struct cvmx_pko_reg_error_cn50xx cn66xx; 8783 struct cvmx_pko_reg_error_s cn68xx; 8784 struct cvmx_pko_reg_error_s cn68xxp1; 8785 struct cvmx_pko_reg_error_cn50xx cn70xx; 8786 struct cvmx_pko_reg_error_cn50xx cn70xxp1; 8787 struct cvmx_pko_reg_error_cn50xx cnf71xx; 8788 }; 8789 8790 typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t; 8791 8792 /** 8793 * cvmx_pko_reg_flags 8794 * 8795 * Notes: 8796 * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation. When set, ENA_DWB 8797 * enables the use of DontWriteBacks during the buffer freeing operations. When not set, STORE_BE inverts 8798 * bits[2:0] of the STORE0 byte write address. When set, RESET causes a 4-cycle reset pulse to the 8799 * entire box. 8800 */ 8801 union cvmx_pko_reg_flags { 8802 u64 u64; 8803 struct cvmx_pko_reg_flags_s { 8804 u64 reserved_9_63 : 55; 8805 u64 dis_perf3 : 1; 8806 u64 dis_perf2 : 1; 8807 u64 dis_perf1 : 1; 8808 u64 dis_perf0 : 1; 8809 u64 ena_throttle : 1; 8810 u64 reset : 1; 8811 u64 store_be : 1; 8812 u64 ena_dwb : 1; 8813 u64 ena_pko : 1; 8814 } s; 8815 struct cvmx_pko_reg_flags_cn30xx { 8816 u64 reserved_4_63 : 60; 8817 u64 reset : 1; 8818 u64 store_be : 1; 8819 u64 ena_dwb : 1; 8820 u64 ena_pko : 1; 8821 } cn30xx; 8822 struct cvmx_pko_reg_flags_cn30xx cn31xx; 8823 struct cvmx_pko_reg_flags_cn30xx cn38xx; 8824 struct cvmx_pko_reg_flags_cn30xx cn38xxp2; 8825 struct cvmx_pko_reg_flags_cn30xx cn50xx; 8826 struct cvmx_pko_reg_flags_cn30xx cn52xx; 8827 struct cvmx_pko_reg_flags_cn30xx cn52xxp1; 8828 struct cvmx_pko_reg_flags_cn30xx cn56xx; 8829 struct cvmx_pko_reg_flags_cn30xx cn56xxp1; 8830 struct cvmx_pko_reg_flags_cn30xx cn58xx; 8831 struct cvmx_pko_reg_flags_cn30xx cn58xxp1; 8832 struct cvmx_pko_reg_flags_cn61xx { 8833 u64 reserved_9_63 : 55; 8834 u64 dis_perf3 : 1; 8835 u64 dis_perf2 : 1; 8836 u64 reserved_4_6 : 3; 8837 u64 reset : 1; 8838 u64 store_be : 1; 8839 u64 ena_dwb : 1; 8840 u64 ena_pko : 1; 8841 } cn61xx; 8842 struct cvmx_pko_reg_flags_cn30xx cn63xx; 8843 struct cvmx_pko_reg_flags_cn30xx cn63xxp1; 8844 struct cvmx_pko_reg_flags_cn61xx cn66xx; 8845 struct cvmx_pko_reg_flags_s cn68xx; 8846 struct cvmx_pko_reg_flags_cn68xxp1 { 8847 u64 reserved_7_63 : 57; 8848 u64 dis_perf1 : 1; 8849 u64 dis_perf0 : 1; 8850 u64 ena_throttle : 1; 8851 u64 reset : 1; 8852 u64 store_be : 1; 8853 u64 ena_dwb : 1; 8854 u64 ena_pko : 1; 8855 } cn68xxp1; 8856 struct cvmx_pko_reg_flags_cn61xx cn70xx; 8857 struct cvmx_pko_reg_flags_cn61xx cn70xxp1; 8858 struct cvmx_pko_reg_flags_cn61xx cnf71xx; 8859 }; 8860 8861 typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t; 8862 8863 /** 8864 * cvmx_pko_reg_gmx_port_mode 8865 * 8866 * Notes: 8867 * The system has a total of 2 + 4 + 4 ports and 2 + 1 + 1 engines (GM0 + PCI + LOOP). 8868 * This CSR sets the number of GMX0 ports and amount of local storage per engine. 8869 * It has no effect on the number of ports or amount of local storage per engine for PCI and LOOP. 8870 * When both GMX ports are used (MODE0=3), each GMX engine has 10kB of local 8871 * storage. Increasing MODE0 to 4 decreases the number of GMX ports to 1 and 8872 * increases the local storage for the one remaining PKO GMX engine to 20kB. 8873 * MODE0 value 0, 1, and 2, or greater than 4 are illegal. 8874 * 8875 * MODE0 GMX0 PCI LOOP GMX0 PCI LOOP 8876 * ports ports ports storage/engine storage/engine storage/engine 8877 * 3 2 4 4 10.0kB 2.5kB 2.5kB 8878 * 4 1 4 4 20.0kB 2.5kB 2.5kB 8879 */ 8880 union cvmx_pko_reg_gmx_port_mode { 8881 u64 u64; 8882 struct cvmx_pko_reg_gmx_port_mode_s { 8883 u64 reserved_6_63 : 58; 8884 u64 mode1 : 3; 8885 u64 mode0 : 3; 8886 } s; 8887 struct cvmx_pko_reg_gmx_port_mode_s cn30xx; 8888 struct cvmx_pko_reg_gmx_port_mode_s cn31xx; 8889 struct cvmx_pko_reg_gmx_port_mode_s cn38xx; 8890 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; 8891 struct cvmx_pko_reg_gmx_port_mode_s cn50xx; 8892 struct cvmx_pko_reg_gmx_port_mode_s cn52xx; 8893 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; 8894 struct cvmx_pko_reg_gmx_port_mode_s cn56xx; 8895 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; 8896 struct cvmx_pko_reg_gmx_port_mode_s cn58xx; 8897 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; 8898 struct cvmx_pko_reg_gmx_port_mode_s cn61xx; 8899 struct cvmx_pko_reg_gmx_port_mode_s cn63xx; 8900 struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1; 8901 struct cvmx_pko_reg_gmx_port_mode_s cn66xx; 8902 struct cvmx_pko_reg_gmx_port_mode_s cn70xx; 8903 struct cvmx_pko_reg_gmx_port_mode_s cn70xxp1; 8904 struct cvmx_pko_reg_gmx_port_mode_s cnf71xx; 8905 }; 8906 8907 typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t; 8908 8909 /** 8910 * cvmx_pko_reg_int_mask 8911 * 8912 * Notes: 8913 * When a mask bit is set, the corresponding interrupt is enabled. 8914 * 8915 */ 8916 union cvmx_pko_reg_int_mask { 8917 u64 u64; 8918 struct cvmx_pko_reg_int_mask_s { 8919 u64 reserved_4_63 : 60; 8920 u64 loopback : 1; 8921 u64 currzero : 1; 8922 u64 doorbell : 1; 8923 u64 parity : 1; 8924 } s; 8925 struct cvmx_pko_reg_int_mask_cn30xx { 8926 u64 reserved_2_63 : 62; 8927 u64 doorbell : 1; 8928 u64 parity : 1; 8929 } cn30xx; 8930 struct cvmx_pko_reg_int_mask_cn30xx cn31xx; 8931 struct cvmx_pko_reg_int_mask_cn30xx cn38xx; 8932 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; 8933 struct cvmx_pko_reg_int_mask_cn50xx { 8934 u64 reserved_3_63 : 61; 8935 u64 currzero : 1; 8936 u64 doorbell : 1; 8937 u64 parity : 1; 8938 } cn50xx; 8939 struct cvmx_pko_reg_int_mask_cn50xx cn52xx; 8940 struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1; 8941 struct cvmx_pko_reg_int_mask_cn50xx cn56xx; 8942 struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1; 8943 struct cvmx_pko_reg_int_mask_cn50xx cn58xx; 8944 struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1; 8945 struct cvmx_pko_reg_int_mask_cn50xx cn61xx; 8946 struct cvmx_pko_reg_int_mask_cn50xx cn63xx; 8947 struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1; 8948 struct cvmx_pko_reg_int_mask_cn50xx cn66xx; 8949 struct cvmx_pko_reg_int_mask_s cn68xx; 8950 struct cvmx_pko_reg_int_mask_s cn68xxp1; 8951 struct cvmx_pko_reg_int_mask_cn50xx cn70xx; 8952 struct cvmx_pko_reg_int_mask_cn50xx cn70xxp1; 8953 struct cvmx_pko_reg_int_mask_cn50xx cnf71xx; 8954 }; 8955 8956 typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t; 8957 8958 /** 8959 * cvmx_pko_reg_loopback_bpid 8960 * 8961 * Notes: 8962 * None. 8963 * 8964 */ 8965 union cvmx_pko_reg_loopback_bpid { 8966 u64 u64; 8967 struct cvmx_pko_reg_loopback_bpid_s { 8968 u64 reserved_59_63 : 5; 8969 u64 bpid7 : 6; 8970 u64 reserved_52_52 : 1; 8971 u64 bpid6 : 6; 8972 u64 reserved_45_45 : 1; 8973 u64 bpid5 : 6; 8974 u64 reserved_38_38 : 1; 8975 u64 bpid4 : 6; 8976 u64 reserved_31_31 : 1; 8977 u64 bpid3 : 6; 8978 u64 reserved_24_24 : 1; 8979 u64 bpid2 : 6; 8980 u64 reserved_17_17 : 1; 8981 u64 bpid1 : 6; 8982 u64 reserved_10_10 : 1; 8983 u64 bpid0 : 6; 8984 u64 reserved_0_3 : 4; 8985 } s; 8986 struct cvmx_pko_reg_loopback_bpid_s cn68xx; 8987 struct cvmx_pko_reg_loopback_bpid_s cn68xxp1; 8988 }; 8989 8990 typedef union cvmx_pko_reg_loopback_bpid cvmx_pko_reg_loopback_bpid_t; 8991 8992 /** 8993 * cvmx_pko_reg_loopback_pkind 8994 * 8995 * Notes: 8996 * None. 8997 * 8998 */ 8999 union cvmx_pko_reg_loopback_pkind { 9000 u64 u64; 9001 struct cvmx_pko_reg_loopback_pkind_s { 9002 u64 reserved_59_63 : 5; 9003 u64 pkind7 : 6; 9004 u64 reserved_52_52 : 1; 9005 u64 pkind6 : 6; 9006 u64 reserved_45_45 : 1; 9007 u64 pkind5 : 6; 9008 u64 reserved_38_38 : 1; 9009 u64 pkind4 : 6; 9010 u64 reserved_31_31 : 1; 9011 u64 pkind3 : 6; 9012 u64 reserved_24_24 : 1; 9013 u64 pkind2 : 6; 9014 u64 reserved_17_17 : 1; 9015 u64 pkind1 : 6; 9016 u64 reserved_10_10 : 1; 9017 u64 pkind0 : 6; 9018 u64 num_ports : 4; 9019 } s; 9020 struct cvmx_pko_reg_loopback_pkind_s cn68xx; 9021 struct cvmx_pko_reg_loopback_pkind_s cn68xxp1; 9022 }; 9023 9024 typedef union cvmx_pko_reg_loopback_pkind cvmx_pko_reg_loopback_pkind_t; 9025 9026 /** 9027 * cvmx_pko_reg_min_pkt 9028 * 9029 * Notes: 9030 * This CSR is used with PKO_MEM_IPORT_PTRS[MIN_PKT] to select the minimum packet size. Packets whose 9031 * size in bytes < (SIZEn+1) are zero-padded to (SIZEn+1) bytes. Note that this does not include CRC bytes. 9032 * SIZE0=0 is read-only and is used when no padding is desired. 9033 */ 9034 union cvmx_pko_reg_min_pkt { 9035 u64 u64; 9036 struct cvmx_pko_reg_min_pkt_s { 9037 u64 size7 : 8; 9038 u64 size6 : 8; 9039 u64 size5 : 8; 9040 u64 size4 : 8; 9041 u64 size3 : 8; 9042 u64 size2 : 8; 9043 u64 size1 : 8; 9044 u64 size0 : 8; 9045 } s; 9046 struct cvmx_pko_reg_min_pkt_s cn68xx; 9047 struct cvmx_pko_reg_min_pkt_s cn68xxp1; 9048 }; 9049 9050 typedef union cvmx_pko_reg_min_pkt cvmx_pko_reg_min_pkt_t; 9051 9052 /** 9053 * cvmx_pko_reg_preempt 9054 */ 9055 union cvmx_pko_reg_preempt { 9056 u64 u64; 9057 struct cvmx_pko_reg_preempt_s { 9058 u64 reserved_16_63 : 48; 9059 u64 min_size : 16; 9060 } s; 9061 struct cvmx_pko_reg_preempt_s cn52xx; 9062 struct cvmx_pko_reg_preempt_s cn52xxp1; 9063 struct cvmx_pko_reg_preempt_s cn56xx; 9064 struct cvmx_pko_reg_preempt_s cn56xxp1; 9065 struct cvmx_pko_reg_preempt_s cn61xx; 9066 struct cvmx_pko_reg_preempt_s cn63xx; 9067 struct cvmx_pko_reg_preempt_s cn63xxp1; 9068 struct cvmx_pko_reg_preempt_s cn66xx; 9069 struct cvmx_pko_reg_preempt_s cn68xx; 9070 struct cvmx_pko_reg_preempt_s cn68xxp1; 9071 struct cvmx_pko_reg_preempt_s cn70xx; 9072 struct cvmx_pko_reg_preempt_s cn70xxp1; 9073 struct cvmx_pko_reg_preempt_s cnf71xx; 9074 }; 9075 9076 typedef union cvmx_pko_reg_preempt cvmx_pko_reg_preempt_t; 9077 9078 /** 9079 * cvmx_pko_reg_queue_mode 9080 * 9081 * Notes: 9082 * Sets the number of queues and amount of local storage per queue 9083 * The system has a total of 256 queues and (256*8) words of local command storage. This CSR sets the 9084 * number of queues that are used. Increasing the value of MODE by 1 decreases the number of queues 9085 * by a power of 2 and increases the local storage per queue by a power of 2. 9086 * MODEn queues storage/queue 9087 * 0 256 64B ( 8 words) 9088 * 1 128 128B (16 words) 9089 * 2 64 256B (32 words) 9090 */ 9091 union cvmx_pko_reg_queue_mode { 9092 u64 u64; 9093 struct cvmx_pko_reg_queue_mode_s { 9094 u64 reserved_2_63 : 62; 9095 u64 mode : 2; 9096 } s; 9097 struct cvmx_pko_reg_queue_mode_s cn30xx; 9098 struct cvmx_pko_reg_queue_mode_s cn31xx; 9099 struct cvmx_pko_reg_queue_mode_s cn38xx; 9100 struct cvmx_pko_reg_queue_mode_s cn38xxp2; 9101 struct cvmx_pko_reg_queue_mode_s cn50xx; 9102 struct cvmx_pko_reg_queue_mode_s cn52xx; 9103 struct cvmx_pko_reg_queue_mode_s cn52xxp1; 9104 struct cvmx_pko_reg_queue_mode_s cn56xx; 9105 struct cvmx_pko_reg_queue_mode_s cn56xxp1; 9106 struct cvmx_pko_reg_queue_mode_s cn58xx; 9107 struct cvmx_pko_reg_queue_mode_s cn58xxp1; 9108 struct cvmx_pko_reg_queue_mode_s cn61xx; 9109 struct cvmx_pko_reg_queue_mode_s cn63xx; 9110 struct cvmx_pko_reg_queue_mode_s cn63xxp1; 9111 struct cvmx_pko_reg_queue_mode_s cn66xx; 9112 struct cvmx_pko_reg_queue_mode_s cn68xx; 9113 struct cvmx_pko_reg_queue_mode_s cn68xxp1; 9114 struct cvmx_pko_reg_queue_mode_s cn70xx; 9115 struct cvmx_pko_reg_queue_mode_s cn70xxp1; 9116 struct cvmx_pko_reg_queue_mode_s cnf71xx; 9117 }; 9118 9119 typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t; 9120 9121 /** 9122 * cvmx_pko_reg_queue_preempt 9123 * 9124 * Notes: 9125 * Per QID, setting both PREEMPTER=1 and PREEMPTEE=1 is illegal and sets only PREEMPTER=1. 9126 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_REG_QUEUE_PTRS1. When programming queues, the 9127 * programming sequence must first write PKO_REG_QUEUE_PREEMPT, then PKO_REG_QUEUE_PTRS1 and then 9128 * PKO_MEM_QUEUE_PTRS for each queue. Preemption is supported only on queues that are ultimately 9129 * mapped to engines 0-7. It is illegal to set preemptee or preempter for a queue that is ultimately 9130 * mapped to engines 8-11. 9131 * 9132 * Also, PKO_REG_ENGINE_INFLIGHT must be at least 2 for any engine on which preemption is enabled. 9133 * 9134 * See the descriptions of PKO_MEM_QUEUE_PTRS for further explanation of queue programming. 9135 */ 9136 union cvmx_pko_reg_queue_preempt { 9137 u64 u64; 9138 struct cvmx_pko_reg_queue_preempt_s { 9139 u64 reserved_2_63 : 62; 9140 u64 preemptee : 1; 9141 u64 preempter : 1; 9142 } s; 9143 struct cvmx_pko_reg_queue_preempt_s cn52xx; 9144 struct cvmx_pko_reg_queue_preempt_s cn52xxp1; 9145 struct cvmx_pko_reg_queue_preempt_s cn56xx; 9146 struct cvmx_pko_reg_queue_preempt_s cn56xxp1; 9147 struct cvmx_pko_reg_queue_preempt_s cn61xx; 9148 struct cvmx_pko_reg_queue_preempt_s cn63xx; 9149 struct cvmx_pko_reg_queue_preempt_s cn63xxp1; 9150 struct cvmx_pko_reg_queue_preempt_s cn66xx; 9151 struct cvmx_pko_reg_queue_preempt_s cn68xx; 9152 struct cvmx_pko_reg_queue_preempt_s cn68xxp1; 9153 struct cvmx_pko_reg_queue_preempt_s cn70xx; 9154 struct cvmx_pko_reg_queue_preempt_s cn70xxp1; 9155 struct cvmx_pko_reg_queue_preempt_s cnf71xx; 9156 }; 9157 9158 typedef union cvmx_pko_reg_queue_preempt cvmx_pko_reg_queue_preempt_t; 9159 9160 /** 9161 * cvmx_pko_reg_queue_ptrs1 9162 * 9163 * Notes: 9164 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255 9165 * and to allow up mapping of up to 16 queues per port. When programming queues 128-255, the 9166 * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or 9167 * PKO_MEM_QUEUE_QOS for each queue. 9168 * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue 9169 * programming. 9170 */ 9171 union cvmx_pko_reg_queue_ptrs1 { 9172 u64 u64; 9173 struct cvmx_pko_reg_queue_ptrs1_s { 9174 u64 reserved_2_63 : 62; 9175 u64 idx3 : 1; 9176 u64 qid7 : 1; 9177 } s; 9178 struct cvmx_pko_reg_queue_ptrs1_s cn50xx; 9179 struct cvmx_pko_reg_queue_ptrs1_s cn52xx; 9180 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; 9181 struct cvmx_pko_reg_queue_ptrs1_s cn56xx; 9182 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; 9183 struct cvmx_pko_reg_queue_ptrs1_s cn58xx; 9184 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; 9185 struct cvmx_pko_reg_queue_ptrs1_s cn61xx; 9186 struct cvmx_pko_reg_queue_ptrs1_s cn63xx; 9187 struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1; 9188 struct cvmx_pko_reg_queue_ptrs1_s cn66xx; 9189 struct cvmx_pko_reg_queue_ptrs1_s cn70xx; 9190 struct cvmx_pko_reg_queue_ptrs1_s cn70xxp1; 9191 struct cvmx_pko_reg_queue_ptrs1_s cnf71xx; 9192 }; 9193 9194 typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t; 9195 9196 /** 9197 * cvmx_pko_reg_read_idx 9198 * 9199 * Notes: 9200 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 9201 * as memories. The names of these CSRs begin with the prefix "PKO_MEM_". 9202 * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 9203 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 9204 * contents of a CSR memory can be read with consecutive CSR read commands. 9205 */ 9206 union cvmx_pko_reg_read_idx { 9207 u64 u64; 9208 struct cvmx_pko_reg_read_idx_s { 9209 u64 reserved_16_63 : 48; 9210 u64 inc : 8; 9211 u64 index : 8; 9212 } s; 9213 struct cvmx_pko_reg_read_idx_s cn30xx; 9214 struct cvmx_pko_reg_read_idx_s cn31xx; 9215 struct cvmx_pko_reg_read_idx_s cn38xx; 9216 struct cvmx_pko_reg_read_idx_s cn38xxp2; 9217 struct cvmx_pko_reg_read_idx_s cn50xx; 9218 struct cvmx_pko_reg_read_idx_s cn52xx; 9219 struct cvmx_pko_reg_read_idx_s cn52xxp1; 9220 struct cvmx_pko_reg_read_idx_s cn56xx; 9221 struct cvmx_pko_reg_read_idx_s cn56xxp1; 9222 struct cvmx_pko_reg_read_idx_s cn58xx; 9223 struct cvmx_pko_reg_read_idx_s cn58xxp1; 9224 struct cvmx_pko_reg_read_idx_s cn61xx; 9225 struct cvmx_pko_reg_read_idx_s cn63xx; 9226 struct cvmx_pko_reg_read_idx_s cn63xxp1; 9227 struct cvmx_pko_reg_read_idx_s cn66xx; 9228 struct cvmx_pko_reg_read_idx_s cn68xx; 9229 struct cvmx_pko_reg_read_idx_s cn68xxp1; 9230 struct cvmx_pko_reg_read_idx_s cn70xx; 9231 struct cvmx_pko_reg_read_idx_s cn70xxp1; 9232 struct cvmx_pko_reg_read_idx_s cnf71xx; 9233 }; 9234 9235 typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t; 9236 9237 /** 9238 * cvmx_pko_reg_throttle 9239 * 9240 * Notes: 9241 * This CSR is used with PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT. INT_MASK corresponds to the 9242 * interfaces listed in the description for PKO_MEM_IPORT_PTRS[INT]. Set INT_MASK[N] to enable the 9243 * updating of PKO_MEM_THROTTLE_PIPE and PKO_MEM_THROTTLE_INT counts for packets destined for 9244 * interface N. INT_MASK has no effect on the updates caused by CSR writes to PKO_MEM_THROTTLE_PIPE 9245 * and PKO_MEM_THROTTLE_INT. Note that this does not disable the throttle logic, just the updating of 9246 * the interface counts. 9247 */ 9248 union cvmx_pko_reg_throttle { 9249 u64 u64; 9250 struct cvmx_pko_reg_throttle_s { 9251 u64 reserved_32_63 : 32; 9252 u64 int_mask : 32; 9253 } s; 9254 struct cvmx_pko_reg_throttle_s cn68xx; 9255 struct cvmx_pko_reg_throttle_s cn68xxp1; 9256 }; 9257 9258 typedef union cvmx_pko_reg_throttle cvmx_pko_reg_throttle_t; 9259 9260 /** 9261 * cvmx_pko_reg_timestamp 9262 * 9263 * Notes: 9264 * None. 9265 * 9266 */ 9267 union cvmx_pko_reg_timestamp { 9268 u64 u64; 9269 struct cvmx_pko_reg_timestamp_s { 9270 u64 reserved_4_63 : 60; 9271 u64 wqe_word : 4; 9272 } s; 9273 struct cvmx_pko_reg_timestamp_s cn61xx; 9274 struct cvmx_pko_reg_timestamp_s cn63xx; 9275 struct cvmx_pko_reg_timestamp_s cn63xxp1; 9276 struct cvmx_pko_reg_timestamp_s cn66xx; 9277 struct cvmx_pko_reg_timestamp_s cn68xx; 9278 struct cvmx_pko_reg_timestamp_s cn68xxp1; 9279 struct cvmx_pko_reg_timestamp_s cn70xx; 9280 struct cvmx_pko_reg_timestamp_s cn70xxp1; 9281 struct cvmx_pko_reg_timestamp_s cnf71xx; 9282 }; 9283 9284 typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t; 9285 9286 /** 9287 * cvmx_pko_shaper_cfg 9288 */ 9289 union cvmx_pko_shaper_cfg { 9290 u64 u64; 9291 struct cvmx_pko_shaper_cfg_s { 9292 u64 reserved_2_63 : 62; 9293 u64 color_aware : 1; 9294 u64 red_send_as_yellow : 1; 9295 } s; 9296 struct cvmx_pko_shaper_cfg_s cn73xx; 9297 struct cvmx_pko_shaper_cfg_s cn78xx; 9298 struct cvmx_pko_shaper_cfg_s cn78xxp1; 9299 struct cvmx_pko_shaper_cfg_s cnf75xx; 9300 }; 9301 9302 typedef union cvmx_pko_shaper_cfg cvmx_pko_shaper_cfg_t; 9303 9304 /** 9305 * cvmx_pko_state_uid_in_use#_rd 9306 * 9307 * For diagnostic use only. 9308 * 9309 */ 9310 union cvmx_pko_state_uid_in_usex_rd { 9311 u64 u64; 9312 struct cvmx_pko_state_uid_in_usex_rd_s { 9313 u64 in_use : 64; 9314 } s; 9315 struct cvmx_pko_state_uid_in_usex_rd_s cn73xx; 9316 struct cvmx_pko_state_uid_in_usex_rd_s cn78xx; 9317 struct cvmx_pko_state_uid_in_usex_rd_s cn78xxp1; 9318 struct cvmx_pko_state_uid_in_usex_rd_s cnf75xx; 9319 }; 9320 9321 typedef union cvmx_pko_state_uid_in_usex_rd cvmx_pko_state_uid_in_usex_rd_t; 9322 9323 /** 9324 * cvmx_pko_status 9325 */ 9326 union cvmx_pko_status { 9327 u64 u64; 9328 struct cvmx_pko_status_s { 9329 u64 pko_rdy : 1; 9330 u64 reserved_24_62 : 39; 9331 u64 c2qlut_rdy : 1; 9332 u64 ppfi_rdy : 1; 9333 u64 iobp1_rdy : 1; 9334 u64 ncb_rdy : 1; 9335 u64 pse_rdy : 1; 9336 u64 pdm_rdy : 1; 9337 u64 peb_rdy : 1; 9338 u64 csi_rdy : 1; 9339 u64 reserved_5_15 : 11; 9340 u64 ncb_bist_status : 1; 9341 u64 c2qlut_bist_status : 1; 9342 u64 pdm_bist_status : 1; 9343 u64 peb_bist_status : 1; 9344 u64 pse_bist_status : 1; 9345 } s; 9346 struct cvmx_pko_status_cn73xx { 9347 u64 pko_rdy : 1; 9348 u64 reserved_62_24 : 39; 9349 u64 c2qlut_rdy : 1; 9350 u64 ppfi_rdy : 1; 9351 u64 iobp1_rdy : 1; 9352 u64 ncb_rdy : 1; 9353 u64 pse_rdy : 1; 9354 u64 pdm_rdy : 1; 9355 u64 peb_rdy : 1; 9356 u64 csi_rdy : 1; 9357 u64 reserved_15_5 : 11; 9358 u64 ncb_bist_status : 1; 9359 u64 c2qlut_bist_status : 1; 9360 u64 pdm_bist_status : 1; 9361 u64 peb_bist_status : 1; 9362 u64 pse_bist_status : 1; 9363 } cn73xx; 9364 struct cvmx_pko_status_cn73xx cn78xx; 9365 struct cvmx_pko_status_cn73xx cn78xxp1; 9366 struct cvmx_pko_status_cn73xx cnf75xx; 9367 }; 9368 9369 typedef union cvmx_pko_status cvmx_pko_status_t; 9370 9371 /** 9372 * cvmx_pko_txf#_pkt_cnt_rd 9373 */ 9374 union cvmx_pko_txfx_pkt_cnt_rd { 9375 u64 u64; 9376 struct cvmx_pko_txfx_pkt_cnt_rd_s { 9377 u64 reserved_8_63 : 56; 9378 u64 cnt : 8; 9379 } s; 9380 struct cvmx_pko_txfx_pkt_cnt_rd_s cn73xx; 9381 struct cvmx_pko_txfx_pkt_cnt_rd_s cn78xx; 9382 struct cvmx_pko_txfx_pkt_cnt_rd_s cn78xxp1; 9383 struct cvmx_pko_txfx_pkt_cnt_rd_s cnf75xx; 9384 }; 9385 9386 typedef union cvmx_pko_txfx_pkt_cnt_rd cvmx_pko_txfx_pkt_cnt_rd_t; 9387 9388 #endif 9389