1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <env.h>
10 #include <errno.h>
11 #include <init.h>
12 #include <log.h>
13 #include <ns16550.h>
14 #include <usb.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/board.h>
19 #include <asm/arch-tegra/cboot.h>
20 #include <asm/arch-tegra/clk_rst.h>
21 #include <asm/arch-tegra/pmc.h>
22 #include <asm/arch-tegra/pmu.h>
23 #include <asm/arch-tegra/sys_proto.h>
24 #include <asm/arch-tegra/uart.h>
25 #include <asm/arch-tegra/warmboot.h>
26 #include <asm/arch-tegra/gpu.h>
27 #include <asm/arch-tegra/usb.h>
28 #include <asm/arch-tegra/xusb-padctl.h>
29 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
30 #include <asm/arch/clock.h>
31 #endif
32 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
33 #include <asm/arch/funcmux.h>
34 #include <asm/arch/pinmux.h>
35 #endif
36 #include <asm/arch/tegra.h>
37 #ifdef CONFIG_TEGRA_CLOCK_SCALING
38 #include <asm/arch/emc.h>
39 #endif
40 #include "emc.h"
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 #ifdef CONFIG_SPL_BUILD
45 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
46 U_BOOT_DRVINFO(tegra_gpios) = {
47 "gpio_tegra"
48 };
49 #endif
50
pinmux_init(void)51 __weak void pinmux_init(void) {}
pin_mux_usb(void)52 __weak void pin_mux_usb(void) {}
pin_mux_spi(void)53 __weak void pin_mux_spi(void) {}
pin_mux_mmc(void)54 __weak void pin_mux_mmc(void) {}
gpio_early_init_uart(void)55 __weak void gpio_early_init_uart(void) {}
pin_mux_display(void)56 __weak void pin_mux_display(void) {}
start_cpu_fan(void)57 __weak void start_cpu_fan(void) {}
cboot_late_init(void)58 __weak void cboot_late_init(void) {}
59
60 #if defined(CONFIG_TEGRA_NAND)
pin_mux_nand(void)61 __weak void pin_mux_nand(void)
62 {
63 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
64 }
65 #endif
66
67 /*
68 * Routine: power_det_init
69 * Description: turn off power detects
70 */
power_det_init(void)71 static void power_det_init(void)
72 {
73 #if defined(CONFIG_TEGRA20)
74 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
75
76 /* turn off power detects */
77 writel(0, &pmc->pmc_pwr_det_latch);
78 writel(0, &pmc->pmc_pwr_det);
79 #endif
80 }
81
tegra_board_id(void)82 __weak int tegra_board_id(void)
83 {
84 return -1;
85 }
86
87 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)88 int checkboard(void)
89 {
90 int board_id = tegra_board_id();
91
92 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
93 if (board_id != -1)
94 printf(", ID: %d\n", board_id);
95 printf("\n");
96
97 return 0;
98 }
99 #endif /* CONFIG_DISPLAY_BOARDINFO */
100
tegra_lcd_pmic_init(int board_it)101 __weak int tegra_lcd_pmic_init(int board_it)
102 {
103 return 0;
104 }
105
nvidia_board_init(void)106 __weak int nvidia_board_init(void)
107 {
108 return 0;
109 }
110
111 /*
112 * Routine: board_init
113 * Description: Early hardware init.
114 */
board_init(void)115 int board_init(void)
116 {
117 __maybe_unused int err;
118 __maybe_unused int board_id;
119
120 /* Do clocks and UART first so that printf() works */
121 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
122 clock_init();
123 clock_verify();
124 #endif
125
126 tegra_gpu_config();
127
128 #ifdef CONFIG_TEGRA_SPI
129 pin_mux_spi();
130 #endif
131
132 #ifdef CONFIG_MMC_SDHCI_TEGRA
133 pin_mux_mmc();
134 #endif
135
136 /* Init is handled automatically in the driver-model case */
137 #if defined(CONFIG_DM_VIDEO)
138 pin_mux_display();
139 #endif
140 /* boot param addr */
141 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
142
143 power_det_init();
144
145 #ifdef CONFIG_SYS_I2C_TEGRA
146 # ifdef CONFIG_TEGRA_PMU
147 if (pmu_set_nominal())
148 debug("Failed to select nominal voltages\n");
149 # ifdef CONFIG_TEGRA_CLOCK_SCALING
150 err = board_emc_init();
151 if (err)
152 debug("Memory controller init failed: %d\n", err);
153 # endif
154 # endif /* CONFIG_TEGRA_PMU */
155 #endif /* CONFIG_SYS_I2C_TEGRA */
156
157 #ifdef CONFIG_USB_EHCI_TEGRA
158 pin_mux_usb();
159 #endif
160
161 #if defined(CONFIG_DM_VIDEO)
162 board_id = tegra_board_id();
163 err = tegra_lcd_pmic_init(board_id);
164 if (err) {
165 debug("Failed to set up LCD PMIC\n");
166 return err;
167 }
168 #endif
169
170 #ifdef CONFIG_TEGRA_NAND
171 pin_mux_nand();
172 #endif
173
174 tegra_xusb_padctl_init();
175
176 #ifdef CONFIG_TEGRA_LP0
177 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
178 warmboot_save_sdram_params();
179
180 /* prepare the WB code to LP0 location */
181 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
182 #endif
183 return nvidia_board_init();
184 }
185
board_cleanup_before_linux(void)186 void board_cleanup_before_linux(void)
187 {
188 /* power down UPHY PLL */
189 tegra_xusb_padctl_exit();
190 }
191
192 #ifdef CONFIG_BOARD_EARLY_INIT_F
__gpio_early_init(void)193 static void __gpio_early_init(void)
194 {
195 }
196
197 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
198
board_early_init_f(void)199 int board_early_init_f(void)
200 {
201 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
202 if (!clock_early_init_done())
203 clock_early_init();
204 #endif
205
206 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
207 #define USBCMD_FS2 (1 << 15)
208 {
209 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
210 writel(USBCMD_FS2, &usbctlr->usb_cmd);
211 }
212 #endif
213
214 /* Do any special system timer/TSC setup */
215 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
216 # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
217 if (!tegra_cpu_is_non_secure())
218 # endif
219 arch_timer_init();
220 #endif
221
222 #if defined(CONFIG_DISABLE_SDMMC1_EARLY)
223 /*
224 * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
225 * We do this because earlier bootloaders have enabled power to
226 * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
227 * results in power being back-driven into the SD-card and SDMMC1
228 * HW, which is 'bad' as per the HW team.
229 *
230 * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
231 * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
232 * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
233 * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
234 * voltage turns off. Since the SDCard voltage is no longer there, the
235 * SDMMC CLK/DAT lines are backdriving into what essentially is a
236 * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
237 *
238 * Note that this can probably be removed when we change over to storing
239 * all BL components on QSPI on Nano, and U-Boot then becomes the first
240 * one to turn on SDMMC1 power. Another fix would be to have CBoot
241 * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
242 */
243 reset_set_enable(PERIPH_ID_SDMMC1, 1);
244 clock_set_enable(PERIPH_ID_SDMMC1, 0);
245 #endif /* CONFIG_DISABLE_SDMMC1_EARLY */
246
247 pinmux_init();
248 board_init_uart_f();
249
250 /* Initialize periph GPIOs */
251 gpio_early_init();
252 gpio_early_init_uart();
253
254 return 0;
255 }
256 #endif /* EARLY_INIT */
257
board_late_init(void)258 int board_late_init(void)
259 {
260 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
261 if (tegra_cpu_is_non_secure()) {
262 printf("CPU is in NS mode\n");
263 env_set("cpu_ns_mode", "1");
264 } else {
265 env_set("cpu_ns_mode", "");
266 }
267 #endif
268 start_cpu_fan();
269 cboot_late_init();
270
271 return 0;
272 }
273
274 /*
275 * In some SW environments, a memory carve-out exists to house a secure
276 * monitor, a trusted OS, and/or various statically allocated media buffers.
277 *
278 * This carveout exists at the highest possible address that is within a
279 * 32-bit physical address space.
280 *
281 * This function returns the total size of this carve-out. At present, the
282 * returned value is hard-coded for simplicity. In the future, it may be
283 * possible to determine the carve-out size:
284 * - By querying some run-time information source, such as:
285 * - A structure passed to U-Boot by earlier boot software.
286 * - SoC registers.
287 * - A call into the secure monitor.
288 * - In the per-board U-Boot configuration header, based on knowledge of the
289 * SW environment that U-Boot is being built for.
290 *
291 * For now, we support two configurations in U-Boot:
292 * - 32-bit ports without any form of carve-out.
293 * - 64 bit ports which are assumed to use a carve-out of a conservatively
294 * hard-coded size.
295 */
carveout_size(void)296 static ulong carveout_size(void)
297 {
298 #ifdef CONFIG_ARM64
299 return SZ_512M;
300 #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
301 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
302 // from BASE to 4GB, not BASE to BASE+SIZE.
303 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
304 #else
305 return 0;
306 #endif
307 }
308
309 /*
310 * Determine the amount of usable RAM below 4GiB, taking into account any
311 * carve-out that may be assigned.
312 */
usable_ram_size_below_4g(void)313 static ulong usable_ram_size_below_4g(void)
314 {
315 ulong total_size_below_4g;
316 ulong usable_size_below_4g;
317
318 /*
319 * The total size of RAM below 4GiB is the lesser address of:
320 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
321 * (b) The size RAM physically present in the system.
322 */
323 if (gd->ram_size < SZ_2G)
324 total_size_below_4g = gd->ram_size;
325 else
326 total_size_below_4g = SZ_2G;
327
328 /* Calculate usable RAM by subtracting out any carve-out size */
329 usable_size_below_4g = total_size_below_4g - carveout_size();
330
331 return usable_size_below_4g;
332 }
333
334 /*
335 * Represent all available RAM in either one or two banks.
336 *
337 * The first bank describes any usable RAM below 4GiB.
338 * The second bank describes any RAM above 4GiB.
339 *
340 * This split is driven by the following requirements:
341 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
342 * property for memory below and above the 4GiB boundary. The layout of that
343 * DT property is directly driven by the entries in the U-Boot bank array.
344 * - The potential existence of a carve-out at the end of RAM below 4GiB can
345 * only be represented using multiple banks.
346 *
347 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
348 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
349 * command-line.
350 *
351 * This does mean that the DT U-Boot passes to the Linux kernel will not
352 * include this RAM in /memory/reg at all. An alternative would be to include
353 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
354 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
355 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
356 * mapping, so either way is acceptable.
357 *
358 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
359 * start address of that bank cannot be represented in the 32-bit .size
360 * field.
361 */
dram_init_banksize(void)362 int dram_init_banksize(void)
363 {
364 int err;
365
366 /* try to compute DRAM bank size based on cboot DTB first */
367 err = cboot_dram_init_banksize();
368 if (err == 0)
369 return err;
370
371 /* fall back to default DRAM bank size computation */
372
373 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
374 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
375
376 #ifdef CONFIG_PCI
377 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
378 #endif
379
380 #ifdef CONFIG_PHYS_64BIT
381 if (gd->ram_size > SZ_2G) {
382 gd->bd->bi_dram[1].start = 0x100000000;
383 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
384 } else
385 #endif
386 {
387 gd->bd->bi_dram[1].start = 0;
388 gd->bd->bi_dram[1].size = 0;
389 }
390
391 return 0;
392 }
393
394 /*
395 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
396 * 32-bits of the physical address space. Cap the maximum usable RAM area
397 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
398 * boundary that most devices can address. Also, don't let U-Boot use any
399 * carve-out, as mentioned above.
400 *
401 * This function is called before dram_init_banksize(), so we can't simply
402 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
403 */
board_get_usable_ram_top(ulong total_size)404 ulong board_get_usable_ram_top(ulong total_size)
405 {
406 ulong ram_top;
407
408 /* try to get top of usable RAM based on cboot DTB first */
409 ram_top = cboot_get_usable_ram_top(total_size);
410 if (ram_top > 0)
411 return ram_top;
412
413 /* fall back to default usable RAM computation */
414
415 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
416 }
417