1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Sun8i a33 platform dram controller init.
4 *
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
6 * Jerry Wang <wangflord@allwinnertech.com>
7 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
8 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
9 */
10 #include <common.h>
11 #include <errno.h>
12 #include <init.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/dram.h>
16 #include <asm/arch/prcm.h>
17 #include <linux/delay.h>
18
19 #define DRAM_CLK_MUL 2
20 #define DRAM_CLK_DIV 1
21
22 struct dram_para {
23 u8 cs1;
24 u8 seq;
25 u8 bank;
26 u8 rank;
27 u8 rows;
28 u8 bus_width;
29 u8 dram_type;
30 u16 page_size;
31 };
32
mctl_set_cr(struct dram_para * para)33 static void mctl_set_cr(struct dram_para *para)
34 {
35 struct sunxi_mctl_com_reg * const mctl_com =
36 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
37
38 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
39 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
40 (para->seq ? MCTL_CR_SEQUENCE : 0) |
41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
42 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
44 &mctl_com->cr);
45 }
46
auto_detect_dram_size(struct dram_para * para)47 static void auto_detect_dram_size(struct dram_para *para)
48 {
49 u8 orig_rank = para->rank;
50 int rows, columns;
51
52 /* Row detect */
53 para->page_size = 512;
54 para->seq = 1;
55 para->rows = 16;
56 para->rank = 1;
57 mctl_set_cr(para);
58 for (rows = 11 ; rows < 16 ; rows++) {
59 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
60 break;
61 }
62
63 /* Column (page size) detect */
64 para->rows = 11;
65 para->page_size = 8192;
66 mctl_set_cr(para);
67 for (columns = 9 ; columns < 13 ; columns++) {
68 if (mctl_mem_matches(1 << columns))
69 break;
70 }
71
72 para->seq = 0;
73 para->rank = orig_rank;
74 para->rows = rows;
75 para->page_size = 1 << columns;
76 mctl_set_cr(para);
77 }
78
ns_to_t(int nanoseconds)79 static inline int ns_to_t(int nanoseconds)
80 {
81 const unsigned int ctrl_freq =
82 CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
83
84 return (ctrl_freq * nanoseconds + 999) / 1000;
85 }
86
auto_set_timing_para(struct dram_para * para)87 static void auto_set_timing_para(struct dram_para *para)
88 {
89 struct sunxi_mctl_ctl_reg * const mctl_ctl =
90 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
91
92 u32 reg_val;
93
94 u8 tccd = 2;
95 u8 tfaw = ns_to_t(50);
96 u8 trrd = max(ns_to_t(10), 4);
97 u8 trcd = ns_to_t(15);
98 u8 trc = ns_to_t(53);
99 u8 txp = max(ns_to_t(8), 3);
100 u8 twtr = max(ns_to_t(8), 4);
101 u8 trtp = max(ns_to_t(8), 4);
102 u8 twr = max(ns_to_t(15), 3);
103 u8 trp = ns_to_t(15);
104 u8 tras = ns_to_t(38);
105
106 u16 trefi = ns_to_t(7800) / 32;
107 u16 trfc = ns_to_t(350);
108
109 /* Fixed timing parameters */
110 u8 tmrw = 0;
111 u8 tmrd = 4;
112 u8 tmod = 12;
113 u8 tcke = 3;
114 u8 tcksrx = 5;
115 u8 tcksre = 5;
116 u8 tckesr = 4;
117 u8 trasmax = 24;
118 u8 tcl = 6; /* CL 12 */
119 u8 tcwl = 4; /* CWL 8 */
120 u8 t_rdata_en = 4;
121 u8 wr_latency = 2;
122
123 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
124 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
125 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
126 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
127
128 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
129 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
130 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
131
132 /* Set work mode register */
133 mctl_set_cr(para);
134 /* Set mode register */
135 if (para->dram_type == DRAM_TYPE_DDR3) {
136 writel(MCTL_MR0, &mctl_ctl->mr0);
137 writel(MCTL_MR1, &mctl_ctl->mr1);
138 writel(MCTL_MR2, &mctl_ctl->mr2);
139 writel(MCTL_MR3, &mctl_ctl->mr3);
140 } else if (para->dram_type == DRAM_TYPE_LPDDR3) {
141 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
142 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
143 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
144 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
145
146 /* timing parameters for LPDDR3 */
147 tfaw = max(ns_to_t(50), 4);
148 trrd = max(ns_to_t(10), 2);
149 trcd = max(ns_to_t(24), 2);
150 trc = ns_to_t(70);
151 txp = max(ns_to_t(8), 2);
152 twtr = max(ns_to_t(8), 2);
153 trtp = max(ns_to_t(8), 2);
154 trp = max(ns_to_t(27), 2);
155 tras = ns_to_t(42);
156 trefi = ns_to_t(3900) / 32;
157 trfc = ns_to_t(210);
158 tmrw = 5;
159 tmrd = 5;
160 tckesr = 5;
161 tcwl = 3; /* CWL 8 */
162 t_rdata_en = 5;
163 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
164 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
165 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
166 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
167 twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
168 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
169 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
170 }
171 /* Set dram timing */
172 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
173 writel(reg_val, &mctl_ctl->dramtmg0);
174 reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
175 writel(reg_val, &mctl_ctl->dramtmg1);
176 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
177 writel(reg_val, &mctl_ctl->dramtmg2);
178 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
179 writel(reg_val, &mctl_ctl->dramtmg3);
180 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
181 writel(reg_val, &mctl_ctl->dramtmg4);
182 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
183 writel(reg_val, &mctl_ctl->dramtmg5);
184 /* Set two rank timing and exit self-refresh timing */
185 reg_val = readl(&mctl_ctl->dramtmg8);
186 reg_val &= ~(0xff << 8);
187 reg_val &= ~(0xff << 0);
188 reg_val |= (0x33 << 8);
189 reg_val |= (0x8 << 0);
190 writel(reg_val, &mctl_ctl->dramtmg8);
191 /* Set phy interface time */
192 reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
193 | (wr_latency << 0);
194 /* PHY interface write latency and read latency configure */
195 writel(reg_val, &mctl_ctl->pitmg0);
196 /* Set phy time PTR0-2 use default */
197 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
198 writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
199 /* Set refresh timing */
200 reg_val = (trefi << 16) | (trfc << 0);
201 writel(reg_val, &mctl_ctl->rfshtmg);
202 }
203
mctl_set_pir(u32 val)204 static void mctl_set_pir(u32 val)
205 {
206 struct sunxi_mctl_ctl_reg * const mctl_ctl =
207 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
208
209 writel(val, &mctl_ctl->pir);
210 mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
211 }
212
mctl_data_train_cfg(struct dram_para * para)213 static void mctl_data_train_cfg(struct dram_para *para)
214 {
215 struct sunxi_mctl_ctl_reg * const mctl_ctl =
216 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
217
218 if (para->rank == 2)
219 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
220 else
221 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
222 }
223
mctl_train_dram(struct dram_para * para)224 static int mctl_train_dram(struct dram_para *para)
225 {
226 struct sunxi_mctl_ctl_reg * const mctl_ctl =
227 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
228
229 mctl_data_train_cfg(para);
230 mctl_set_pir(0x5f3);
231
232 return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
233 }
234
set_master_priority(void)235 static void set_master_priority(void)
236 {
237 writel(0x00a0000d, MCTL_MASTER_CFG0(0));
238 writel(0x00500064, MCTL_MASTER_CFG1(0));
239 writel(0x07000009, MCTL_MASTER_CFG0(1));
240 writel(0x00000600, MCTL_MASTER_CFG1(1));
241 writel(0x01000009, MCTL_MASTER_CFG0(3));
242 writel(0x00000064, MCTL_MASTER_CFG1(3));
243 writel(0x08000009, MCTL_MASTER_CFG0(4));
244 writel(0x00000640, MCTL_MASTER_CFG1(4));
245 writel(0x20000308, MCTL_MASTER_CFG0(8));
246 writel(0x00001000, MCTL_MASTER_CFG1(8));
247 writel(0x02800009, MCTL_MASTER_CFG0(9));
248 writel(0x00000100, MCTL_MASTER_CFG1(9));
249 writel(0x01800009, MCTL_MASTER_CFG0(5));
250 writel(0x00000100, MCTL_MASTER_CFG1(5));
251 writel(0x01800009, MCTL_MASTER_CFG0(7));
252 writel(0x00000100, MCTL_MASTER_CFG1(7));
253 writel(0x00640009, MCTL_MASTER_CFG0(6));
254 writel(0x00000032, MCTL_MASTER_CFG1(6));
255 writel(0x0100000d, MCTL_MASTER_CFG0(2));
256 writel(0x00500080, MCTL_MASTER_CFG1(2));
257 }
258
mctl_channel_init(struct dram_para * para)259 static int mctl_channel_init(struct dram_para *para)
260 {
261 struct sunxi_mctl_ctl_reg * const mctl_ctl =
262 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
263 struct sunxi_mctl_com_reg * const mctl_com =
264 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
265 u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
266 u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
267 u32 i, rval;
268
269 auto_set_timing_para(para);
270
271 /* Set dram master access priority */
272 writel(0x000101a0, &mctl_com->bwcr);
273 /* set cpu high priority */
274 writel(0x1, &mctl_com->mapr);
275 set_master_priority();
276 udelay(250);
277
278 /* Disable dram VTC */
279 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
280 clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
281
282 writel(0x94be6fa3, MCTL_PROTECT);
283 udelay(100);
284 clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
285 writel(0x0, MCTL_PROTECT);
286 udelay(100);
287
288
289 /* Set ODT */
290 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
291 rval = 0x0;
292 else
293 rval = 0x2;
294
295 for (i = 0 ; i < 11 ; i++) {
296 clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
297 rval << 24);
298 clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
299 rval << 24);
300 clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
301 rval << 24);
302 clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
303 rval << 24);
304 }
305
306 for (i = 0; i < 31; i++)
307 clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
308
309 /* set PLL configuration */
310 if (CONFIG_DRAM_CLK >= 480)
311 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
312 else
313 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
314
315 /* Auto detect dram config, set 2 rank and 16bit bus-width */
316 para->cs1 = 0;
317 para->rank = 2;
318 para->bus_width = 16;
319 mctl_set_cr(para);
320
321 /* Open DQS gating */
322 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
323 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
324
325 if (para->dram_type == DRAM_TYPE_LPDDR3)
326 clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
327 0x1 << 31);
328 if (readl(&mctl_com->cr) & 0x1)
329 writel(0x00000303, &mctl_ctl->odtmap);
330 else
331 writel(0x00000201, &mctl_ctl->odtmap);
332
333 mctl_data_train_cfg(para);
334 /* ZQ calibration */
335 clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
336 clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
337 /* CA calibration */
338
339 if (para->dram_type == DRAM_TYPE_DDR3)
340 mctl_set_pir(0x0201f3 | 0x1<<10);
341 else
342 mctl_set_pir(0x020173 | 0x1<<10);
343
344 /* DQS gate training */
345 if (mctl_train_dram(para) != 0) {
346 low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
347 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
348
349 if (low_data_lines_status == 0x3)
350 return -EIO;
351
352 /* DRAM has only one rank */
353 para->rank = 1;
354 mctl_set_cr(para);
355
356 if (low_data_lines_status == high_data_lines_status)
357 goto done; /* 16 bit bus, 1 rank */
358
359 if (!(low_data_lines_status & high_data_lines_status)) {
360 /* Retry 16 bit bus-width with CS1 set */
361 para->cs1 = 1;
362 mctl_set_cr(para);
363 if (mctl_train_dram(para) == 0)
364 goto done;
365 }
366
367 /* Try 8 bit bus-width */
368 writel(0x0, DXnGCR0(1)); /* Disable high DQ */
369 para->cs1 = 0;
370 para->bus_width = 8;
371 mctl_set_cr(para);
372 if (mctl_train_dram(para) != 0)
373 return -EIO;
374 }
375 done:
376 /* Check the dramc status */
377 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
378
379 /* Close DQS gating */
380 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
381
382 /* set PGCR3,CKE polarity */
383 writel(0x00aa0060, &mctl_ctl->pgcr3);
384 /* Enable master access */
385 writel(0xffffffff, &mctl_com->maer);
386
387 return 0;
388 }
389
mctl_sys_init(struct dram_para * para)390 static void mctl_sys_init(struct dram_para *para)
391 {
392 struct sunxi_ccm_reg * const ccm =
393 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
394 struct sunxi_mctl_ctl_reg * const mctl_ctl =
395 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
396
397 clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
398 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
399 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
400 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
401 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
402 udelay(1000);
403 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
404
405 clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
406
407 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
408 CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
409 CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
410 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
411
412 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
413 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
414 setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
415 setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
416
417 para->rank = 2;
418 para->bus_width = 16;
419 mctl_set_cr(para);
420
421 /* Set dram master access priority */
422 writel(0x0000e00f, &mctl_ctl->clken); /* normal */
423
424 udelay(250);
425 }
426
sunxi_dram_init(void)427 unsigned long sunxi_dram_init(void)
428 {
429 struct sunxi_mctl_com_reg * const mctl_com =
430 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
431 struct sunxi_mctl_ctl_reg * const mctl_ctl =
432 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
433
434 struct dram_para para = {
435 .cs1 = 0,
436 .bank = 1,
437 .rank = 1,
438 .rows = 15,
439 .bus_width = 16,
440 .page_size = 2048,
441 };
442
443 #if defined(CONFIG_MACH_SUN8I_A83T)
444 #if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
445 para.dram_type = CONFIG_DRAM_TYPE;
446 #else
447 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
448 #endif
449 #endif
450 setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
451
452 writel(0, (SUNXI_PRCM_BASE + 0x1e8));
453 udelay(10);
454
455 mctl_sys_init(¶);
456
457 if (mctl_channel_init(¶) != 0)
458 return 0;
459
460 auto_detect_dram_size(¶);
461
462 /* Enable master software clk */
463 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
464
465 /* Set DRAM ODT MAP */
466 if (para.rank == 2)
467 writel(0x00000303, &mctl_ctl->odtmap);
468 else
469 writel(0x00000201, &mctl_ctl->odtmap);
470
471 return para.page_size * (para.bus_width / 8) *
472 (1 << (para.bank + para.rank + para.rows));
473 }
474