1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4  */
5 
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ar71xx_regs.h>
13 #include <mach/ath79.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
ar933x_get_xtal(void)17 static u32 ar933x_get_xtal(void)
18 {
19 	u32 val;
20 
21 	val = ath79_get_bootstrap();
22 	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
23 		return 40000000;
24 	else
25 		return 25000000;
26 }
27 
get_serial_clock(void)28 int get_serial_clock(void)
29 {
30 	return ar933x_get_xtal();
31 }
32 
get_clocks(void)33 int get_clocks(void)
34 {
35 	void __iomem *regs;
36 	u32 val, xtal, pll, div;
37 
38 	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
39 			   MAP_NOCACHE);
40 	xtal = ar933x_get_xtal();
41 	val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
42 
43 	/* VCOOUT = XTAL * DIV_INT */
44 	div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
45 			& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
46 	pll = xtal / div;
47 
48 	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
49 	div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
50 			& AR933X_PLL_CPU_CONFIG_NINT_MASK;
51 	pll *= div;
52 	div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
53 			& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
54 	if (!div)
55 		div = 1;
56 	pll >>= div;
57 
58 	val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
59 
60 	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
61 	div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
62 			& AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
63 	gd->cpu_clk = pll / div;
64 
65 	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
66 	div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
67 			& AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
68 	gd->mem_clk = pll / div;
69 
70 	/* AHB_CLK = PLLOUT / AHB_POST_DIV */
71 	div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
72 			& AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
73 	gd->bus_clk = pll / div;
74 
75 	return 0;
76 }
77 
get_bus_freq(ulong dummy)78 ulong get_bus_freq(ulong dummy)
79 {
80 	if (!gd->bus_clk)
81 		get_clocks();
82 	return gd->bus_clk;
83 }
84 
get_ddr_freq(ulong dummy)85 ulong get_ddr_freq(ulong dummy)
86 {
87 	if (!gd->mem_clk)
88 		get_clocks();
89 	return gd->mem_clk;
90 }
91