1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * uniphier_spi.c - Socionext UniPhier SPI driver
4 * Copyright 2019 Socionext, Inc.
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <time.h>
12 #include <asm/global_data.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <spi.h>
19 #include <wait_bit.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define SSI_CTL 0x00
24 #define SSI_CTL_EN BIT(0)
25
26 #define SSI_CKS 0x04
27 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
28 #define SSI_CKS_CKPHS BIT(14)
29 #define SSI_CKS_CKINIT BIT(13)
30 #define SSI_CKS_CKDLY BIT(12)
31
32 #define SSI_TXWDS 0x08
33 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
34 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
35 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
36
37 #define SSI_RXWDS 0x0c
38 #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
39 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
40
41 #define SSI_FPS 0x10
42 #define SSI_FPS_FSPOL BIT(15)
43 #define SSI_FPS_FSTRT BIT(14)
44
45 #define SSI_SR 0x14
46 #define SSI_SR_BUSY BIT(7)
47 #define SSI_SR_TNF BIT(5)
48 #define SSI_SR_RNE BIT(0)
49
50 #define SSI_IE 0x18
51
52 #define SSI_IC 0x1c
53 #define SSI_IC_TCIC BIT(4)
54 #define SSI_IC_RCIC BIT(3)
55 #define SSI_IC_RORIC BIT(0)
56
57 #define SSI_FC 0x20
58 #define SSI_FC_TXFFL BIT(12)
59 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
60 #define SSI_FC_RXFFL BIT(4)
61 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
62
63 #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
64
65 #define SSI_FIFO_DEPTH 8U
66
67 #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
68 #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
69
70 #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
71
72 struct uniphier_spi_plat {
73 void __iomem *base;
74 u32 frequency; /* input frequency */
75 u32 speed_hz;
76 uint deactivate_delay_us; /* Delay to wait after deactivate */
77 uint activate_delay_us; /* Delay to wait after activate */
78 };
79
80 struct uniphier_spi_priv {
81 void __iomem *base;
82 u8 mode;
83 u8 fifo_depth;
84 u8 bits_per_word;
85 ulong last_transaction_us; /* Time of last transaction end */
86 };
87
uniphier_spi_enable(struct uniphier_spi_priv * priv,int enable)88 static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
89 {
90 u32 val;
91
92 val = readl(priv->base + SSI_CTL);
93 if (enable)
94 val |= SSI_CTL_EN;
95 else
96 val &= ~SSI_CTL_EN;
97 writel(val, priv->base + SSI_CTL);
98 }
99
uniphier_spi_regdump(struct uniphier_spi_priv * priv)100 static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
101 {
102 pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
103 pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
104 pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
105 pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
106 pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
107 pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
108 pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
109 pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
110 pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
111 pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
112 }
113
spi_cs_activate(struct udevice * dev)114 static void spi_cs_activate(struct udevice *dev)
115 {
116 struct udevice *bus = dev->parent;
117 struct uniphier_spi_plat *plat = dev_get_plat(bus);
118 struct uniphier_spi_priv *priv = dev_get_priv(bus);
119 ulong delay_us; /* The delay completed so far */
120 u32 val;
121
122 /* If it's too soon to do another transaction, wait */
123 if (plat->deactivate_delay_us && priv->last_transaction_us) {
124 delay_us = timer_get_us() - priv->last_transaction_us;
125 if (delay_us < plat->deactivate_delay_us)
126 udelay(plat->deactivate_delay_us - delay_us);
127 }
128
129 val = readl(priv->base + SSI_FPS);
130 if (priv->mode & SPI_CS_HIGH)
131 val |= SSI_FPS_FSPOL;
132 else
133 val &= ~SSI_FPS_FSPOL;
134 writel(val, priv->base + SSI_FPS);
135
136 if (plat->activate_delay_us)
137 udelay(plat->activate_delay_us);
138 }
139
spi_cs_deactivate(struct udevice * dev)140 static void spi_cs_deactivate(struct udevice *dev)
141 {
142 struct udevice *bus = dev->parent;
143 struct uniphier_spi_plat *plat = dev_get_plat(bus);
144 struct uniphier_spi_priv *priv = dev_get_priv(bus);
145 u32 val;
146
147 val = readl(priv->base + SSI_FPS);
148 if (priv->mode & SPI_CS_HIGH)
149 val &= ~SSI_FPS_FSPOL;
150 else
151 val |= SSI_FPS_FSPOL;
152 writel(val, priv->base + SSI_FPS);
153
154 /* Remember time of this transaction so we can honour the bus delay */
155 if (plat->deactivate_delay_us)
156 priv->last_transaction_us = timer_get_us();
157 }
158
uniphier_spi_claim_bus(struct udevice * dev)159 static int uniphier_spi_claim_bus(struct udevice *dev)
160 {
161 struct udevice *bus = dev->parent;
162 struct uniphier_spi_priv *priv = dev_get_priv(bus);
163 u32 val, size;
164
165 uniphier_spi_enable(priv, false);
166
167 /* disable interrupts */
168 writel(0, priv->base + SSI_IE);
169
170 /* bits_per_word */
171 size = priv->bits_per_word;
172 val = readl(priv->base + SSI_TXWDS);
173 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
174 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
175 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
176 writel(val, priv->base + SSI_TXWDS);
177
178 val = readl(priv->base + SSI_RXWDS);
179 val &= ~SSI_RXWDS_DTLEN_MASK;
180 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
181 writel(val, priv->base + SSI_RXWDS);
182
183 /* reset FIFOs */
184 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
185 writel(val, priv->base + SSI_FC);
186
187 /* FIFO threthold */
188 val = readl(priv->base + SSI_FC);
189 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
190 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
191 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
192 writel(val, priv->base + SSI_FC);
193
194 /* clear interrupts */
195 writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
196 priv->base + SSI_IC);
197
198 uniphier_spi_enable(priv, true);
199
200 return 0;
201 }
202
uniphier_spi_release_bus(struct udevice * dev)203 static int uniphier_spi_release_bus(struct udevice *dev)
204 {
205 struct udevice *bus = dev->parent;
206 struct uniphier_spi_priv *priv = dev_get_priv(bus);
207
208 uniphier_spi_enable(priv, false);
209
210 return 0;
211 }
212
uniphier_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)213 static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
214 const void *dout, void *din, unsigned long flags)
215 {
216 struct udevice *bus = dev->parent;
217 struct uniphier_spi_priv *priv = dev_get_priv(bus);
218 const u8 *tx_buf = dout;
219 u8 *rx_buf = din, buf;
220 u32 len = bitlen / 8;
221 u32 tx_len, rx_len;
222 u32 ts, status;
223 int ret = 0;
224
225 if (bitlen % 8) {
226 dev_err(dev, "Non byte aligned SPI transfer\n");
227 return -EINVAL;
228 }
229
230 if (flags & SPI_XFER_BEGIN)
231 spi_cs_activate(dev);
232
233 uniphier_spi_enable(priv, true);
234
235 ts = get_timer(0);
236 tx_len = len;
237 rx_len = len;
238
239 uniphier_spi_regdump(priv);
240
241 while (tx_len || rx_len) {
242 ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
243 SSI_REG_TIMEOUT * 1000, false);
244 if (ret) {
245 if (ret == -ETIMEDOUT)
246 dev_err(dev, "access timeout\n");
247 break;
248 }
249
250 status = readl(priv->base + SSI_SR);
251 /* write the data into TX */
252 if (tx_len && (status & SSI_SR_TNF)) {
253 buf = tx_buf ? *tx_buf++ : 0;
254 writel(buf, priv->base + SSI_XDR);
255 tx_len--;
256 }
257
258 /* read the data from RX */
259 if (rx_len && (status & SSI_SR_RNE)) {
260 buf = readl(priv->base + SSI_XDR);
261 if (rx_buf)
262 *rx_buf++ = buf;
263 rx_len--;
264 }
265
266 if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
267 dev_err(dev, "transfer timeout\n");
268 ret = -ETIMEDOUT;
269 break;
270 }
271 }
272
273 if (flags & SPI_XFER_END)
274 spi_cs_deactivate(dev);
275
276 uniphier_spi_enable(priv, false);
277
278 return ret;
279 }
280
uniphier_spi_set_speed(struct udevice * bus,uint speed)281 static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
282 {
283 struct uniphier_spi_plat *plat = dev_get_plat(bus);
284 struct uniphier_spi_priv *priv = dev_get_priv(bus);
285 u32 val, ckdiv;
286
287 if (speed > plat->frequency)
288 speed = plat->frequency;
289
290 /* baudrate */
291 ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
292 ckdiv = round_up(ckdiv, 2);
293
294 val = readl(priv->base + SSI_CKS);
295 val &= ~SSI_CKS_CKRAT_MASK;
296 val |= ckdiv & SSI_CKS_CKRAT_MASK;
297 writel(val, priv->base + SSI_CKS);
298
299 return 0;
300 }
301
uniphier_spi_set_mode(struct udevice * bus,uint mode)302 static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
303 {
304 struct uniphier_spi_priv *priv = dev_get_priv(bus);
305 u32 val1, val2;
306
307 /*
308 * clock setting
309 * CKPHS capture timing. 0:rising edge, 1:falling edge
310 * CKINIT clock initial level. 0:low, 1:high
311 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
312 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
313 *
314 * frame setting
315 * FSPOL frame signal porarity. 0: low, 1: high
316 * FSTRT start frame timing
317 * 0: rising edge of clock, 1: falling edge of clock
318 */
319 val1 = readl(priv->base + SSI_CKS);
320 val2 = readl(priv->base + SSI_FPS);
321
322 switch (mode & (SPI_CPOL | SPI_CPHA)) {
323 case SPI_MODE_0:
324 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
325 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
326 val1 &= ~SSI_CKS_CKINIT;
327 val2 &= ~SSI_FPS_FSTRT;
328 break;
329 case SPI_MODE_1:
330 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
331 val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
332 val2 |= SSI_FPS_FSTRT;
333 break;
334 case SPI_MODE_2:
335 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
336 val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
337 val1 &= ~SSI_CKS_CKPHS;
338 val2 |= SSI_FPS_FSTRT;
339 break;
340 case SPI_MODE_3:
341 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
342 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
343 val1 &= ~SSI_CKS_CKDLY;
344 val2 &= ~SSI_FPS_FSTRT;
345 break;
346 }
347
348 writel(val1, priv->base + SSI_CKS);
349 writel(val2, priv->base + SSI_FPS);
350
351 /* format */
352 val1 = readl(priv->base + SSI_TXWDS);
353 val2 = readl(priv->base + SSI_RXWDS);
354 if (mode & SPI_LSB_FIRST) {
355 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
356 val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
357 }
358 writel(val1, priv->base + SSI_TXWDS);
359 writel(val2, priv->base + SSI_RXWDS);
360
361 priv->mode = mode;
362
363 return 0;
364 }
365
uniphier_spi_of_to_plat(struct udevice * bus)366 static int uniphier_spi_of_to_plat(struct udevice *bus)
367 {
368 struct uniphier_spi_plat *plat = dev_get_plat(bus);
369 const void *blob = gd->fdt_blob;
370 int node = dev_of_offset(bus);
371
372 plat->base = dev_read_addr_ptr(bus);
373
374 plat->frequency =
375 fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
376 plat->deactivate_delay_us =
377 fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
378 plat->activate_delay_us =
379 fdtdec_get_int(blob, node, "spi-activate-delay", 0);
380 plat->speed_hz = plat->frequency / 2;
381
382 return 0;
383 }
384
uniphier_spi_probe(struct udevice * bus)385 static int uniphier_spi_probe(struct udevice *bus)
386 {
387 struct uniphier_spi_plat *plat = dev_get_plat(bus);
388 struct uniphier_spi_priv *priv = dev_get_priv(bus);
389
390 priv->base = plat->base;
391 priv->fifo_depth = SSI_FIFO_DEPTH;
392 priv->bits_per_word = 8;
393
394 return 0;
395 }
396
397 static const struct dm_spi_ops uniphier_spi_ops = {
398 .claim_bus = uniphier_spi_claim_bus,
399 .release_bus = uniphier_spi_release_bus,
400 .xfer = uniphier_spi_xfer,
401 .set_speed = uniphier_spi_set_speed,
402 .set_mode = uniphier_spi_set_mode,
403 };
404
405 static const struct udevice_id uniphier_spi_ids[] = {
406 { .compatible = "socionext,uniphier-scssi" },
407 { /* Sentinel */ }
408 };
409
410 U_BOOT_DRIVER(uniphier_spi) = {
411 .name = "uniphier_spi",
412 .id = UCLASS_SPI,
413 .of_match = uniphier_spi_ids,
414 .ops = &uniphier_spi_ops,
415 .of_to_plat = uniphier_spi_of_to_plat,
416 .plat_auto = sizeof(struct uniphier_spi_plat),
417 .priv_auto = sizeof(struct uniphier_spi_priv),
418 .probe = uniphier_spi_probe,
419 };
420