1 /*
2 * Copyright (C) 2012 Renesas Solutions Corp.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <common.h>
24 #include <cpu_func.h>
25 #include <init.h>
26 #include <malloc.h>
27 #include <asm/global_data.h>
28 #include <asm/processor.h>
29 #include <asm/mach-types.h>
30 #include <asm/io.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/gpio.h>
33 #include <asm/arch/rmobile.h>
34
35 #define s_init_wait(cnt) \
36 ({ \
37 volatile u32 i = 0x10000 * cnt; \
38 while (i > 0) \
39 i--; \
40 })
41
42 #define USBCR1 0xE605810A
43
s_init(void)44 void s_init(void)
45 {
46 struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
47 struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
48 struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
49 struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
50 struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
51 struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
52
53 /* Watchdog init */
54 writew(0xA500, &rwdt0->rwtcsra0);
55 writew(0xA500, &rwdt1->rwtcsra0);
56
57 /* CPG */
58 writel(0xFF800080, &cpg->rmstpcr4);
59 writel(0xFF800080, &cpg->smstpcr4);
60
61 /* USB clock */
62 writel(0x00000080, &cpg->usbckcr);
63 s_init_wait(1);
64
65 /* USBCR1 */
66 writew(0x0710, USBCR1);
67
68 /* FRQCR */
69 writel(0x00000000, &cpg->frqcrb);
70 writel(0x62030533, &cpg->frqcra);
71 writel(0x208A354E, &cpg->frqcrc);
72 writel(0x80331050, &cpg->frqcrb);
73 s_init_wait(1);
74
75 writel(0x00000000, &cpg->frqcrd);
76 s_init_wait(1);
77
78 /* SUBClk */
79 writel(0x0000010B, &cpg->subckcr);
80
81 /* PLL */
82 writel(0x00004004, &cpg->pllc01cr);
83 s_init_wait(1);
84
85 writel(0xa0000000, &cpg->pllc2cr);
86 s_init_wait(2);
87
88 /* BSC */
89 writel(0x0000001B, &bsc->cmncr);
90
91 writel(0x20000000, &dbsc->dbcmd);
92 writel(0x10009C40, &dbsc->dbcmd);
93 s_init_wait(1);
94
95 writel(0x00000007, &dbsc->dbkind);
96 writel(0x0E030A02, &dbsc->dbconf0);
97 writel(0x00000001, &dbsc->dbphytype);
98 writel(0x00000000, &dbsc->dbbl);
99 writel(0x00000006, &dbsc->dbtr0);
100 writel(0x00000005, &dbsc->dbtr1);
101 writel(0x00000000, &dbsc->dbtr2);
102 writel(0x00000006, &dbsc->dbtr3);
103 writel(0x00080006, &dbsc->dbtr4);
104 writel(0x00000015, &dbsc->dbtr5);
105 writel(0x0000000f, &dbsc->dbtr6);
106 writel(0x00000004, &dbsc->dbtr7);
107 writel(0x00000018, &dbsc->dbtr8);
108 writel(0x00000006, &dbsc->dbtr9);
109 writel(0x00000006, &dbsc->dbtr10);
110 writel(0x0000000F, &dbsc->dbtr11);
111 writel(0x0000000D, &dbsc->dbtr12);
112 writel(0x000000A0, &dbsc->dbtr13);
113 writel(0x000A0003, &dbsc->dbtr14);
114 writel(0x00000003, &dbsc->dbtr15);
115 writel(0x40005005, &dbsc->dbtr16);
116 writel(0x0C0C0000, &dbsc->dbtr17);
117 writel(0x00000200, &dbsc->dbtr18);
118 writel(0x00000040, &dbsc->dbtr19);
119 writel(0x00000001, &dbsc->dbrnk0);
120 writel(0x00000110, &dbsc->dbdficnt);
121 writel(0x00000101, &ddrp->funcctrl);
122 writel(0x00000001, &ddrp->dllctrl);
123 writel(0x00000186, &ddrp->zqcalctrl);
124 writel(0xB3440051, &ddrp->zqodtctrl);
125 writel(0x94449443, &ddrp->rdctrl);
126 writel(0x000000C0, &ddrp->rdtmg);
127 writel(0x00000101, &ddrp->fifoinit);
128 writel(0x02060506, &ddrp->outctrl);
129 writel(0x00004646, &ddrp->dqcalofs1);
130 writel(0x00004646, &ddrp->dqcalofs2);
131 writel(0x800000aa, &ddrp->dqcalexp);
132 writel(0x00000000, &ddrp->dllctrl);
133 writel(0x00000000, DDRPNCNT);
134
135 writel(0x0000000C, &dbsc->dbcmd);
136 readl(&dbsc->dbwait);
137 s_init_wait(1);
138
139 writel(0x00000002, DDRPNCNT);
140
141 writel(0x0000000C, &dbsc->dbcmd);
142 readl(&dbsc->dbwait);
143 s_init_wait(1);
144
145 writel(0x00000187, &ddrp->zqcalctrl);
146
147 writel(0x00009C40, &dbsc->dbcmd);
148 readl(&dbsc->dbwait);
149 s_init_wait(1);
150
151 writel(0x00009C40, &dbsc->dbcmd);
152 readl(&dbsc->dbwait);
153 s_init_wait(1);
154
155 writel(0x00000010, &dbsc->dbdficnt);
156 writel(0x02060507, &ddrp->outctrl);
157
158 writel(0x00009C40, &dbsc->dbcmd);
159 readl(&dbsc->dbwait);
160 s_init_wait(1);
161
162 writel(0x21009C40, &dbsc->dbcmd);
163 readl(&dbsc->dbwait);
164 s_init_wait(1);
165
166 writel(0x00009C40, &dbsc->dbcmd);
167 readl(&dbsc->dbwait);
168 s_init_wait(1);
169
170 writel(0x00009C40, &dbsc->dbcmd);
171 readl(&dbsc->dbwait);
172 s_init_wait(1);
173
174 writel(0x00009C40, &dbsc->dbcmd);
175 readl(&dbsc->dbwait);
176 s_init_wait(1);
177
178 writel(0x00009C40, &dbsc->dbcmd);
179 readl(&dbsc->dbwait);
180 s_init_wait(1);
181
182 writel(0x11000044, &dbsc->dbcmd);
183 readl(&dbsc->dbwait);
184 s_init_wait(1);
185
186 writel(0x2A000000, &dbsc->dbcmd);
187 readl(&dbsc->dbwait);
188 s_init_wait(1);
189
190 writel(0x2B000000, &dbsc->dbcmd);
191 readl(&dbsc->dbwait);
192
193 writel(0x29000004, &dbsc->dbcmd);
194 readl(&dbsc->dbwait);
195
196 writel(0x28001520, &dbsc->dbcmd);
197 readl(&dbsc->dbwait);
198 s_init_wait(1);
199
200 writel(0x03000200, &dbsc->dbcmd);
201 readl(&dbsc->dbwait);
202 s_init_wait(1);
203
204 writel(0x000001FF, &dbsc->dbrfcnf0);
205 writel(0x00010C30, &dbsc->dbrfcnf1);
206 writel(0x00000000, &dbsc->dbrfcnf2);
207
208 writel(0x00000001, &dbsc->dbrfen);
209 writel(0x00000001, &dbsc->dbacen);
210
211 /* BSC */
212 writel(0x00410400, &bsc->cs0bcr);
213 writel(0x00410400, &bsc->cs2bcr);
214 writel(0x00410400, &bsc->cs5bbcr);
215 writel(0x02CB0400, &bsc->cs6abcr);
216
217 writel(0x00000440, &bsc->cs0wcr);
218 writel(0x00000440, &bsc->cs2wcr);
219 writel(0x00000240, &bsc->cs5bwcr);
220 writel(0x00000240, &bsc->cs6awcr);
221
222 writel(0x00000005, &bsc->rbwtcnt);
223 writel(0x00000002, &bsc->cs0wcr2);
224 writel(0x00000002, &bsc->cs2wcr2);
225 writel(0x00000002, &bsc->cs4wcr2);
226 }
227
228 #define GPIO_ICCR (0xE60581A0)
229 #define ICCR_15BIT (1 << 15) /* any time 1 */
230 #define IIC0_CONTA (1 << 7)
231 #define IIC0_CONTB (1 << 6)
232 #define IIC1_CONTA (1 << 5)
233 #define IIC1_CONTB (1 << 4)
234 #define IIC0_PS33E (1 << 1)
235 #define IIC1_PS33E (1 << 0)
236 #define GPIO_ICCR_DATA \
237 (ICCR_15BIT | \
238 IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
239 IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
240
241 #define MSTPCR1 0xE6150134
242 #define TMU0_MSTP125 (1 << 25)
243 #define I2C0_MSTP116 (1 << 16)
244
245 #define MSTPCR3 0xE615013C
246 #define I2C1_MSTP323 (1 << 23)
247 #define GETHER_MSTP309 (1 << 9)
248
249 #define GPIO_SCIFA1_TXD (0xE60520C4)
250 #define GPIO_SCIFA1_RXD (0xE60520C3)
251
board_early_init_f(void)252 int board_early_init_f(void)
253 {
254 /* TMU */
255 clrbits_le32(MSTPCR1, TMU0_MSTP125);
256
257 /* GETHER */
258 clrbits_le32(MSTPCR3, GETHER_MSTP309);
259
260 /* I2C 0/1 */
261 clrbits_le32(MSTPCR1, I2C0_MSTP116);
262 clrbits_le32(MSTPCR3, I2C1_MSTP323);
263
264 /* SCIFA1 */
265 writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
266 writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
267
268 /* IICCR */
269 writew(GPIO_ICCR_DATA, GPIO_ICCR);
270
271 return 0;
272 }
273
274 DECLARE_GLOBAL_DATA_PTR;
board_init(void)275 int board_init(void)
276 {
277 /* board id for linux */
278 gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
279 /* adress of boot parameters */
280 gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
281
282 /* Init PFC controller */
283 r8a7740_pinmux_init();
284
285 /* GETHER Enable */
286 gpio_request(GPIO_FN_ET_CRS, NULL);
287 gpio_request(GPIO_FN_ET_MDC, NULL);
288 gpio_request(GPIO_FN_ET_MDIO, NULL);
289 gpio_request(GPIO_FN_ET_TX_ER, NULL);
290 gpio_request(GPIO_FN_ET_RX_ER, NULL);
291 gpio_request(GPIO_FN_ET_ERXD0, NULL);
292 gpio_request(GPIO_FN_ET_ERXD1, NULL);
293 gpio_request(GPIO_FN_ET_ERXD2, NULL);
294 gpio_request(GPIO_FN_ET_ERXD3, NULL);
295 gpio_request(GPIO_FN_ET_TX_CLK, NULL);
296 gpio_request(GPIO_FN_ET_TX_EN, NULL);
297 gpio_request(GPIO_FN_ET_ETXD0, NULL);
298 gpio_request(GPIO_FN_ET_ETXD1, NULL);
299 gpio_request(GPIO_FN_ET_ETXD2, NULL);
300 gpio_request(GPIO_FN_ET_ETXD3, NULL);
301 gpio_request(GPIO_FN_ET_PHY_INT, NULL);
302 gpio_request(GPIO_FN_ET_COL, NULL);
303 gpio_request(GPIO_FN_ET_RX_DV, NULL);
304 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
305
306 gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
307 gpio_direction_output(GPIO_PORT18, 1);
308
309 return 0;
310 }
311
dram_init(void)312 int dram_init(void)
313 {
314 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
315 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
316
317 return 0;
318 }
319
board_late_init(void)320 int board_late_init(void)
321 {
322 return 0;
323 }
324
reset_cpu(void)325 void reset_cpu(void)
326 {
327 }
328