1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 4 * 5 * Based on original Kirkwood support which is 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 */ 10 11 #ifndef _CONFIG_EDMINIV2_H 12 #define _CONFIG_EDMINIV2_H 13 14 /* 15 * SPL 16 */ 17 18 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 19 #define CONFIG_SPL_STACK 0x00020000 20 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 21 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 22 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 23 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 24 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 25 #define CONFIG_SYS_UBOOT_START 0x00800000 26 27 /* 28 * High Level Configuration Options (easy to change) 29 */ 30 31 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 32 #define CONFIG_88F5182 1 /* SOC Name */ 33 34 #include <asm/arch/orion5x.h> 35 /* 36 * CLKs configurations 37 */ 38 39 /* 40 * Board-specific values for Orion5x MPP low level init: 41 * - MPPs 12 to 15 are SATA LEDs (mode 5) 42 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 43 * MPP16 to MPP19, mode 0 for others 44 */ 45 46 #define ORION5X_MPP0_7 0x00000003 47 #define ORION5X_MPP8_15 0x55550000 48 #define ORION5X_MPP16_23 0x00005555 49 50 /* 51 * Board-specific values for Orion5x GPIO low level init: 52 * - GPIO3 is input (RTC interrupt) 53 * - GPIO16 is Power LED control (0 = on, 1 = off) 54 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 55 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 56 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 57 * - GPIO22 is SATA disk power status () 58 * - GPIO23 is supply status for SATA disk () 59 * - GPIO24 is supply control for board (write 1 to power off) 60 * Last GPIO is 25, further bits are supposed to be 0. 61 * Enable mask has ones for INPUT, 0 for OUTPUT. 62 * Default is LED ON, board ON :) 63 */ 64 65 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 66 #define ORION5X_GPIO_OUT_VALUE 0x00000000 67 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 68 69 /* 70 * NS16550 Configuration 71 */ 72 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 76 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 77 78 /* 79 * Serial Port configuration 80 * The following definitions let you select what serial you want to use 81 * for your console driver. 82 */ 83 84 #define CONFIG_SYS_BAUDRATE_TABLE \ 85 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 86 87 /* 88 * FLASH configuration 89 */ 90 91 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 92 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 93 #define CONFIG_SYS_FLASH_BASE 0xfff80000 94 95 /* auto boot */ 96 97 /* 98 * For booting Linux, the board info and command line data 99 * have to be in the first 8 MB of memory, since this is 100 * the maximum mapped by the Linux kernel during initialization. 101 */ 102 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 103 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 104 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 105 106 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 107 108 /* 109 * Network 110 */ 111 112 #ifdef CONFIG_CMD_NET 113 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 114 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 115 #define CONFIG_PHY_BASE_ADR 0x8 116 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 117 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 118 #endif 119 120 /* 121 * IDE 122 */ 123 #ifdef CONFIG_IDE 124 #define __io 125 /* Needs byte-swapping for ATA data register */ 126 #define CONFIG_IDE_SWAP_IO 127 /* Data, registers and alternate blocks are at the same offset */ 128 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 129 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 130 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 131 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 132 #define CONFIG_SYS_ATA_STRIDE 4 133 /* Controller supports 48-bits LBA addressing */ 134 #define CONFIG_LBA48 135 /* A single bus, a single device */ 136 #define CONFIG_SYS_IDE_MAXBUS 1 137 #define CONFIG_SYS_IDE_MAXDEVICE 1 138 /* ATA registers base is at SATA controller base */ 139 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 140 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 141 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 142 /* end of IDE defines */ 143 #endif /* CMD_IDE */ 144 145 /* 146 * Common USB/EHCI configuration 147 */ 148 #ifdef CONFIG_CMD_USB 149 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 150 #endif /* CONFIG_CMD_USB */ 151 152 /* 153 * I2C related stuff 154 */ 155 #ifdef CONFIG_CMD_I2C 156 #define CONFIG_SYS_I2C 157 #define CONFIG_SYS_I2C_MVTWSI 158 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 159 #define CONFIG_SYS_I2C_SLAVE 0x0 160 #define CONFIG_SYS_I2C_SPEED 100000 161 #endif 162 163 /* 164 * Environment variables configurations 165 */ 166 167 /* 168 * Size of malloc() pool 169 */ 170 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 171 172 /* 173 * Other required minimal configurations 174 */ 175 176 #define CONFIG_SYS_LOAD_ADDR 0x00800000 177 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 178 179 /* Enable command line editing */ 180 181 /* provide extensive help */ 182 183 /* additions for new relocation code, must be added to all boards */ 184 #define CONFIG_SYS_SDRAM_BASE 0 185 #define CONFIG_SYS_INIT_SP_ADDR \ 186 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 187 188 #endif /* _CONFIG_EDMINIV2_H */ 189