1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __T4QDS_H 10 #define __T4QDS_H 11 12 /* High Level Configuration Options */ 13 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 14 15 #ifndef CONFIG_RESET_VECTOR_ADDRESS 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17 #endif 18 19 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 20 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 21 #define CONFIG_PCIE1 /* PCIE controller 1 */ 22 #define CONFIG_PCIE2 /* PCIE controller 2 */ 23 #define CONFIG_PCIE3 /* PCIE controller 3 */ 24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 25 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 26 27 #define CONFIG_SYS_SRIO 28 #define CONFIG_SRIO1 /* SRIO port 1 */ 29 #define CONFIG_SRIO2 /* SRIO port 2 */ 30 31 /* 32 * These can be toggled for performance analysis, otherwise use default. 33 */ 34 #define CONFIG_SYS_CACHE_STASHING 35 #define CONFIG_BTB /* toggle branch predition */ 36 #ifdef CONFIG_DDR_ECC 37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #endif 40 41 #define CONFIG_ENABLE_36BIT_PHYS 42 43 /* 44 * Config the L3 Cache as L3 SRAM 45 */ 46 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 47 #define CONFIG_SYS_L3_SIZE (512 << 10) 48 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 49 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 50 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 51 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 52 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 53 54 #define CONFIG_SYS_DCSRBAR 0xf0000000 55 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 56 57 /* 58 * DDR Setup 59 */ 60 #define CONFIG_VERY_BIG_RAM 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 65 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 66 67 #define CONFIG_DDR_SPD 68 69 /* 70 * IFC Definitions 71 */ 72 #define CONFIG_SYS_FLASH_BASE 0xe0000000 73 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 74 75 #ifdef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 77 #else 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 79 #endif 80 81 #define CONFIG_HWCONFIG 82 83 /* define to use L1 as initial stack */ 84 #define CONFIG_L1_INIT_RAM 85 #define CONFIG_SYS_INIT_RAM_LOCK 86 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 87 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 88 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 89 /* The assembler doesn't like typecast */ 90 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 91 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 92 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 93 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 94 95 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 96 GENERATED_GBL_DATA_SIZE) 97 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 98 99 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 100 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 101 102 /* Serial Port - controlled on board with jumper J8 103 * open - index 2 104 * shorted - index 1 105 */ 106 #define CONFIG_SYS_NS16550_SERIAL 107 #define CONFIG_SYS_NS16550_REG_SIZE 1 108 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 109 110 #define CONFIG_SYS_BAUDRATE_TABLE \ 111 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 112 113 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 114 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 115 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 116 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 117 118 /* I2C */ 119 #define CONFIG_SYS_I2C 120 #define CONFIG_SYS_I2C_FSL 121 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 122 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 123 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 124 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 125 126 /* 127 * RapidIO 128 */ 129 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 130 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 131 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 132 133 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 134 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 135 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 136 137 /* 138 * General PCI 139 * Memory space is mapped 1-1, but I/O space must start from 0. 140 */ 141 142 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 143 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 144 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 145 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 146 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 147 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 148 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 149 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 150 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 151 152 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 153 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 154 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 155 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 156 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 157 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 158 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 159 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 160 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 161 162 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 163 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 164 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 165 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 166 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 167 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 168 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 169 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 170 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 171 172 /* controller 4, Base address 203000 */ 173 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 174 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 175 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 176 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 177 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 178 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 179 180 #ifdef CONFIG_PCI 181 #define CONFIG_PCI_INDIRECT_BRIDGE 182 183 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 184 #endif /* CONFIG_PCI */ 185 186 /* SATA */ 187 #ifdef CONFIG_FSL_SATA_V2 188 #define CONFIG_SYS_SATA_MAX_DEVICE 2 189 #define CONFIG_SATA1 190 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 191 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 192 #define CONFIG_SATA2 193 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 194 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 195 196 #define CONFIG_LBA48 197 #endif 198 199 #ifdef CONFIG_FMAN_ENET 200 #define CONFIG_ETHPRIME "FM1@DTSEC1" 201 #endif 202 203 /* 204 * Environment 205 */ 206 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 207 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 208 209 /* 210 * Miscellaneous configurable options 211 */ 212 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 213 214 /* 215 * For booting Linux, the board info and command line data 216 * have to be in the first 64 MB of memory, since this is 217 * the maximum mapped by the Linux kernel during initialization. 218 */ 219 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 220 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 221 222 #ifdef CONFIG_CMD_KGDB 223 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 224 #endif 225 226 /* 227 * Environment Configuration 228 */ 229 #define CONFIG_ROOTPATH "/opt/nfsroot" 230 #define CONFIG_BOOTFILE "uImage" 231 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 232 233 /* default location for tftp and bootm */ 234 #define CONFIG_LOADADDR 1000000 235 236 #define CONFIG_HVBOOT \ 237 "setenv bootargs config-addr=0x60000000; " \ 238 "bootm 0x01000000 - 0x00f00000" 239 240 #endif /* __CONFIG_H */ 241