1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 */
7
8 #include <common.h>
9 #include <clock_legacy.h>
10 #include <asm/global_data.h>
11 #include <asm/processor.h>
12
13 #include <asm/immap.h>
14 #include <asm/io.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /*
19 * Low Power Divider specifications
20 */
21 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
22 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
23
24 #define CLOCK_PLL_FVCO_MAX 540000000
25 #define CLOCK_PLL_FVCO_MIN 300000000
26
27 #define CLOCK_PLL_FSYS_MAX 266666666
28 #define CLOCK_PLL_FSYS_MIN 100000000
29 #define MHZ 1000000
30
clock_enter_limp(int lpdiv)31 void clock_enter_limp(int lpdiv)
32 {
33 ccm_t *ccm = (ccm_t *)MMAP_CCM;
34 int i, j;
35
36 /* Check bounds of divider */
37 if (lpdiv < CLOCK_LPD_MIN)
38 lpdiv = CLOCK_LPD_MIN;
39 if (lpdiv > CLOCK_LPD_MAX)
40 lpdiv = CLOCK_LPD_MAX;
41
42 /* Round divider down to nearest power of two */
43 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
44
45 /* Apply the divider to the system clock */
46 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
47
48 /* Enable Limp Mode */
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
50 }
51
52 /*
53 * brief Exit Limp mode
54 * warning The PLL should be set and locked prior to exiting Limp mode
55 */
clock_exit_limp(void)56 void clock_exit_limp(void)
57 {
58 ccm_t *ccm = (ccm_t *)MMAP_CCM;
59 pll_t *pll = (pll_t *)MMAP_PLL;
60
61 /* Exit Limp mode */
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
63
64 /* Wait for the PLL to lock */
65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
66 ;
67 }
68
69 /*
70 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
71 */
get_clocks(void)72 int get_clocks(void)
73 {
74
75 ccm_t *ccm = (ccm_t *)MMAP_CCM;
76 pll_t *pll = (pll_t *)MMAP_PLL;
77 int vco, temp, pcrvalue, pfdr;
78 u8 bootmode;
79
80 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
81 pfdr = pcrvalue >> 24;
82
83 if (pfdr == 0x1E)
84 bootmode = 0; /* Normal Mode */
85
86 #ifdef CONFIG_CF_SBF
87 bootmode = 3; /* Serial Mode */
88 #endif
89
90 if (bootmode == 0) {
91 /* Normal mode */
92 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
93 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
94 /* Default value */
95 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
96 pcrvalue |= 0x1E << 24;
97 out_be32(&pll->pcr, pcrvalue);
98 vco =
99 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
100 CONFIG_SYS_INPUT_CLKSRC;
101 }
102 gd->arch.vco_clk = vco; /* Vco clock */
103 } else if (bootmode == 3) {
104 /* serial mode */
105 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
106 gd->arch.vco_clk = vco; /* Vco clock */
107 }
108
109 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
110 /* Limp mode */
111 } else {
112 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
113
114 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
115 gd->cpu_clk = vco / temp; /* cpu clock */
116
117 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
118 gd->arch.flb_clk = vco / temp; /* flexbus clock */
119 gd->bus_clk = gd->arch.flb_clk;
120 }
121
122 #ifdef CONFIG_SYS_I2C_FSL
123 gd->arch.i2c1_clk = gd->bus_clk;
124 #endif
125
126 return (0);
127 }
128