1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_SECURE_BOOT_H 7 #define __FSL_SECURE_BOOT_H 8 #include <asm/config_mpc85xx.h> 9 10 #ifdef CONFIG_NXP_ESBC 11 #if defined(CONFIG_FSL_CORENET) 12 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 13 #elif defined(CONFIG_TARGET_BSC9132QDS) 14 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 15 #elif defined(CONFIG_TARGET_C29XPCIE) 16 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 17 #else 18 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 19 #endif 20 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 21 22 #if defined(CONFIG_TARGET_B4860QDS) || \ 23 defined(CONFIG_TARGET_B4420QDS) || \ 24 defined(CONFIG_TARGET_T4160QDS) || \ 25 defined(CONFIG_TARGET_T4240QDS) || \ 26 defined(CONFIG_TARGET_T2080QDS) || \ 27 defined(CONFIG_TARGET_T2080RDB) || \ 28 defined(CONFIG_TARGET_T1040RDB) || \ 29 defined(CONFIG_TARGET_T1040D4RDB) || \ 30 defined(CONFIG_TARGET_T1042RDB) || \ 31 defined(CONFIG_TARGET_T1042D4RDB) || \ 32 defined(CONFIG_TARGET_T1042RDB_PI) || \ 33 defined(CONFIG_ARCH_T1023) || \ 34 defined(CONFIG_ARCH_T1024) 35 #ifndef CONFIG_SYS_RAMBOOT 36 #define CONFIG_SYS_CPC_REINIT_F 37 #endif 38 #define CONFIG_KEY_REVOCATION 39 #undef CONFIG_SYS_INIT_L3_ADDR 40 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 41 #endif 42 43 #if defined(CONFIG_RAMBOOT_PBL) 44 #undef CONFIG_SYS_INIT_L3_ADDR 45 #ifdef CONFIG_SYS_INIT_L3_VADDR 46 #define CONFIG_SYS_INIT_L3_ADDR \ 47 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 48 0xbff00000 49 #else 50 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 51 #endif 52 #endif 53 54 #if defined(CONFIG_TARGET_C29XPCIE) 55 #define CONFIG_KEY_REVOCATION 56 #endif 57 58 #if defined(CONFIG_ARCH_P3041) || \ 59 defined(CONFIG_ARCH_P4080) || \ 60 defined(CONFIG_ARCH_P5040) || \ 61 defined(CONFIG_ARCH_P2041) 62 #define CONFIG_FSL_TRUST_ARCH_v1 63 #endif 64 65 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) 66 /* The key used for verification of next level images 67 * is picked up from an Extension Table which has 68 * been verified by the ISBC (Internal Secure boot Code) 69 * in boot ROM of the SoC. 70 * The feature is only applicable in case of NOR boot and is 71 * not applicable in case of RAMBOOT (NAND, SD, SPI). 72 */ 73 #define CONFIG_FSL_ISBC_KEY_EXT 74 #endif 75 #endif /* #ifdef CONFIG_NXP_ESBC */ 76 77 #ifdef CONFIG_CHAIN_OF_TRUST 78 #ifdef CONFIG_SPL_BUILD 79 /* 80 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init 81 * due to space crunch on CPC and thus malloc will not work. 82 */ 83 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 84 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 85 #define CONFIG_SPL_JR0_LIODN_S 454 86 #define CONFIG_SPL_JR0_LIODN_NS 458 87 /* 88 * Define the key hash for U-Boot here if public/private key pair used to 89 * sign U-boot are different from the SRK hash put in the fuse 90 * Example of defining KEY_HASH is 91 * #define CONFIG_SPL_UBOOT_KEY_HASH \ 92 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 93 * else leave it defined as NULL 94 */ 95 96 #define CONFIG_SPL_UBOOT_KEY_HASH NULL 97 #endif /* ifdef CONFIG_SPL_BUILD */ 98 99 #define CONFIG_FSL_SEC_MON 100 101 #ifndef CONFIG_SPL_BUILD 102 /* 103 * fsl_setenv_chain_of_trust() must be called from 104 * board_late_init() 105 */ 106 107 /* If Boot Script is not on NOR and is required to be copied on RAM */ 108 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 109 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 110 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 111 #define CONFIG_BS_HDR_SIZE 0x00002000 112 #define CONFIG_BS_ADDR_RAM 0x00012000 113 #define CONFIG_BS_ADDR_DEVICE 0x00802000 114 #define CONFIG_BS_SIZE 0x00001000 115 116 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 117 #else 118 119 /* The bootscript header address is different for B4860 because the NOR 120 * mapping is different on B4 due to reduced NOR size. 121 */ 122 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) 123 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 124 #elif defined(CONFIG_FSL_CORENET) 125 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 126 #elif defined(CONFIG_TARGET_BSC9132QDS) 127 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 128 #elif defined(CONFIG_TARGET_C29XPCIE) 129 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 130 #else 131 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 132 #endif 133 134 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ 135 136 #include <config_fsl_chain_trust.h> 137 #endif /* #ifndef CONFIG_SPL_BUILD */ 138 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 139 #endif 140