1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6 #ifndef NIC_REG_H 7 #define NIC_REG_H 8 9 #define NIC_PF_REG_COUNT 29573 10 #define NIC_VF_REG_COUNT 249 11 12 /* Physical function register offsets */ 13 #define NIC_PF_CFG (0x0000) 14 #define NIC_PF_STATUS (0x0010) 15 16 #define NIC_PF_INTR_TIMER_CFG (0x0030) 17 #define NIC_PF_BIST_STATUS (0x0040) 18 #define NIC_PF_SOFT_RESET (0x0050) 19 20 #define NIC_PF_TCP_TIMER (0x0060) 21 #define NIC_PF_BP_CFG (0x0080) 22 #define NIC_PF_RRM_CFG (0x0088) 23 #define NIC_PF_CQM_CF (0x00A0) 24 #define NIC_PF_CNM_CF (0x00A8) 25 #define NIC_PF_CNM_STATUS (0x00B0) 26 #define NIC_PF_CQ_AVG_CFG (0x00C0) 27 #define NIC_PF_RRM_AVG_CFG (0x00C8) 28 29 #define NIC_PF_INTF_0_1_SEND_CFG (0x0200) 30 #define NIC_PF_INTF_0_1_BP_CFG (0x0208) 31 #define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210) 32 #define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220) 33 #define NIC_PF_RBDR_BP_STATE_0_3 (0x0240) 34 35 #define NIC_PF_MAILBOX_INT (0x0410) 36 #define NIC_PF_MAILBOX_INT_W1S (0x0430) 37 #define NIC_PF_MAILBOX_ENA_W1C (0x0450) 38 #define NIC_PF_MAILBOX_ENA_W1S (0x0470) 39 40 #define NIC_PF_RX_ETYPE_0_7 (0x0500) 41 #define NIC_PF_RX_CFG (0x05D0) 42 #define NIC_PF_PKIND_0_15_CFG (0x0600) 43 44 #define NIC_PF_ECC0_FLIP0 (0x1000) 45 #define NIC_PF_ECC1_FLIP0 (0x1008) 46 #define NIC_PF_ECC2_FLIP0 (0x1010) 47 #define NIC_PF_ECC3_FLIP0 (0x1018) 48 #define NIC_PF_ECC0_FLIP1 (0x1080) 49 #define NIC_PF_ECC1_FLIP1 (0x1088) 50 #define NIC_PF_ECC2_FLIP1 (0x1090) 51 #define NIC_PF_ECC3_FLIP1 (0x1098) 52 #define NIC_PF_ECC0_CDIS (0x1100) 53 #define NIC_PF_ECC1_CDIS (0x1108) 54 #define NIC_PF_ECC2_CDIS (0x1110) 55 #define NIC_PF_ECC3_CDIS (0x1118) 56 #define NIC_PF_BIST0_STATUS (0x1280) 57 #define NIC_PF_BIST1_STATUS (0x1288) 58 #define NIC_PF_BIST2_STATUS (0x1290) 59 #define NIC_PF_BIST3_STATUS (0x1298) 60 61 #define NIC_PF_ECC0_SBE_INT (0x2000) 62 #define NIC_PF_ECC0_SBE_INT_W1S (0x2008) 63 #define NIC_PF_ECC0_SBE_ENA_W1C (0x2010) 64 #define NIC_PF_ECC0_SBE_ENA_W1S (0x2018) 65 #define NIC_PF_ECC0_DBE_INT (0x2100) 66 #define NIC_PF_ECC0_DBE_INT_W1S (0x2108) 67 #define NIC_PF_ECC0_DBE_ENA_W1C (0x2110) 68 #define NIC_PF_ECC0_DBE_ENA_W1S (0x2118) 69 70 #define NIC_PF_ECC1_SBE_INT (0x2200) 71 #define NIC_PF_ECC1_SBE_INT_W1S (0x2208) 72 #define NIC_PF_ECC1_SBE_ENA_W1C (0x2210) 73 #define NIC_PF_ECC1_SBE_ENA_W1S (0x2218) 74 #define NIC_PF_ECC1_DBE_INT (0x2300) 75 #define NIC_PF_ECC1_DBE_INT_W1S (0x2308) 76 #define NIC_PF_ECC1_DBE_ENA_W1C (0x2310) 77 #define NIC_PF_ECC1_DBE_ENA_W1S (0x2318) 78 79 #define NIC_PF_ECC2_SBE_INT (0x2400) 80 #define NIC_PF_ECC2_SBE_INT_W1S (0x2408) 81 #define NIC_PF_ECC2_SBE_ENA_W1C (0x2410) 82 #define NIC_PF_ECC2_SBE_ENA_W1S (0x2418) 83 #define NIC_PF_ECC2_DBE_INT (0x2500) 84 #define NIC_PF_ECC2_DBE_INT_W1S (0x2508) 85 #define NIC_PF_ECC2_DBE_ENA_W1C (0x2510) 86 #define NIC_PF_ECC2_DBE_ENA_W1S (0x2518) 87 88 #define NIC_PF_ECC3_SBE_INT (0x2600) 89 #define NIC_PF_ECC3_SBE_INT_W1S (0x2608) 90 #define NIC_PF_ECC3_SBE_ENA_W1C (0x2610) 91 #define NIC_PF_ECC3_SBE_ENA_W1S (0x2618) 92 #define NIC_PF_ECC3_DBE_INT (0x2700) 93 #define NIC_PF_ECC3_DBE_INT_W1S (0x2708) 94 #define NIC_PF_ECC3_DBE_ENA_W1C (0x2710) 95 #define NIC_PF_ECC3_DBE_ENA_W1S (0x2718) 96 97 #define NIC_PF_CPI_0_2047_CFG (0x200000) 98 #define NIC_PF_MPI_0_2047_CFG (0x210000) 99 #define NIC_PF_RSSI_0_4097_RQ (0x220000) 100 #define NIC_PF_LMAC_0_7_CFG (0x240000) 101 #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000) 102 #define NIC_PF_LMAC_0_7_CREDIT (0x244000) 103 #define NIC_PF_CHAN_0_255_TX_CFG (0x400000) 104 #define NIC_PF_CHAN_0_255_RX_CFG (0x420000) 105 #define NIC_PF_CHAN_0_255_SW_XOFF (0x440000) 106 #define NIC_PF_CHAN_0_255_CREDIT (0x460000) 107 #define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000) 108 109 #define NIC_PF_SW_SYNC_RX (0x490000) 110 111 #define NIC_PF_SW_SYNC_RX_DONE (0x490008) 112 #define NIC_PF_TL2_0_63_CFG (0x500000) 113 #define NIC_PF_TL2_0_63_PRI (0x520000) 114 #define NIC_PF_TL2_LMAC (0x540000) 115 #define NIC_PF_TL2_0_63_SH_STATUS (0x580000) 116 #define NIC_PF_TL3A_0_63_CFG (0x5F0000) 117 #define NIC_PF_TL3_0_255_CFG (0x600000) 118 #define NIC_PF_TL3_0_255_CHAN (0x620000) 119 #define NIC_PF_TL3_0_255_PIR (0x640000) 120 #define NIC_PF_TL3_0_255_SW_XOFF (0x660000) 121 #define NIC_PF_TL3_0_255_CNM_RATE (0x680000) 122 #define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000) 123 #define NIC_PF_TL4A_0_255_CFG (0x6F0000) 124 #define NIC_PF_TL4_0_1023_CFG (0x800000) 125 #define NIC_PF_TL4_0_1023_SW_XOFF (0x820000) 126 #define NIC_PF_TL4_0_1023_SH_STATUS (0x840000) 127 #define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000) 128 #define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000) 129 130 #define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030) 131 #define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000) 132 #define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100) 133 #define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000) 134 #define NIC_PF_QSET_0_127_CFG (0x20010000) 135 #define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400) 136 #define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420) 137 #define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500) 138 #define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600) 139 #define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00) 140 #define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08) 141 #define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00) 142 143 #define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000) 144 #define NIC_PF_MSIX_VEC_0_CTL (0x000008) 145 #define NIC_PF_MSIX_PBA_0 (0x0F0000) 146 147 /* Virtual function register offsets */ 148 #define NIC_VNIC_CFG (0x000020) 149 #define NIC_VF_PF_MAILBOX_0_1 (0x000130) 150 #define NIC_VF_INT (0x000200) 151 #define NIC_VF_INT_W1S (0x000220) 152 #define NIC_VF_ENA_W1C (0x000240) 153 #define NIC_VF_ENA_W1S (0x000260) 154 155 #define NIC_VNIC_RSS_CFG (0x0020E0) 156 #define NIC_VNIC_RSS_KEY_0_4 (0x002200) 157 #define NIC_VNIC_TX_STAT_0_4 (0x004000) 158 #define NIC_VNIC_RX_STAT_0_13 (0x004100) 159 #define NIC_QSET_RQ_GEN_CFG (0x010010) 160 161 #define NIC_QSET_CQ_0_7_CFG (0x010400) 162 #define NIC_QSET_CQ_0_7_CFG2 (0x010408) 163 #define NIC_QSET_CQ_0_7_THRESH (0x010410) 164 #define NIC_QSET_CQ_0_7_BASE (0x010420) 165 #define NIC_QSET_CQ_0_7_HEAD (0x010428) 166 #define NIC_QSET_CQ_0_7_TAIL (0x010430) 167 #define NIC_QSET_CQ_0_7_DOOR (0x010438) 168 #define NIC_QSET_CQ_0_7_STATUS (0x010440) 169 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448) 170 #define NIC_QSET_CQ_0_7_DEBUG (0x010450) 171 172 #define NIC_QSET_RQ_0_7_CFG (0x010600) 173 #define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700) 174 175 #define NIC_QSET_SQ_0_7_CFG (0x010800) 176 #define NIC_QSET_SQ_0_7_THRESH (0x010810) 177 #define NIC_QSET_SQ_0_7_BASE (0x010820) 178 #define NIC_QSET_SQ_0_7_HEAD (0x010828) 179 #define NIC_QSET_SQ_0_7_TAIL (0x010830) 180 #define NIC_QSET_SQ_0_7_DOOR (0x010838) 181 #define NIC_QSET_SQ_0_7_STATUS (0x010840) 182 #define NIC_QSET_SQ_0_7_DEBUG (0x010848) 183 #define NIC_QSET_SQ_0_7_CNM_CHG (0x010860) 184 #define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900) 185 186 #define NIC_QSET_RBDR_0_1_CFG (0x010C00) 187 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10) 188 #define NIC_QSET_RBDR_0_1_BASE (0x010C20) 189 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28) 190 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30) 191 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38) 192 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40) 193 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48) 194 #define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50) 195 196 #define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000) 197 #define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008) 198 #define NIC_VF_MSIX_PBA (0x0F0000) 199 200 /* Offsets within registers */ 201 #define NIC_MSIX_VEC_SHIFT 4 202 #define NIC_Q_NUM_SHIFT 18 203 #define NIC_QS_ID_SHIFT 21 204 #define NIC_VF_NUM_SHIFT 21 205 206 /* Port kind configuration register */ 207 struct pkind_cfg { 208 #if defined(__BIG_ENDIAN_BITFIELD) 209 uint64_t reserved_42_63:22; 210 uint64_t hdr_sl:5; /* Header skip length */ 211 uint64_t rx_hdr:3; /* TNS Receive header present */ 212 uint64_t lenerr_en:1; /* L2 length error check enable */ 213 uint64_t reserved_32_32:1; 214 uint64_t maxlen:16; /* Max frame size */ 215 uint64_t minlen:16; /* Min frame size */ 216 #elif defined(__LITTLE_ENDIAN_BITFIELD) 217 uint64_t minlen:16; 218 uint64_t maxlen:16; 219 uint64_t reserved_32_32:1; 220 uint64_t lenerr_en:1; 221 uint64_t rx_hdr:3; 222 uint64_t hdr_sl:5; 223 uint64_t reserved_42_63:22; 224 #endif 225 }; 226 227 static inline uint64_t BGXX_PF_BAR0(unsigned long param1) 228 __attribute__ ((pure, always_inline)); BGXX_PF_BAR0(unsigned long param1)229static inline uint64_t BGXX_PF_BAR0(unsigned long param1) 230 { 231 assert(param1 <= 1); 232 return 0x87E0E0000000 + (param1 << 24); 233 } 234 235 #define BGXX_PF_BAR0_SIZE 0x400000 236 #define NIC_PF_BAR0 0x843000000000 237 #define NIC_PF_BAR0_SIZE 0x40000000 238 239 static inline uint64_t NIC_VFX_BAR0(unsigned long param1) 240 __attribute__ ((pure, always_inline)); NIC_VFX_BAR0(unsigned long param1)241static inline uint64_t NIC_VFX_BAR0(unsigned long param1) 242 { 243 assert(param1 <= 127); 244 245 return 0x8430A0000000 + (param1 << 21); 246 } 247 248 #define NIC_VFX_BAR0_SIZE 0x200000 249 250 #endif /* NIC_REG_H */ 251