1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Samsung Electronics
4 * Przemyslaw Marczak <p.marczak@samsung.com>
5 */
6
7 #include <common.h>
8 #include <log.h>
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/power.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/global_data.h>
14 #include <asm/gpio.h>
15 #include <asm/arch/cpu.h>
16 #include <dm.h>
17 #include <env.h>
18 #include <power/pmic.h>
19 #include <power/regulator.h>
20 #include <power/max77686_pmic.h>
21 #include <errno.h>
22 #include <mmc.h>
23 #include <usb.h>
24 #include <usb/dwc2_udc.h>
25 #include <samsung/misc.h>
26 #include "setup.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #ifdef CONFIG_BOARD_TYPES
31 /* Odroid board types */
32 enum {
33 ODROID_TYPE_U3,
34 ODROID_TYPE_X2,
35 ODROID_TYPES,
36 };
37
set_board_type(void)38 void set_board_type(void)
39 {
40 /* Set GPA1 pin 1 to HI - enable XCL205 output */
41 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
42 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
43 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
44 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
45
46 /* Set GPC1 pin 2 to IN - check XCL205 output state */
47 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
48 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
49
50 /* XCL205 - needs some latch time */
51 sdelay(200000);
52
53 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
54 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
55 gd->board_type = ODROID_TYPE_X2;
56 else
57 gd->board_type = ODROID_TYPE_U3;
58 }
59
set_board_revision(void)60 void set_board_revision(void)
61 {
62 /*
63 * Revision already set by set_board_type() because it can be
64 * executed early.
65 */
66 }
67
get_board_type(void)68 const char *get_board_type(void)
69 {
70 const char *board_type[] = {"u3", "x2"};
71
72 return board_type[gd->board_type];
73 }
74 #endif
75
76 #ifdef CONFIG_SET_DFU_ALT_INFO
get_dfu_alt_system(char * interface,char * devstr)77 char *get_dfu_alt_system(char *interface, char *devstr)
78 {
79 return env_get("dfu_alt_system");
80 }
81
get_dfu_alt_boot(char * interface,char * devstr)82 char *get_dfu_alt_boot(char *interface, char *devstr)
83 {
84 struct mmc *mmc;
85 char *alt_boot;
86 int dev_num;
87
88 dev_num = simple_strtoul(devstr, NULL, 10);
89
90 mmc = find_mmc_device(dev_num);
91 if (!mmc)
92 return NULL;
93
94 if (mmc_init(mmc))
95 return NULL;
96
97 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
98 CONFIG_DFU_ALT_BOOT_EMMC;
99
100 return alt_boot;
101 }
102 #endif
103
board_clock_init(void)104 static void board_clock_init(void)
105 {
106 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
107 struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
108 samsung_get_base_clock();
109
110 /*
111 * CMU_CPU clocks src to MPLL
112 * Bit values: 0 ; 1
113 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
114 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
115 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
116 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
117 */
118 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
119 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
120 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
121 MUX_MPLL_USER_SEL_C(1);
122
123 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
124
125 /* Wait for mux change */
126 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
127 continue;
128
129 /* Set APLL to 1000MHz */
130 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
131 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
132
133 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
134
135 /* Wait for PLL to be locked */
136 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
137 continue;
138
139 /* Set CMU_CPU clocks src to APLL */
140 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
141 MUX_MPLL_USER_SEL_C(1);
142 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
143
144 /* Wait for mux change */
145 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
146 continue;
147
148 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
149 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
150 APLL_RATIO(0) | CORE2_RATIO(0);
151 /*
152 * Set dividers for MOUTcore = 1000 MHz
153 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
154 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
155 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
156 * periph = armclk / (ratio + 1) = 1000 MHz (0)
157 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
158 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
159 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
160 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
161 */
162 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
163 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
164 APLL_RATIO(7) | CORE2_RATIO(7);
165
166 clrsetbits_le32(&clk->div_cpu0, clr, set);
167
168 /* Wait for divider ready status */
169 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
170 continue;
171
172 /*
173 * For MOUThpm = 1000 MHz (MOUTapll)
174 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
175 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
176 * cores_out = armclk / (ratio + 1) = 200 (4)
177 */
178 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
179 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
180
181 clrsetbits_le32(&clk->div_cpu1, clr, set);
182
183 /* Wait for divider ready status */
184 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
185 continue;
186
187 /*
188 * Set CMU_DMC clocks src to APLL
189 * Bit values: 0 ; 1
190 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
191 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
192 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
193 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
194 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
195 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
196 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
197 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
198 */
199 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
200 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
201 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
202 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
203 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
204 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
205 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
206
207 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
208
209 /* Wait for mux change */
210 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
211 continue;
212
213 /* Set MPLL to 800MHz */
214 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
215
216 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
217
218 /* Wait for PLL to be locked */
219 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
220 continue;
221
222 /* Switch back CMU_DMC mux */
223 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
224 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
225 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
226
227 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
228
229 /* Wait for mux change */
230 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
231 continue;
232
233 /* CLK_DIV_DMC0 */
234 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
235 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
236 /*
237 * For:
238 * MOUTdmc = 800 MHz
239 * MOUTdphy = 800 MHz
240 *
241 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
242 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
243 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
244 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
245 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
246 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
247 */
248 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
249 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
250
251 clrsetbits_le32(&clk->div_dmc0, clr, set);
252
253 /* Wait for divider ready status */
254 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
255 continue;
256
257 /* CLK_DIV_DMC1 */
258 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
259 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
260 /*
261 * For:
262 * MOUTg2d = 800 MHz
263 * MOUTc2c = 800 Mhz
264 * MOUTpwi = 108 MHz
265 *
266 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
267 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
268 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
269 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
270 */
271 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
272 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
273
274 clrsetbits_le32(&clk->div_dmc1, clr, set);
275
276 /* Wait for divider ready status */
277 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
278 continue;
279
280 /* CLK_SRC_PERIL0 */
281 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
282 UART3_SEL(15) | UART4_SEL(15);
283 /*
284 * Set CLK_SRC_PERIL0 clocks src to MPLL
285 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
286 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
287 * 8(SCLK_VPLL)
288 *
289 * Set all to SCLK_MPLL_USER_T
290 */
291 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
292 UART4_SEL(6);
293
294 clrsetbits_le32(&clk->src_peril0, clr, set);
295
296 /* CLK_DIV_PERIL0 */
297 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
298 UART3_RATIO(15) | UART4_RATIO(15);
299 /*
300 * For MOUTuart0-4: 800MHz
301 *
302 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
303 */
304 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
305 UART3_RATIO(7) | UART4_RATIO(7);
306
307 clrsetbits_le32(&clk->div_peril0, clr, set);
308
309 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
310 continue;
311
312 /* CLK_DIV_FSYS1 */
313 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
314 MMC1_PRE_RATIO(255);
315 /*
316 * For MOUTmmc0-3 = 800 MHz (MPLL)
317 *
318 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
319 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
320 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
321 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
322 */
323 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
324 MMC1_PRE_RATIO(1);
325
326 clrsetbits_le32(&clk->div_fsys1, clr, set);
327
328 /* Wait for divider ready status */
329 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
330 continue;
331
332 /* CLK_DIV_FSYS2 */
333 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
334 MMC3_PRE_RATIO(255);
335 /*
336 * For MOUTmmc0-3 = 800 MHz (MPLL)
337 *
338 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
339 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
340 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
341 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
342 */
343 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
344 MMC3_PRE_RATIO(1);
345
346 clrsetbits_le32(&clk->div_fsys2, clr, set);
347
348 /* Wait for divider ready status */
349 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
350 continue;
351
352 /* CLK_DIV_FSYS3 */
353 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
354 /*
355 * For MOUTmmc4 = 800 MHz (MPLL)
356 *
357 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
358 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
359 */
360 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
361
362 clrsetbits_le32(&clk->div_fsys3, clr, set);
363
364 /* Wait for divider ready status */
365 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
366 continue;
367
368 return;
369 }
370
board_gpio_init(void)371 static void board_gpio_init(void)
372 {
373 /* eMMC Reset Pin */
374 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
375
376 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
377 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
378 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
379
380 /* Enable FAN (Odroid U3) */
381 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
382
383 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
384 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
385 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
386
387 /* OTG Vbus output (Odroid U3+) */
388 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
389
390 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
391 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
392 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
393
394 /* OTG INT (Odroid U3+) */
395 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
396
397 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
398 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
399 gpio_direction_input(EXYNOS4X12_GPIO_X31);
400
401 /* Blue LED (Odroid X2/U2/U3) */
402 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
403
404 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
405
406 #ifdef CONFIG_CMD_USB
407 /* USB3503A Reference frequency */
408 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
409
410 /* USB3503A Connect */
411 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
412
413 /* USB3503A Reset */
414 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
415 #endif
416 }
417
exynos_early_init_f(void)418 int exynos_early_init_f(void)
419 {
420 board_clock_init();
421
422 return 0;
423 }
424
exynos_init(void)425 int exynos_init(void)
426 {
427 board_gpio_init();
428
429 return 0;
430 }
431
exynos_power_init(void)432 int exynos_power_init(void)
433 {
434 const char *mmc_regulators[] = {
435 "VDDQ_EMMC_1.8V",
436 "VDDQ_EMMC_2.8V",
437 "TFLASH_2.8V",
438 NULL,
439 };
440
441 if (regulator_list_autoset(mmc_regulators, NULL, true))
442 pr_err("Unable to init all mmc regulators\n");
443
444 return 0;
445 }
446
447 #ifdef CONFIG_USB_GADGET
s5pc210_phy_control(int on)448 static int s5pc210_phy_control(int on)
449 {
450 struct udevice *dev;
451 int ret;
452
453 ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
454 if (ret) {
455 pr_err("Regulator get error: %d\n", ret);
456 return ret;
457 }
458
459 if (on)
460 return regulator_set_mode(dev, OPMODE_ON);
461 else
462 return regulator_set_mode(dev, OPMODE_LPM);
463 }
464
465 struct dwc2_plat_otg_data s5pc210_otg_data = {
466 .phy_control = s5pc210_phy_control,
467 .regs_phy = EXYNOS4X12_USBPHY_BASE,
468 .regs_otg = EXYNOS4X12_USBOTG_BASE,
469 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
470 .usb_flags = PHY0_SLEEP,
471 };
472 #endif
473
474 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
475
set_usb3503_ref_clk(void)476 static void set_usb3503_ref_clk(void)
477 {
478 #ifdef CONFIG_BOARD_TYPES
479 /*
480 * gpx3-0 chooses primary (low) or secondary (high) reference clock
481 * frequencies table. The choice of clock is done through hard-wired
482 * REF_SEL pins.
483 * The Odroid Us have reference clock at 24 MHz (00 entry from secondary
484 * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).
485 */
486 if (gd->board_type == ODROID_TYPE_U3)
487 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
488 else
489 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
490 #else
491 /* Choose Odroid Xs frequency without board types */
492 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
493 #endif /* CONFIG_BOARD_TYPES */
494 }
495
board_usb_init(int index,enum usb_init_type init)496 int board_usb_init(int index, enum usb_init_type init)
497 {
498 #ifdef CONFIG_CMD_USB
499 struct udevice *dev;
500 int ret;
501
502 set_usb3503_ref_clk();
503
504 /* Disconnect, Reset, Connect */
505 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
506 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
507 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
508 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
509
510 /* Power off and on BUCK8 for LAN9730 */
511 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
512
513 ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
514 if (ret) {
515 pr_err("Regulator get error: %d\n", ret);
516 return ret;
517 }
518
519 ret = regulator_set_enable(dev, true);
520 if (ret) {
521 pr_err("Regulator %s enable setting error: %d\n", dev->name, ret);
522 return ret;
523 }
524
525 ret = regulator_set_value(dev, 750000);
526 if (ret) {
527 pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
528 return ret;
529 }
530
531 ret = regulator_set_value(dev, 3300000);
532 if (ret) {
533 pr_err("Regulator %s value setting error: %d\n", dev->name, ret);
534 return ret;
535 }
536 #endif
537 debug("USB_udc_probe\n");
538 return dwc2_udc_probe(&s5pc210_otg_data);
539 }
540 #endif
541