1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <init.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx53.h>
16 #include <asm/global_data.h>
17 #include <asm/mach-imx/mx5_video.h>
18 #include <ACEX1K.h>
19 #include <asm/gpio.h>
20 #include <linux/delay.h>
21
22 enum LED_GPIOS {
23 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
24 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
25 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
26 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
27 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
28 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
29 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
30 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
31 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
32 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
33 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
34 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
35 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
36 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
37 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
38 };
39
40 #define CCAT_BASE_ADDR ((void *)0xf0000000)
41 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
42 #define CCAT_SIZE 1191788
43 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
44 static const char CCAT_SIGNATURE[] = "CCAT";
45
46 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
47 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
48
49 DECLARE_GLOBAL_DATA_PTR;
50
get_board_rev(void)51 u32 get_board_rev(void)
52 {
53 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
54 struct fuse_bank *bank = &iim->bank[0];
55 struct fuse_bank0_regs *fuse =
56 (struct fuse_bank0_regs *)bank->fuse_regs;
57
58 int rev = readl(&fuse->gp[6]);
59
60 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
61 }
62
63 /*
64 * Set CCAT mode
65 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
66 */
weim_cs0_settings(u32 mode)67 void weim_cs0_settings(u32 mode)
68 {
69 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
70
71 writel(0x0, &weim_regs->cs0gcr1);
72 writel(mode, &weim_regs->cs0gcr1);
73 writel(0x00001002, &weim_regs->cs0gcr2);
74
75 writel(0x04000000, &weim_regs->cs0rcr1);
76 writel(0x00000000, &weim_regs->cs0rcr2);
77
78 writel(0x04000000, &weim_regs->cs0wcr1);
79 writel(0x00000000, &weim_regs->cs0wcr2);
80 }
81
setup_gpio_eim(void)82 static void setup_gpio_eim(void)
83 {
84 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
85 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
86 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
87 gpio_direction_input(GPIO_C3_STATUS);
88 gpio_direction_input(GPIO_C3_DONE);
89 gpio_direction_output(GPIO_C3_CONFIG, 1);
90
91 weim_cs0_settings(CCAT_MODE_RUN);
92 }
93
setup_gpio_sups(void)94 static void setup_gpio_sups(void)
95 {
96 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
97 gpio_direction_input(GPIO_SUPS_INT);
98
99 static const int BLINK_INTERVALL = 50000;
100 int status = 1;
101 while (gpio_get_value(GPIO_SUPS_INT)) {
102 /* signal "CX SUPS power fail" */
103 gpio_set_value(GPIO_LED_PWR_R,
104 (++status / BLINK_INTERVALL) % 2);
105 }
106
107 /* signal "CX power up" */
108 gpio_set_value(GPIO_LED_PWR_R, 1);
109 }
110
setup_gpio_leds(void)111 static void setup_gpio_leds(void)
112 {
113 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
114 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
115 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
116 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
117 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
118 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
119 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
120 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
121 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
122
123 gpio_direction_output(GPIO_LED_SD2_R, 0);
124 gpio_direction_output(GPIO_LED_SD2_B, 0);
125 gpio_direction_output(GPIO_LED_SD2_G, 0);
126 gpio_direction_output(GPIO_LED_SD1_R, 0);
127 gpio_direction_output(GPIO_LED_SD1_B, 0);
128 gpio_direction_output(GPIO_LED_SD1_G, 0);
129 gpio_direction_output(GPIO_LED_PWR_R, 0);
130 gpio_direction_output(GPIO_LED_PWR_B, 0);
131 gpio_direction_output(GPIO_LED_PWR_G, 0);
132 }
133
power_init(void)134 static int power_init(void)
135 {
136 /* nothing to do on CX9020 */
137 return 0;
138 }
139
clock_1GHz(void)140 static void clock_1GHz(void)
141 {
142 int ret;
143 u32 ref_clk = MXC_HCLK;
144 /*
145 * After increasing voltage to 1.25V, we can switch
146 * CPU clock to 1GHz and DDR to 400MHz safely
147 */
148 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
149 if (ret)
150 printf("CPU: Switch CPU clock to 1GHZ failed\n");
151
152 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
153 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
154 if (ret)
155 printf("CPU: Switch DDR clock to 400MHz failed\n");
156 }
157
board_early_init_f(void)158 int board_early_init_f(void)
159 {
160
161 return 0;
162 }
163
board_init(void)164 int board_init(void)
165 {
166 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
167
168 mxc_set_sata_internal_clock();
169
170 setup_gpio_leds();
171 setup_gpio_sups();
172 setup_gpio_eim();
173 setup_iomux_lcd();
174
175 return 0;
176 }
177
checkboard(void)178 int checkboard(void)
179 {
180 puts("Board: Beckhoff CX9020\n");
181
182 return 0;
183 }
184
ccat_config_fn(int assert_config,int flush,int cookie)185 static int ccat_config_fn(int assert_config, int flush, int cookie)
186 {
187 /* prepare FPGA for programming */
188 weim_cs0_settings(CCAT_MODE_CONFIG);
189 gpio_set_value(GPIO_C3_CONFIG, 0);
190 udelay(1);
191 gpio_set_value(GPIO_C3_CONFIG, 1);
192 udelay(230);
193
194 return FPGA_SUCCESS;
195 }
196
ccat_status_fn(int cookie)197 static int ccat_status_fn(int cookie)
198 {
199 return FPGA_FAIL;
200 }
201
ccat_write_fn(const void * buf,size_t buf_len,int flush,int cookie)202 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
203 {
204 const uint8_t *const buffer = buf;
205
206 /* program CCAT */
207 int i;
208 for (i = 0; i < buf_len; ++i)
209 writeb(buffer[i], CCAT_BASE_ADDR);
210
211 writeb(0xff, CCAT_BASE_ADDR);
212 writeb(0xff, CCAT_BASE_ADDR);
213
214 return FPGA_SUCCESS;
215 }
216
ccat_done_fn(int cookie)217 static int ccat_done_fn(int cookie)
218 {
219 /* programming complete? */
220 return gpio_get_value(GPIO_C3_DONE);
221 }
222
ccat_post_fn(int cookie)223 static int ccat_post_fn(int cookie)
224 {
225 /* switch to FPGA run mode */
226 weim_cs0_settings(CCAT_MODE_RUN);
227 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
228
229 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
230 printf("Verifing CCAT firmware failed, signature not found\n");
231 return FPGA_FAIL;
232 }
233
234 /* signal "CX booting OS" */
235 gpio_set_value(GPIO_LED_PWR_R, 1);
236 gpio_set_value(GPIO_LED_PWR_G, 1);
237 gpio_set_value(GPIO_LED_PWR_B, 0);
238 return FPGA_SUCCESS;
239 }
240
241 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
242 .config = ccat_config_fn,
243 .status = ccat_status_fn,
244 .done = ccat_done_fn,
245 .write = ccat_write_fn,
246 .abort = ccat_post_fn,
247 .post = ccat_post_fn,
248 };
249
250 static Altera_desc ccat_fpga = {
251 .family = Altera_CYC2,
252 .iface = passive_serial,
253 .size = CCAT_SIZE,
254 .iface_fns = &ccat_fns,
255 .base = CCAT_BASE_ADDR,
256 };
257
board_late_init(void)258 int board_late_init(void)
259 {
260 if (!power_init())
261 clock_1GHz();
262
263 fpga_init();
264 fpga_add(fpga_altera, &ccat_fpga);
265
266 return 0;
267 }
268