1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sunxi_emac.c -- Allwinner A10 ethernet driver
4 *
5 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <dm/device_compat.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <malloc.h>
16 #include <miiphy.h>
17 #include <net.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21
22 /* EMAC register */
23 struct emac_regs {
24 u32 ctl; /* 0x00 */
25 u32 tx_mode; /* 0x04 */
26 u32 tx_flow; /* 0x08 */
27 u32 tx_ctl0; /* 0x0c */
28 u32 tx_ctl1; /* 0x10 */
29 u32 tx_ins; /* 0x14 */
30 u32 tx_pl0; /* 0x18 */
31 u32 tx_pl1; /* 0x1c */
32 u32 tx_sta; /* 0x20 */
33 u32 tx_io_data; /* 0x24 */
34 u32 tx_io_data1;/* 0x28 */
35 u32 tx_tsvl0; /* 0x2c */
36 u32 tx_tsvh0; /* 0x30 */
37 u32 tx_tsvl1; /* 0x34 */
38 u32 tx_tsvh1; /* 0x38 */
39 u32 rx_ctl; /* 0x3c */
40 u32 rx_hash0; /* 0x40 */
41 u32 rx_hash1; /* 0x44 */
42 u32 rx_sta; /* 0x48 */
43 u32 rx_io_data; /* 0x4c */
44 u32 rx_fbc; /* 0x50 */
45 u32 int_ctl; /* 0x54 */
46 u32 int_sta; /* 0x58 */
47 u32 mac_ctl0; /* 0x5c */
48 u32 mac_ctl1; /* 0x60 */
49 u32 mac_ipgt; /* 0x64 */
50 u32 mac_ipgr; /* 0x68 */
51 u32 mac_clrt; /* 0x6c */
52 u32 mac_maxf; /* 0x70 */
53 u32 mac_supp; /* 0x74 */
54 u32 mac_test; /* 0x78 */
55 u32 mac_mcfg; /* 0x7c */
56 u32 mac_mcmd; /* 0x80 */
57 u32 mac_madr; /* 0x84 */
58 u32 mac_mwtd; /* 0x88 */
59 u32 mac_mrdd; /* 0x8c */
60 u32 mac_mind; /* 0x90 */
61 u32 mac_ssrr; /* 0x94 */
62 u32 mac_a0; /* 0x98 */
63 u32 mac_a1; /* 0x9c */
64 };
65
66 /* SRAMC register */
67 struct sunxi_sramc_regs {
68 u32 ctrl0;
69 u32 ctrl1;
70 };
71
72 /* 0: Disable 1: Aborted frame enable(default) */
73 #define EMAC_TX_AB_M (0x1 << 0)
74 /* 0: CPU 1: DMA(default) */
75 #define EMAC_TX_TM (0x1 << 1)
76
77 #define EMAC_TX_SETUP (0)
78
79 /* 0: DRQ asserted 1: DRQ automatically(default) */
80 #define EMAC_RX_DRQ_MODE (0x1 << 1)
81 /* 0: CPU 1: DMA(default) */
82 #define EMAC_RX_TM (0x1 << 2)
83 /* 0: Normal(default) 1: Pass all Frames */
84 #define EMAC_RX_PA (0x1 << 4)
85 /* 0: Normal(default) 1: Pass Control Frames */
86 #define EMAC_RX_PCF (0x1 << 5)
87 /* 0: Normal(default) 1: Pass Frames with CRC Error */
88 #define EMAC_RX_PCRCE (0x1 << 6)
89 /* 0: Normal(default) 1: Pass Frames with Length Error */
90 #define EMAC_RX_PLE (0x1 << 7)
91 /* 0: Normal 1: Pass Frames length out of range(default) */
92 #define EMAC_RX_POR (0x1 << 8)
93 /* 0: Not accept 1: Accept unicast Packets(default) */
94 #define EMAC_RX_UCAD (0x1 << 16)
95 /* 0: Normal(default) 1: DA Filtering */
96 #define EMAC_RX_DAF (0x1 << 17)
97 /* 0: Not accept 1: Accept multicast Packets(default) */
98 #define EMAC_RX_MCO (0x1 << 20)
99 /* 0: Disable(default) 1: Enable Hash filter */
100 #define EMAC_RX_MHF (0x1 << 21)
101 /* 0: Not accept 1: Accept Broadcast Packets(default) */
102 #define EMAC_RX_BCO (0x1 << 22)
103 /* 0: Disable(default) 1: Enable SA Filtering */
104 #define EMAC_RX_SAF (0x1 << 24)
105 /* 0: Normal(default) 1: Inverse Filtering */
106 #define EMAC_RX_SAIF (0x1 << 25)
107
108 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
109 EMAC_RX_MCO | EMAC_RX_BCO)
110
111 /* 0: Disable 1: Enable Receive Flow Control(default) */
112 #define EMAC_MAC_CTL0_RFC (0x1 << 2)
113 /* 0: Disable 1: Enable Transmit Flow Control(default) */
114 #define EMAC_MAC_CTL0_TFC (0x1 << 3)
115
116 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
117
118 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
119 #define EMAC_MAC_CTL1_FLC (0x1 << 1)
120 /* 0: Disable(default) 1: Enable Huge Frame */
121 #define EMAC_MAC_CTL1_HF (0x1 << 2)
122 /* 0: Disable(default) 1: Enable MAC Delayed CRC */
123 #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
124 /* 0: Disable 1: Enable MAC CRC(default) */
125 #define EMAC_MAC_CTL1_CRC (0x1 << 4)
126 /* 0: Disable 1: Enable MAC PAD Short frames(default) */
127 #define EMAC_MAC_CTL1_PC (0x1 << 5)
128 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
129 #define EMAC_MAC_CTL1_VC (0x1 << 6)
130 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
131 #define EMAC_MAC_CTL1_ADP (0x1 << 7)
132 /* 0: Disable(default) 1: Enable */
133 #define EMAC_MAC_CTL1_PRE (0x1 << 8)
134 /* 0: Disable(default) 1: Enable */
135 #define EMAC_MAC_CTL1_LPE (0x1 << 9)
136 /* 0: Disable(default) 1: Enable no back off */
137 #define EMAC_MAC_CTL1_NB (0x1 << 12)
138 /* 0: Disable(default) 1: Enable */
139 #define EMAC_MAC_CTL1_BNB (0x1 << 13)
140 /* 0: Disable(default) 1: Enable */
141 #define EMAC_MAC_CTL1_ED (0x1 << 14)
142
143 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
144 EMAC_MAC_CTL1_PC)
145
146 #define EMAC_MAC_IPGT 0x15
147
148 #define EMAC_MAC_NBTB_IPG1 0xc
149 #define EMAC_MAC_NBTB_IPG2 0x12
150
151 #define EMAC_MAC_CW 0x37
152 #define EMAC_MAC_RM 0xf
153
154 #define EMAC_MAC_MFL 0x0600
155
156 /* Receive status */
157 #define EMAC_CRCERR (0x1 << 4)
158 #define EMAC_LENERR (0x3 << 5)
159
160 #define EMAC_RX_BUFSIZE 2000
161
162 struct emac_eth_dev {
163 struct emac_regs *regs;
164 struct clk clk;
165 struct mii_dev *bus;
166 struct phy_device *phydev;
167 int link_printed;
168 #ifdef CONFIG_DM_ETH
169 uchar rx_buf[EMAC_RX_BUFSIZE];
170 #endif
171 };
172
173 struct emac_rxhdr {
174 s16 rx_len;
175 u16 rx_status;
176 };
177
emac_inblk_32bit(void * reg,void * data,int count)178 static void emac_inblk_32bit(void *reg, void *data, int count)
179 {
180 int cnt = (count + 3) >> 2;
181
182 if (cnt) {
183 u32 *buf = data;
184
185 do {
186 u32 x = readl(reg);
187 *buf++ = x;
188 } while (--cnt);
189 }
190 }
191
emac_outblk_32bit(void * reg,void * data,int count)192 static void emac_outblk_32bit(void *reg, void *data, int count)
193 {
194 int cnt = (count + 3) >> 2;
195
196 if (cnt) {
197 const u32 *buf = data;
198
199 do {
200 writel(*buf++, reg);
201 } while (--cnt);
202 }
203 }
204
205 /* Read a word from phyxcer */
emac_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)206 static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
207 {
208 struct emac_eth_dev *priv = bus->priv;
209 struct emac_regs *regs = priv->regs;
210
211 /* issue the phy address and reg */
212 writel(addr << 8 | reg, ®s->mac_madr);
213
214 /* pull up the phy io line */
215 writel(0x1, ®s->mac_mcmd);
216
217 /* Wait read complete */
218 mdelay(1);
219
220 /* push down the phy io line */
221 writel(0x0, ®s->mac_mcmd);
222
223 /* And read data */
224 return readl(®s->mac_mrdd);
225 }
226
227 /* Write a word to phyxcer */
emac_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)228 static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
229 u16 value)
230 {
231 struct emac_eth_dev *priv = bus->priv;
232 struct emac_regs *regs = priv->regs;
233
234 /* issue the phy address and reg */
235 writel(addr << 8 | reg, ®s->mac_madr);
236
237 /* pull up the phy io line */
238 writel(0x1, ®s->mac_mcmd);
239
240 /* Wait write complete */
241 mdelay(1);
242
243 /* push down the phy io line */
244 writel(0x0, ®s->mac_mcmd);
245
246 /* and write data */
247 writel(value, ®s->mac_mwtd);
248
249 return 0;
250 }
251
sunxi_emac_init_phy(struct emac_eth_dev * priv,void * dev)252 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
253 {
254 int ret, mask = 0xffffffff;
255
256 #ifdef CONFIG_PHY_ADDR
257 mask = 1 << CONFIG_PHY_ADDR;
258 #endif
259
260 priv->bus = mdio_alloc();
261 if (!priv->bus) {
262 printf("Failed to allocate MDIO bus\n");
263 return -ENOMEM;
264 }
265
266 priv->bus->read = emac_mdio_read;
267 priv->bus->write = emac_mdio_write;
268 priv->bus->priv = priv;
269 strcpy(priv->bus->name, "emac");
270
271 ret = mdio_register(priv->bus);
272 if (ret)
273 return ret;
274
275 priv->phydev = phy_find_by_mask(priv->bus, mask,
276 PHY_INTERFACE_MODE_MII);
277 if (!priv->phydev)
278 return -ENODEV;
279
280 phy_connect_dev(priv->phydev, dev);
281 phy_config(priv->phydev);
282
283 return 0;
284 }
285
emac_setup(struct emac_eth_dev * priv)286 static void emac_setup(struct emac_eth_dev *priv)
287 {
288 struct emac_regs *regs = priv->regs;
289 u32 reg_val;
290
291 /* Set up TX */
292 writel(EMAC_TX_SETUP, ®s->tx_mode);
293
294 /* Set up RX */
295 writel(EMAC_RX_SETUP, ®s->rx_ctl);
296
297 /* Set MAC */
298 /* Set MAC CTL0 */
299 writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
300
301 /* Set MAC CTL1 */
302 reg_val = 0;
303 if (priv->phydev->duplex == DUPLEX_FULL)
304 reg_val = (0x1 << 0);
305 writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
306
307 /* Set up IPGT */
308 writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
309
310 /* Set up IPGR */
311 writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
312
313 /* Set up Collison window */
314 writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
315
316 /* Set up Max Frame Length */
317 writel(EMAC_MAC_MFL, ®s->mac_maxf);
318 }
319
emac_reset(struct emac_eth_dev * priv)320 static void emac_reset(struct emac_eth_dev *priv)
321 {
322 struct emac_regs *regs = priv->regs;
323
324 debug("resetting device\n");
325
326 /* RESET device */
327 writel(0, ®s->ctl);
328 udelay(200);
329
330 writel(1, ®s->ctl);
331 udelay(200);
332 }
333
_sunxi_write_hwaddr(struct emac_eth_dev * priv,u8 * enetaddr)334 static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
335 {
336 struct emac_regs *regs = priv->regs;
337 u32 enetaddr_lo, enetaddr_hi;
338
339 enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
340 enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
341
342 writel(enetaddr_hi, ®s->mac_a0);
343 writel(enetaddr_lo, ®s->mac_a1);
344
345 return 0;
346 }
347
_sunxi_emac_eth_init(struct emac_eth_dev * priv,u8 * enetaddr)348 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
349 {
350 struct emac_regs *regs = priv->regs;
351 int ret;
352
353 /* Init EMAC */
354
355 /* Flush RX FIFO */
356 setbits_le32(®s->rx_ctl, 0x8);
357 udelay(1);
358
359 /* Init MAC */
360
361 /* Soft reset MAC */
362 clrbits_le32(®s->mac_ctl0, 0x1 << 15);
363
364 /* Clear RX counter */
365 writel(0x0, ®s->rx_fbc);
366 udelay(1);
367
368 /* Set up EMAC */
369 emac_setup(priv);
370
371 _sunxi_write_hwaddr(priv, enetaddr);
372
373 mdelay(1);
374
375 emac_reset(priv);
376
377 /* PHY POWER UP */
378 ret = phy_startup(priv->phydev);
379 if (ret) {
380 printf("Could not initialize PHY %s\n",
381 priv->phydev->dev->name);
382 return ret;
383 }
384
385 /* Print link status only once */
386 if (!priv->link_printed) {
387 printf("ENET Speed is %d Mbps - %s duplex connection\n",
388 priv->phydev->speed,
389 priv->phydev->duplex ? "FULL" : "HALF");
390 priv->link_printed = 1;
391 }
392
393 /* Set EMAC SPEED depend on PHY */
394 if (priv->phydev->speed == SPEED_100)
395 setbits_le32(®s->mac_supp, 1 << 8);
396 else
397 clrbits_le32(®s->mac_supp, 1 << 8);
398
399 /* Set duplex depend on phy */
400 if (priv->phydev->duplex == DUPLEX_FULL)
401 setbits_le32(®s->mac_ctl1, 1 << 0);
402 else
403 clrbits_le32(®s->mac_ctl1, 1 << 0);
404
405 /* Enable RX/TX */
406 setbits_le32(®s->ctl, 0x7);
407
408 return 0;
409 }
410
_sunxi_emac_eth_recv(struct emac_eth_dev * priv,void * packet)411 static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
412 {
413 struct emac_regs *regs = priv->regs;
414 struct emac_rxhdr rxhdr;
415 u32 rxcount;
416 u32 reg_val;
417 int rx_len;
418 int rx_status;
419 int good_packet;
420
421 /* Check packet ready or not */
422
423 /* Race warning: The first packet might arrive with
424 * the interrupts disabled, but the second will fix
425 */
426 rxcount = readl(®s->rx_fbc);
427 if (!rxcount) {
428 /* Had one stuck? */
429 rxcount = readl(®s->rx_fbc);
430 if (!rxcount)
431 return -EAGAIN;
432 }
433
434 reg_val = readl(®s->rx_io_data);
435 if (reg_val != 0x0143414d) {
436 /* Disable RX */
437 clrbits_le32(®s->ctl, 0x1 << 2);
438
439 /* Flush RX FIFO */
440 setbits_le32(®s->rx_ctl, 0x1 << 3);
441 while (readl(®s->rx_ctl) & (0x1 << 3))
442 ;
443
444 /* Enable RX */
445 setbits_le32(®s->ctl, 0x1 << 2);
446
447 return -EAGAIN;
448 }
449
450 /* A packet ready now
451 * Get status/length
452 */
453 good_packet = 1;
454
455 emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
456
457 rx_len = rxhdr.rx_len;
458 rx_status = rxhdr.rx_status;
459
460 /* Packet Status check */
461 if (rx_len < 0x40) {
462 good_packet = 0;
463 debug("RX: Bad Packet (runt)\n");
464 }
465
466 /* rx_status is identical to RSR register. */
467 if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
468 good_packet = 0;
469 if (rx_status & EMAC_CRCERR)
470 printf("crc error\n");
471 if (rx_status & EMAC_LENERR)
472 printf("length error\n");
473 }
474
475 /* Move data from EMAC */
476 if (good_packet) {
477 if (rx_len > EMAC_RX_BUFSIZE) {
478 printf("Received packet is too big (len=%d)\n", rx_len);
479 return -EMSGSIZE;
480 }
481 emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len);
482 return rx_len;
483 }
484
485 return -EIO; /* Bad packet */
486 }
487
_sunxi_emac_eth_send(struct emac_eth_dev * priv,void * packet,int len)488 static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
489 int len)
490 {
491 struct emac_regs *regs = priv->regs;
492
493 /* Select channel 0 */
494 writel(0, ®s->tx_ins);
495
496 /* Write packet */
497 emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
498
499 /* Set TX len */
500 writel(len, ®s->tx_pl0);
501
502 /* Start translate from fifo to phy */
503 setbits_le32(®s->tx_ctl0, 1);
504
505 return 0;
506 }
507
sunxi_emac_board_setup(struct udevice * dev,struct emac_eth_dev * priv)508 static int sunxi_emac_board_setup(struct udevice *dev,
509 struct emac_eth_dev *priv)
510 {
511 struct sunxi_sramc_regs *sram =
512 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
513 struct emac_regs *regs = priv->regs;
514 int pin, ret;
515
516 /* Map SRAM to EMAC */
517 setbits_le32(&sram->ctrl1, 0x5 << 2);
518
519 /* Configure pin mux settings for MII Ethernet */
520 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
521 sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
522
523 /* Set up clock gating */
524 ret = clk_enable(&priv->clk);
525 if (ret) {
526 dev_err(dev, "failed to enable emac clock\n");
527 return ret;
528 }
529
530 /* Set MII clock */
531 clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
532
533 return 0;
534 }
535
sunxi_emac_eth_start(struct udevice * dev)536 static int sunxi_emac_eth_start(struct udevice *dev)
537 {
538 struct eth_pdata *pdata = dev_get_plat(dev);
539
540 return _sunxi_emac_eth_init(dev_get_priv(dev), pdata->enetaddr);
541 }
542
sunxi_emac_eth_send(struct udevice * dev,void * packet,int length)543 static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
544 {
545 struct emac_eth_dev *priv = dev_get_priv(dev);
546
547 return _sunxi_emac_eth_send(priv, packet, length);
548 }
549
sunxi_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)550 static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
551 {
552 struct emac_eth_dev *priv = dev_get_priv(dev);
553 int rx_len;
554
555 rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
556 *packetp = priv->rx_buf;
557
558 return rx_len;
559 }
560
sunxi_emac_eth_stop(struct udevice * dev)561 static void sunxi_emac_eth_stop(struct udevice *dev)
562 {
563 /* Nothing to do here */
564 }
565
sunxi_emac_eth_probe(struct udevice * dev)566 static int sunxi_emac_eth_probe(struct udevice *dev)
567 {
568 struct eth_pdata *pdata = dev_get_plat(dev);
569 struct emac_eth_dev *priv = dev_get_priv(dev);
570 int ret;
571
572 priv->regs = (struct emac_regs *)pdata->iobase;
573
574 ret = clk_get_by_index(dev, 0, &priv->clk);
575 if (ret) {
576 dev_err(dev, "failed to get emac clock\n");
577 return ret;
578 }
579
580 ret = sunxi_emac_board_setup(dev, priv);
581 if (ret)
582 return ret;
583
584 return sunxi_emac_init_phy(priv, dev);
585 }
586
587 static const struct eth_ops sunxi_emac_eth_ops = {
588 .start = sunxi_emac_eth_start,
589 .send = sunxi_emac_eth_send,
590 .recv = sunxi_emac_eth_recv,
591 .stop = sunxi_emac_eth_stop,
592 };
593
sunxi_emac_eth_of_to_plat(struct udevice * dev)594 static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
595 {
596 struct eth_pdata *pdata = dev_get_plat(dev);
597
598 pdata->iobase = dev_read_addr(dev);
599
600 return 0;
601 }
602
603 static const struct udevice_id sunxi_emac_eth_ids[] = {
604 { .compatible = "allwinner,sun4i-a10-emac" },
605 { }
606 };
607
608 U_BOOT_DRIVER(eth_sunxi_emac) = {
609 .name = "eth_sunxi_emac",
610 .id = UCLASS_ETH,
611 .of_match = sunxi_emac_eth_ids,
612 .of_to_plat = sunxi_emac_eth_of_to_plat,
613 .probe = sunxi_emac_eth_probe,
614 .ops = &sunxi_emac_eth_ops,
615 .priv_auto = sizeof(struct emac_eth_dev),
616 .plat_auto = sizeof(struct eth_pdata),
617 };
618