1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 Einfochips
4 * Copyright 2019 Linaro Ltd.
5 */
6
7/dts-v1/;
8
9#include "fsl-imx8qxp.dtsi"
10#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"
11
12/ {
13	model = "Einfochips i.MX8QXP AI_ML";
14	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
15
16	chosen {
17		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
18		stdout-path = &lpuart2;
19	};
20
21	memory@80000000 {
22		device_type = "memory";
23		reg = <0x00000000 0x80000000 0 0x80000000>;
24	};
25};
26
27&lpuart0 {
28	pinctrl-names = "default";
29	pinctrl-0 = <&pinctrl_lpuart0>;
30	status = "okay";
31};
32
33&lpuart1 {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_lpuart1>;
36	status = "okay";
37};
38
39&lpuart2 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_lpuart2>;
42	status = "okay";
43};
44
45&lpuart3 {
46	pinctrl-names = "default";
47	pinctrl-0 = <&pinctrl_lpuart3>;
48	status = "okay";
49};
50
51&fec1 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_fec1>;
54	phy-mode = "rgmii";
55	phy-handle = <&ethphy0>;
56	fsl,ar8031-phy-fixup;
57	fsl,magic-packet;
58	phy-reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
59	phy-reset-duration = <10>;
60	phy-reset-post-delay = <150>;
61	status = "okay";
62
63	mdio {
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		ethphy0: ethernet-phy@0 {
68			compatible = "ethernet-phy-ieee802.3-c22";
69			reg = <0>;
70		};
71	};
72};
73
74/* LS-I2C1 */
75&i2c1 {
76	#address-cells = <1>;
77	#size-cells = <0>;
78	clock-frequency = <100000>;
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_lpi2c1>;
81	status = "okay";
82};
83
84&usdhc1 {
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_usdhc1>;
87	bus-width = <4>;
88	no-sd;
89	#address-cells = <1>;
90	#size-cells = <0>;
91	status = "okay";
92};
93
94&usdhc2 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_usdhc2>;
97	bus-width = <4>;
98	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
99	status = "okay";
100};
101
102&iomuxc {
103	pinctrl_fec1: fec1grp {
104		fsl,pins = <
105			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
106			SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
107			SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
108			SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
109			SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
110			SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
111			SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
112			SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
113			SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
114			SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
115			SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
116			SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
117			SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
118			SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
119			SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
120			SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
121		>;
122	};
123
124	pinctrl_lpi2c1: lpi2c1grp {
125		fsl,pins = <
126			SC_P_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
127			SC_P_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
128		>;
129	};
130
131	pinctrl_lpuart0: lpuart0grp {
132		fsl,pins = <
133			SC_P_UART0_RX_ADMA_UART0_RX			0X06000020
134			SC_P_UART0_TX_ADMA_UART0_TX			0X06000020
135		>;
136	};
137
138	pinctrl_lpuart1: lpuart1grp {
139		fsl,pins = <
140			SC_P_UART1_RX_ADMA_UART1_RX			0X06000020
141			SC_P_UART1_TX_ADMA_UART1_TX			0X06000020
142		>;
143	};
144
145	pinctrl_lpuart2: lpuart2grp {
146		fsl,pins = <
147			SC_P_UART2_RX_ADMA_UART2_RX			0X06000020
148			SC_P_UART2_TX_ADMA_UART2_TX			0X06000020
149		>;
150	};
151
152	pinctrl_lpuart3: lpuart3grp {
153		fsl,pins = <
154			SC_P_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020
155			SC_P_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020
156		>;
157	};
158
159	pinctrl_usdhc1: usdhc1grp {
160		fsl,pins = <
161			SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
162			SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
163			SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021
164			SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021
165			SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021
166			SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021
167		>;
168	};
169
170	pinctrl_usdhc2: usdhc2grp {
171		fsl,pins = <
172			SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
173			SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
174			SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021
175			SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021
176			SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021
177			SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021
178			SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
179		>;
180	};
181};
182