1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; 66 clocks = <&clk IMX8MN_CLK_ARM>; 67 enable-method = "psci"; 68 next-level-cache = <&A53_L2>; 69 operating-points-v2 = <&a53_opp_table>; 70 nvmem-cells = <&cpu_speed_grade>; 71 nvmem-cell-names = "speed_grade"; 72 cpu-idle-states = <&cpu_pd_wait>; 73 #cooling-cells = <2>; 74 }; 75 76 A53_1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x1>; 80 clock-latency = <61036>; 81 clocks = <&clk IMX8MN_CLK_ARM>; 82 enable-method = "psci"; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 cpu-idle-states = <&cpu_pd_wait>; 86 #cooling-cells = <2>; 87 }; 88 89 A53_2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x2>; 93 clock-latency = <61036>; 94 clocks = <&clk IMX8MN_CLK_ARM>; 95 enable-method = "psci"; 96 next-level-cache = <&A53_L2>; 97 operating-points-v2 = <&a53_opp_table>; 98 cpu-idle-states = <&cpu_pd_wait>; 99 #cooling-cells = <2>; 100 }; 101 102 A53_3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x3>; 106 clock-latency = <61036>; 107 clocks = <&clk IMX8MN_CLK_ARM>; 108 enable-method = "psci"; 109 next-level-cache = <&A53_L2>; 110 operating-points-v2 = <&a53_opp_table>; 111 cpu-idle-states = <&cpu_pd_wait>; 112 #cooling-cells = <2>; 113 }; 114 115 A53_L2: l2-cache0 { 116 compatible = "cache"; 117 }; 118 }; 119 120 a53_opp_table: opp-table { 121 compatible = "operating-points-v2"; 122 opp-shared; 123 124 opp-1200000000 { 125 opp-hz = /bits/ 64 <1200000000>; 126 opp-microvolt = <850000>; 127 opp-supported-hw = <0xb00>, <0x7>; 128 clock-latency-ns = <150000>; 129 opp-suspend; 130 }; 131 132 opp-1400000000 { 133 opp-hz = /bits/ 64 <1400000000>; 134 opp-microvolt = <950000>; 135 opp-supported-hw = <0x300>, <0x7>; 136 clock-latency-ns = <150000>; 137 opp-suspend; 138 }; 139 140 opp-1500000000 { 141 opp-hz = /bits/ 64 <1500000000>; 142 opp-microvolt = <1000000>; 143 opp-supported-hw = <0x100>, <0x3>; 144 clock-latency-ns = <150000>; 145 opp-suspend; 146 }; 147 }; 148 149 osc_32k: clock-osc-32k { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <32768>; 153 clock-output-names = "osc_32k"; 154 }; 155 156 osc_24m: clock-osc-24m { 157 compatible = "fixed-clock"; 158 #clock-cells = <0>; 159 clock-frequency = <24000000>; 160 clock-output-names = "osc_24m"; 161 }; 162 163 clk_ext1: clock-ext1 { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <133000000>; 167 clock-output-names = "clk_ext1"; 168 }; 169 170 clk_ext2: clock-ext2 { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <133000000>; 174 clock-output-names = "clk_ext2"; 175 }; 176 177 clk_ext3: clock-ext3 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext3"; 182 }; 183 184 clk_ext4: clock-ext4 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency= <133000000>; 188 clock-output-names = "clk_ext4"; 189 }; 190 191 pmu { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupts = <GIC_PPI 7 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 195 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 196 }; 197 198 psci { 199 compatible = "arm,psci-1.0"; 200 method = "smc"; 201 }; 202 203 thermal-zones { 204 cpu-thermal { 205 polling-delay-passive = <250>; 206 polling-delay = <2000>; 207 thermal-sensors = <&tmu>; 208 trips { 209 cpu_alert0: trip0 { 210 temperature = <85000>; 211 hysteresis = <2000>; 212 type = "passive"; 213 }; 214 215 cpu_crit0: trip1 { 216 temperature = <95000>; 217 hysteresis = <2000>; 218 type = "critical"; 219 }; 220 }; 221 222 cooling-maps { 223 map0 { 224 trip = <&cpu_alert0>; 225 cooling-device = 226 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 227 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 228 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 229 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 230 }; 231 }; 232 }; 233 }; 234 235 timer { 236 compatible = "arm,armv8-timer"; 237 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 241 clock-frequency = <8000000>; 242 arm,no-tick-in-suspend; 243 }; 244 245 soc@0 { 246 compatible = "fsl,imx8mn-soc", "simple-bus"; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 ranges = <0x0 0x0 0x0 0x3e000000>; 250 nvmem-cells = <&imx8mn_uid>; 251 nvmem-cell-names = "soc_unique_id"; 252 253 aips1: bus@30000000 { 254 compatible = "fsl,aips-bus", "simple-bus"; 255 reg = <0x30000000 0x400000>; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 ranges; 259 260 spba: spba-bus@30000000 { 261 compatible = "fsl,spba-bus", "simple-bus"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 reg = <0x30000000 0x100000>; 265 ranges; 266 267 sai2: sai@30020000 { 268 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 269 reg = <0x30020000 0x10000>; 270 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 272 <&clk IMX8MN_CLK_DUMMY>, 273 <&clk IMX8MN_CLK_SAI2_ROOT>, 274 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 275 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 276 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 277 dma-names = "rx", "tx"; 278 status = "disabled"; 279 }; 280 281 sai3: sai@30030000 { 282 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 283 reg = <0x30030000 0x10000>; 284 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 286 <&clk IMX8MN_CLK_DUMMY>, 287 <&clk IMX8MN_CLK_SAI3_ROOT>, 288 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 289 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 290 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 291 dma-names = "rx", "tx"; 292 status = "disabled"; 293 }; 294 295 sai5: sai@30050000 { 296 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 297 reg = <0x30050000 0x10000>; 298 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 300 <&clk IMX8MN_CLK_DUMMY>, 301 <&clk IMX8MN_CLK_SAI5_ROOT>, 302 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 303 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 304 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 305 dma-names = "rx", "tx"; 306 fsl,shared-interrupt; 307 fsl,dataline = <0 0xf 0xf>; 308 status = "disabled"; 309 }; 310 311 sai6: sai@30060000 { 312 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 313 reg = <0x30060000 0x10000>; 314 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 316 <&clk IMX8MN_CLK_DUMMY>, 317 <&clk IMX8MN_CLK_SAI6_ROOT>, 318 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 319 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 320 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 micfil: audio-controller@30080000 { 326 compatible = "fsl,imx8mm-micfil"; 327 reg = <0x30080000 0x10000>; 328 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 333 <&clk IMX8MN_CLK_PDM_ROOT>, 334 <&clk IMX8MN_AUDIO_PLL1_OUT>, 335 <&clk IMX8MN_AUDIO_PLL2_OUT>, 336 <&clk IMX8MN_CLK_EXT3>; 337 clock-names = "ipg_clk", "ipg_clk_app", 338 "pll8k", "pll11k", "clkext3"; 339 dmas = <&sdma2 24 25 0x80000000>; 340 dma-names = "rx"; 341 status = "disabled"; 342 }; 343 344 spdif1: spdif@30090000 { 345 compatible = "fsl,imx35-spdif"; 346 reg = <0x30090000 0x10000>; 347 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 349 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 350 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 352 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 353 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 354 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 355 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 356 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 357 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 358 clock-names = "core", "rxtx0", 359 "rxtx1", "rxtx2", 360 "rxtx3", "rxtx4", 361 "rxtx5", "rxtx6", 362 "rxtx7", "spba"; 363 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 sai7: sai@300b0000 { 369 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 370 reg = <0x300b0000 0x10000>; 371 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 373 <&clk IMX8MN_CLK_DUMMY>, 374 <&clk IMX8MN_CLK_SAI7_ROOT>, 375 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 376 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 377 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 easrc: easrc@300c0000 { 383 compatible = "fsl,imx8mn-easrc"; 384 reg = <0x300c0000 0x10000>; 385 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 387 clock-names = "mem"; 388 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 389 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 390 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 391 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 392 dma-names = "ctx0_rx", "ctx0_tx", 393 "ctx1_rx", "ctx1_tx", 394 "ctx2_rx", "ctx2_tx", 395 "ctx3_rx", "ctx3_tx"; 396 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 397 fsl,asrc-rate = <8000>; 398 fsl,asrc-format = <2>; 399 status = "disabled"; 400 }; 401 }; 402 403 gpio1: gpio@30200000 { 404 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 405 reg = <0x30200000 0x10000>; 406 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 gpio-ranges = <&iomuxc 0 10 30>; 414 }; 415 416 gpio2: gpio@30210000 { 417 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 418 reg = <0x30210000 0x10000>; 419 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 422 gpio-controller; 423 #gpio-cells = <2>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 gpio-ranges = <&iomuxc 0 40 21>; 427 }; 428 429 gpio3: gpio@30220000 { 430 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 431 reg = <0x30220000 0x10000>; 432 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 gpio-ranges = <&iomuxc 0 61 26>; 440 }; 441 442 gpio4: gpio@30230000 { 443 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 444 reg = <0x30230000 0x10000>; 445 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 gpio-ranges = <&iomuxc 21 108 11>; 453 }; 454 455 gpio5: gpio@30240000 { 456 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 457 reg = <0x30240000 0x10000>; 458 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 gpio-ranges = <&iomuxc 0 119 30>; 466 }; 467 468 tmu: tmu@30260000 { 469 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 470 reg = <0x30260000 0x10000>; 471 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 472 #thermal-sensor-cells = <0>; 473 }; 474 475 wdog1: watchdog@30280000 { 476 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 477 reg = <0x30280000 0x10000>; 478 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 480 status = "disabled"; 481 }; 482 483 wdog2: watchdog@30290000 { 484 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 485 reg = <0x30290000 0x10000>; 486 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 488 status = "disabled"; 489 }; 490 491 wdog3: watchdog@302a0000 { 492 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 493 reg = <0x302a0000 0x10000>; 494 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 496 status = "disabled"; 497 }; 498 499 sdma3: dma-controller@302b0000 { 500 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 501 reg = <0x302b0000 0x10000>; 502 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 504 <&clk IMX8MN_CLK_SDMA3_ROOT>; 505 clock-names = "ipg", "ahb"; 506 #dma-cells = <3>; 507 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 508 }; 509 510 sdma2: dma-controller@302c0000 { 511 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 512 reg = <0x302c0000 0x10000>; 513 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 515 <&clk IMX8MN_CLK_SDMA2_ROOT>; 516 clock-names = "ipg", "ahb"; 517 #dma-cells = <3>; 518 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 519 }; 520 521 iomuxc: pinctrl@30330000 { 522 compatible = "fsl,imx8mn-iomuxc"; 523 reg = <0x30330000 0x10000>; 524 }; 525 526 gpr: iomuxc-gpr@30340000 { 527 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 528 reg = <0x30340000 0x10000>; 529 }; 530 531 ocotp: efuse@30350000 { 532 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 533 reg = <0x30350000 0x10000>; 534 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 538 imx8mn_uid: unique-id@410 { 539 reg = <0x4 0x8>; 540 }; 541 542 cpu_speed_grade: speed-grade@10 { 543 reg = <0x10 4>; 544 }; 545 546 fec_mac_address: mac-address@90 { 547 reg = <0x90 6>; 548 }; 549 }; 550 551 anatop: anatop@30360000 { 552 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 553 "syscon"; 554 reg = <0x30360000 0x10000>; 555 }; 556 557 snvs: snvs@30370000 { 558 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 559 reg = <0x30370000 0x10000>; 560 561 snvs_rtc: snvs-rtc-lp { 562 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 563 regmap = <&snvs>; 564 offset = <0x34>; 565 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 568 clock-names = "snvs-rtc"; 569 }; 570 571 snvs_pwrkey: snvs-powerkey { 572 compatible = "fsl,sec-v4.0-pwrkey"; 573 regmap = <&snvs>; 574 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 576 clock-names = "snvs-pwrkey"; 577 linux,keycode = <KEY_POWER>; 578 wakeup-source; 579 status = "disabled"; 580 }; 581 }; 582 583 clk: clock-controller@30380000 { 584 compatible = "fsl,imx8mn-ccm"; 585 reg = <0x30380000 0x10000>; 586 #clock-cells = <1>; 587 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 588 <&clk_ext3>, <&clk_ext4>; 589 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 590 "clk_ext3", "clk_ext4"; 591 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 592 <&clk IMX8MN_CLK_A53_CORE>, 593 <&clk IMX8MN_CLK_NOC>, 594 <&clk IMX8MN_CLK_AUDIO_AHB>, 595 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 596 <&clk IMX8MN_SYS_PLL3>, 597 <&clk IMX8MN_AUDIO_PLL1>, 598 <&clk IMX8MN_AUDIO_PLL2>; 599 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 600 <&clk IMX8MN_ARM_PLL_OUT>, 601 <&clk IMX8MN_SYS_PLL3_OUT>, 602 <&clk IMX8MN_SYS_PLL1_800M>; 603 assigned-clock-rates = <0>, <0>, <0>, 604 <400000000>, 605 <400000000>, 606 <600000000>, 607 <393216000>, 608 <361267200>; 609 }; 610 611 src: reset-controller@30390000 { 612 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 613 reg = <0x30390000 0x10000>; 614 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 615 #reset-cells = <1>; 616 }; 617 618 gpc: gpc@303a0000 { 619 compatible = "fsl,imx8mn-gpc"; 620 reg = <0x303a0000 0x10000>; 621 interrupt-parent = <&gic>; 622 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 623 624 pgc { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 628 pgc_hsiomix: power-domain@0 { 629 #power-domain-cells = <0>; 630 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 631 clocks = <&clk IMX8MN_CLK_USB_BUS>; 632 }; 633 634 pgc_otg1: power-domain@1 { 635 #power-domain-cells = <0>; 636 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 637 power-domains = <&pgc_hsiomix>; 638 }; 639 640 pgc_gpumix: power-domain@2 { 641 #power-domain-cells = <0>; 642 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 643 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 644 <&clk IMX8MN_CLK_GPU_SHADER_DIV>, 645 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 646 <&clk IMX8MN_CLK_GPU_AHB>; 647 resets = <&src IMX8MQ_RESET_GPU_RESET>; 648 }; 649 650 dispmix_pd: power-domain@3 { 651 #power-domain-cells = <0>; 652 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 653 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 654 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 655 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 656 }; 657 658 mipi_pd: power-domain@4 { 659 #power-domain-cells = <0>; 660 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 661 power-domains = <&dispmix_pd>; 662 }; 663 }; 664 }; 665 }; 666 667 aips2: bus@30400000 { 668 compatible = "fsl,aips-bus", "simple-bus"; 669 reg = <0x30400000 0x400000>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 ranges; 673 674 pwm1: pwm@30660000 { 675 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 676 reg = <0x30660000 0x10000>; 677 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 679 <&clk IMX8MN_CLK_PWM1_ROOT>; 680 clock-names = "ipg", "per"; 681 #pwm-cells = <2>; 682 status = "disabled"; 683 }; 684 685 pwm2: pwm@30670000 { 686 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 687 reg = <0x30670000 0x10000>; 688 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 690 <&clk IMX8MN_CLK_PWM2_ROOT>; 691 clock-names = "ipg", "per"; 692 #pwm-cells = <2>; 693 status = "disabled"; 694 }; 695 696 pwm3: pwm@30680000 { 697 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 698 reg = <0x30680000 0x10000>; 699 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 701 <&clk IMX8MN_CLK_PWM3_ROOT>; 702 clock-names = "ipg", "per"; 703 #pwm-cells = <2>; 704 status = "disabled"; 705 }; 706 707 pwm4: pwm@30690000 { 708 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 709 reg = <0x30690000 0x10000>; 710 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 712 <&clk IMX8MN_CLK_PWM4_ROOT>; 713 clock-names = "ipg", "per"; 714 #pwm-cells = <2>; 715 status = "disabled"; 716 }; 717 718 system_counter: timer@306a0000 { 719 compatible = "nxp,sysctr-timer"; 720 reg = <0x306a0000 0x20000>; 721 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&osc_24m>; 723 clock-names = "per"; 724 }; 725 }; 726 727 aips3: bus@30800000 { 728 compatible = "fsl,aips-bus", "simple-bus"; 729 reg = <0x30800000 0x400000>; 730 #address-cells = <1>; 731 #size-cells = <1>; 732 ranges; 733 734 ecspi1: spi@30820000 { 735 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 reg = <0x30820000 0x10000>; 739 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 741 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 742 clock-names = "ipg", "per"; 743 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 }; 747 748 ecspi2: spi@30830000 { 749 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 reg = <0x30830000 0x10000>; 753 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 755 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 756 clock-names = "ipg", "per"; 757 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 758 dma-names = "rx", "tx"; 759 status = "disabled"; 760 }; 761 762 ecspi3: spi@30840000 { 763 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 reg = <0x30840000 0x10000>; 767 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 769 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 770 clock-names = "ipg", "per"; 771 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 uart1: serial@30860000 { 777 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 778 reg = <0x30860000 0x10000>; 779 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 781 <&clk IMX8MN_CLK_UART1_ROOT>; 782 clock-names = "ipg", "per"; 783 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 784 dma-names = "rx", "tx"; 785 status = "disabled"; 786 }; 787 788 uart3: serial@30880000 { 789 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 790 reg = <0x30880000 0x10000>; 791 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 793 <&clk IMX8MN_CLK_UART3_ROOT>; 794 clock-names = "ipg", "per"; 795 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 796 dma-names = "rx", "tx"; 797 status = "disabled"; 798 }; 799 800 uart2: serial@30890000 { 801 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 802 reg = <0x30890000 0x10000>; 803 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 805 <&clk IMX8MN_CLK_UART2_ROOT>; 806 clock-names = "ipg", "per"; 807 status = "disabled"; 808 }; 809 810 crypto: crypto@30900000 { 811 compatible = "fsl,sec-v4.0"; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 reg = <0x30900000 0x40000>; 815 ranges = <0 0x30900000 0x40000>; 816 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&clk IMX8MN_CLK_AHB>, 818 <&clk IMX8MN_CLK_IPG_ROOT>; 819 clock-names = "aclk", "ipg"; 820 821 sec_jr0: jr@1000 { 822 compatible = "fsl,sec-v4.0-job-ring"; 823 reg = <0x1000 0x1000>; 824 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 825 }; 826 827 sec_jr1: jr@2000 { 828 compatible = "fsl,sec-v4.0-job-ring"; 829 reg = <0x2000 0x1000>; 830 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 831 }; 832 833 sec_jr2: jr@3000 { 834 compatible = "fsl,sec-v4.0-job-ring"; 835 reg = <0x3000 0x1000>; 836 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 837 }; 838 }; 839 840 i2c1: i2c@30a20000 { 841 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 reg = <0x30a20000 0x10000>; 845 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 847 status = "disabled"; 848 }; 849 850 i2c2: i2c@30a30000 { 851 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 reg = <0x30a30000 0x10000>; 855 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 857 status = "disabled"; 858 }; 859 860 i2c3: i2c@30a40000 { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 864 reg = <0x30a40000 0x10000>; 865 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 867 status = "disabled"; 868 }; 869 870 i2c4: i2c@30a50000 { 871 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 reg = <0x30a50000 0x10000>; 875 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 877 status = "disabled"; 878 }; 879 880 uart4: serial@30a60000 { 881 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 882 reg = <0x30a60000 0x10000>; 883 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 885 <&clk IMX8MN_CLK_UART4_ROOT>; 886 clock-names = "ipg", "per"; 887 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 888 dma-names = "rx", "tx"; 889 status = "disabled"; 890 }; 891 892 mu: mailbox@30aa0000 { 893 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 894 reg = <0x30aa0000 0x10000>; 895 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 897 #mbox-cells = <2>; 898 }; 899 900 usdhc1: mmc@30b40000 { 901 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 902 reg = <0x30b40000 0x10000>; 903 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 905 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 906 <&clk IMX8MN_CLK_USDHC1_ROOT>; 907 clock-names = "ipg", "ahb", "per"; 908 fsl,tuning-start-tap = <20>; 909 fsl,tuning-step= <2>; 910 bus-width = <4>; 911 status = "disabled"; 912 }; 913 914 usdhc2: mmc@30b50000 { 915 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 916 reg = <0x30b50000 0x10000>; 917 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 919 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 920 <&clk IMX8MN_CLK_USDHC2_ROOT>; 921 clock-names = "ipg", "ahb", "per"; 922 fsl,tuning-start-tap = <20>; 923 fsl,tuning-step= <2>; 924 bus-width = <4>; 925 status = "disabled"; 926 }; 927 928 usdhc3: mmc@30b60000 { 929 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 930 reg = <0x30b60000 0x10000>; 931 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 933 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 934 <&clk IMX8MN_CLK_USDHC3_ROOT>; 935 clock-names = "ipg", "ahb", "per"; 936 fsl,tuning-start-tap = <20>; 937 fsl,tuning-step= <2>; 938 bus-width = <4>; 939 status = "disabled"; 940 }; 941 942 flexspi: spi@30bb0000 { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 compatible = "nxp,imx8mm-fspi"; 946 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 947 reg-names = "fspi_base", "fspi_mmap"; 948 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 950 <&clk IMX8MN_CLK_QSPI_ROOT>; 951 clock-names = "fspi", "fspi_en"; 952 status = "disabled"; 953 }; 954 955 sdma1: dma-controller@30bd0000 { 956 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 957 reg = <0x30bd0000 0x10000>; 958 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 960 <&clk IMX8MN_CLK_AHB>; 961 clock-names = "ipg", "ahb"; 962 #dma-cells = <3>; 963 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 964 }; 965 966 fec1: ethernet@30be0000 { 967 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 968 reg = <0x30be0000 0x10000>; 969 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 974 <&clk IMX8MN_CLK_ENET1_ROOT>, 975 <&clk IMX8MN_CLK_ENET_TIMER>, 976 <&clk IMX8MN_CLK_ENET_REF>, 977 <&clk IMX8MN_CLK_ENET_PHY_REF>; 978 clock-names = "ipg", "ahb", "ptp", 979 "enet_clk_ref", "enet_out"; 980 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 981 <&clk IMX8MN_CLK_ENET_TIMER>, 982 <&clk IMX8MN_CLK_ENET_REF>, 983 <&clk IMX8MN_CLK_ENET_PHY_REF>; 984 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 985 <&clk IMX8MN_SYS_PLL2_100M>, 986 <&clk IMX8MN_SYS_PLL2_125M>, 987 <&clk IMX8MN_SYS_PLL2_50M>; 988 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 989 fsl,num-tx-queues = <3>; 990 fsl,num-rx-queues = <3>; 991 nvmem-cells = <&fec_mac_address>; 992 nvmem-cell-names = "mac-address"; 993 nvmem_macaddr_swap; 994 fsl,stop-mode = <&gpr 0x10 3>; 995 status = "disabled"; 996 }; 997 998 }; 999 1000 aips4: bus@32c00000 { 1001 compatible = "fsl,aips-bus", "simple-bus"; 1002 reg = <0x32c00000 0x400000>; 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 ranges; 1006 1007 usbotg1: usb@32e40000 { 1008 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 1009 reg = <0x32e40000 0x200>; 1010 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1012 clock-names = "usb1_ctrl_root_clk"; 1013 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1014 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1015 phys = <&usbphynop1>; 1016 fsl,usbmisc = <&usbmisc1 0>; 1017 power-domains = <&pgc_otg1>; 1018 status = "disabled"; 1019 }; 1020 1021 usbmisc1: usbmisc@32e40200 { 1022 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 1023 #index-cells = <1>; 1024 reg = <0x32e40200 0x200>; 1025 }; 1026 }; 1027 1028 dma_apbh: dma-controller@33000000 { 1029 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1030 reg = <0x33000000 0x2000>; 1031 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1036 #dma-cells = <1>; 1037 dma-channels = <4>; 1038 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1039 }; 1040 1041 gpmi: nand-controller@33002000 { 1042 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1043 #address-cells = <1>; 1044 #size-cells = <1>; 1045 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1046 reg-names = "gpmi-nand", "bch"; 1047 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1048 interrupt-names = "bch"; 1049 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1050 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1051 clock-names = "gpmi_io", "gpmi_bch_apb"; 1052 dmas = <&dma_apbh 0>; 1053 dma-names = "rx-tx"; 1054 status = "disabled"; 1055 }; 1056 1057 gic: interrupt-controller@38800000 { 1058 compatible = "arm,gic-v3"; 1059 reg = <0x38800000 0x10000>, 1060 <0x38880000 0xc0000>; 1061 #interrupt-cells = <3>; 1062 interrupt-controller; 1063 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1064 }; 1065 1066 ddrc: memory-controller@3d400000 { 1067 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1068 reg = <0x3d400000 0x400000>; 1069 clock-names = "core", "pll", "alt", "apb"; 1070 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1071 <&clk IMX8MN_DRAM_PLL>, 1072 <&clk IMX8MN_CLK_DRAM_ALT>, 1073 <&clk IMX8MN_CLK_DRAM_APB>; 1074 }; 1075 1076 ddr-pmu@3d800000 { 1077 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1078 reg = <0x3d800000 0x400000>; 1079 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1080 }; 1081 }; 1082 1083 usbphynop1: usbphynop1 { 1084 #phy-cells = <0>; 1085 compatible = "usb-nop-xceiv"; 1086 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1087 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1088 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1089 clock-names = "main_clk"; 1090 }; 1091}; 1092