1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 39 /* 40 * vcpumntirq: 41 * virtual CPU interface maintenance interrupt 42 */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 serdes0: serdes@900000 { 55 compatible = "ti,phy-am654-serdes"; 56 reg = <0x0 0x900000 0x0 0x2000>; 57 reg-names = "serdes"; 58 #phy-cells = <2>; 59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 64 ti,serdes-clk = <&serdes0_clk>; 65 #clock-cells = <1>; 66 mux-controls = <&serdes_mux 0>; 67 }; 68 69 serdes1: serdes@910000 { 70 compatible = "ti,phy-am654-serdes"; 71 reg = <0x0 0x910000 0x0 0x2000>; 72 reg-names = "serdes"; 73 #phy-cells = <2>; 74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 79 ti,serdes-clk = <&serdes1_clk>; 80 #clock-cells = <1>; 81 mux-controls = <&serdes_mux 1>; 82 }; 83 84 main_uart0: serial@2800000 { 85 compatible = "ti,am654-uart"; 86 reg = <0x00 0x02800000 0x00 0x100>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 90 clock-frequency = <48000000>; 91 current-speed = <115200>; 92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 93 }; 94 95 main_uart1: serial@2810000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02810000 0x00 0x100>; 98 reg-shift = <2>; 99 reg-io-width = <4>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 }; 104 105 main_uart2: serial@2820000 { 106 compatible = "ti,am654-uart"; 107 reg = <0x00 0x02820000 0x00 0x100>; 108 reg-shift = <2>; 109 reg-io-width = <4>; 110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 111 clock-frequency = <48000000>; 112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 124 <&main_udmap 0x4001>; 125 dma-names = "tx", "rx1", "rx2"; 126 dma-coherent; 127 128 rng: rng@4e10000 { 129 compatible = "inside-secure,safexcel-eip76"; 130 reg = <0x0 0x4e10000 0x0 0x7d>; 131 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&k3_clks 136 1>; 133 }; 134 }; 135 136 main_pmx0: pinctrl@11c000 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x11c000 0x0 0x2e4>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0xffffffff>; 142 }; 143 144 main_pmx1: pinctrl@11c2e8 { 145 compatible = "pinctrl-single"; 146 reg = <0x0 0x11c2e8 0x0 0x24>; 147 #pinctrl-cells = <1>; 148 pinctrl-single,register-width = <32>; 149 pinctrl-single,function-mask = <0xffffffff>; 150 }; 151 152 main_i2c0: i2c@2000000 { 153 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 154 reg = <0x0 0x2000000 0x0 0x100>; 155 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clock-names = "fck"; 159 clocks = <&k3_clks 110 1>; 160 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 161 }; 162 163 main_i2c1: i2c@2010000 { 164 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 165 reg = <0x0 0x2010000 0x0 0x100>; 166 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clock-names = "fck"; 170 clocks = <&k3_clks 111 1>; 171 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 172 }; 173 174 main_i2c2: i2c@2020000 { 175 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 176 reg = <0x0 0x2020000 0x0 0x100>; 177 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clock-names = "fck"; 181 clocks = <&k3_clks 112 1>; 182 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 183 }; 184 185 main_i2c3: i2c@2030000 { 186 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 187 reg = <0x0 0x2030000 0x0 0x100>; 188 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 clock-names = "fck"; 192 clocks = <&k3_clks 113 1>; 193 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 194 }; 195 196 ecap0: pwm@3100000 { 197 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 198 #pwm-cells = <3>; 199 reg = <0x0 0x03100000 0x0 0x60>; 200 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 201 clocks = <&k3_clks 39 0>; 202 clock-names = "fck"; 203 }; 204 205 main_spi0: spi@2100000 { 206 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 207 reg = <0x0 0x2100000 0x0 0x400>; 208 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 137 1>; 210 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 214 dma-names = "tx0", "rx0"; 215 }; 216 217 main_spi1: spi@2110000 { 218 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 219 reg = <0x0 0x2110000 0x0 0x400>; 220 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&k3_clks 138 1>; 222 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 assigned-clocks = <&k3_clks 137 1>; 226 assigned-clock-rates = <48000000>; 227 }; 228 229 main_spi2: spi@2120000 { 230 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 231 reg = <0x0 0x2120000 0x0 0x400>; 232 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&k3_clks 139 1>; 234 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 main_spi3: spi@2130000 { 240 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 241 reg = <0x0 0x2130000 0x0 0x400>; 242 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&k3_clks 140 1>; 244 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 main_spi4: spi@2140000 { 250 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 251 reg = <0x0 0x2140000 0x0 0x400>; 252 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&k3_clks 141 1>; 254 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 sdhci0: sdhci@4f80000 { 260 compatible = "ti,am654-sdhci-5.1"; 261 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 262 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 264 clock-names = "clk_ahb", "clk_xin"; 265 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 266 mmc-ddr-1_8v; 267 mmc-hs200-1_8v; 268 ti,otap-del-sel-legacy = <0x0>; 269 ti,otap-del-sel-mmc-hs = <0x0>; 270 ti,otap-del-sel-sd-hs = <0x0>; 271 ti,otap-del-sel-sdr12 = <0x0>; 272 ti,otap-del-sel-sdr25 = <0x0>; 273 ti,otap-del-sel-sdr50 = <0x8>; 274 ti,otap-del-sel-sdr104 = <0x5>; 275 ti,otap-del-sel-ddr50 = <0x5>; 276 ti,otap-del-sel-ddr52 = <0x5>; 277 ti,otap-del-sel-hs200 = <0x5>; 278 ti,otap-del-sel-hs400 = <0x0>; 279 ti,itap-del-sel-legacy = <0xa>; 280 ti,itap-del-sel-mmc-hs = <0x1>; 281 ti,itap-del-sel-sdr12 = <0xa>; 282 ti,itap-del-sel-sdr25 = <0x1>; 283 ti,clkbuf-sel = <0x7>; 284 ti,trm-icp = <0x8>; 285 dma-coherent; 286 }; 287 288 sdhci1: sdhci@4fa0000 { 289 compatible = "ti,am654-sdhci-5.1"; 290 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 291 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 292 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 293 clock-names = "clk_ahb", "clk_xin"; 294 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 295 ti,otap-del-sel-legacy = <0x0>; 296 ti,otap-del-sel-mmc-hs = <0x0>; 297 ti,otap-del-sel-sd-hs = <0x0>; 298 ti,otap-del-sel-sdr12 = <0x0>; 299 ti,otap-del-sel-sdr25 = <0x0>; 300 ti,otap-del-sel-sdr50 = <0x8>; 301 ti,otap-del-sel-sdr104 = <0x7>; 302 ti,otap-del-sel-ddr50 = <0x4>; 303 ti,otap-del-sel-ddr52 = <0x4>; 304 ti,otap-del-sel-hs200 = <0x7>; 305 ti,itap-del-sel-legacy = <0xa>; 306 ti,itap-del-sel-mmc-hs = <0x1>; 307 ti,itap-del-sel-sdr12 = <0xa>; 308 ti,itap-del-sel-sdr25 = <0x1>; 309 ti,clkbuf-sel = <0x7>; 310 ti,trm-icp = <0x8>; 311 dma-coherent; 312 }; 313 314 scm_conf: scm-conf@100000 { 315 compatible = "syscon", "simple-mfd"; 316 reg = <0 0x00100000 0 0x1c000>; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0x0 0x0 0x00100000 0x1c000>; 320 321 pcie0_mode: pcie-mode@4060 { 322 compatible = "syscon"; 323 reg = <0x00004060 0x4>; 324 }; 325 326 pcie1_mode: pcie-mode@4070 { 327 compatible = "syscon"; 328 reg = <0x00004070 0x4>; 329 }; 330 331 pcie_devid: pcie-devid@210 { 332 compatible = "syscon"; 333 reg = <0x00000210 0x4>; 334 }; 335 336 serdes0_clk: clock@4080 { 337 compatible = "syscon"; 338 reg = <0x00004080 0x4>; 339 }; 340 341 serdes1_clk: clock@4090 { 342 compatible = "syscon"; 343 reg = <0x00004090 0x4>; 344 }; 345 346 serdes_mux: mux-controller { 347 compatible = "mmio-mux"; 348 #mux-control-cells = <1>; 349 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 350 <0x4090 0x3>; /* SERDES1 lane select */ 351 }; 352 353 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 354 compatible = "syscon"; 355 reg = <0x0000041e0 0x14>; 356 }; 357 358 ehrpwm_tbclk: clock@4140 { 359 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 360 reg = <0x4140 0x18>; 361 #clock-cells = <1>; 362 }; 363 }; 364 365 dwc3_0: dwc3@4000000 { 366 compatible = "ti,am654-dwc3"; 367 reg = <0x0 0x4000000 0x0 0x4000>; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x0 0x0 0x4000000 0x20000>; 371 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 372 dma-coherent; 373 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 375 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 376 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 377 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 378 379 usb0: usb@10000 { 380 compatible = "snps,dwc3"; 381 reg = <0x10000 0x10000>; 382 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-names = "peripheral", 386 "host", 387 "otg"; 388 maximum-speed = "high-speed"; 389 dr_mode = "otg"; 390 phys = <&usb0_phy>; 391 phy-names = "usb2-phy"; 392 snps,dis_u3_susphy_quirk; 393 }; 394 }; 395 396 usb0_phy: phy@4100000 { 397 compatible = "ti,am654-usb2", "ti,omap-usb2"; 398 reg = <0x0 0x4100000 0x0 0x54>; 399 syscon-phy-power = <&scm_conf 0x4000>; 400 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 401 clock-names = "wkupclk", "refclk"; 402 #phy-cells = <0>; 403 }; 404 405 dwc3_1: dwc3@4020000 { 406 compatible = "ti,am654-dwc3"; 407 reg = <0x0 0x4020000 0x0 0x4000>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0x0 0x0 0x4020000 0x20000>; 411 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 412 dma-coherent; 413 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 414 clocks = <&k3_clks 152 2>; 415 assigned-clocks = <&k3_clks 152 2>; 416 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 417 418 usb1: usb@10000 { 419 compatible = "snps,dwc3"; 420 reg = <0x10000 0x10000>; 421 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-names = "peripheral", 425 "host", 426 "otg"; 427 maximum-speed = "high-speed"; 428 dr_mode = "otg"; 429 phys = <&usb1_phy>; 430 phy-names = "usb2-phy"; 431 }; 432 }; 433 434 usb1_phy: phy@4110000 { 435 compatible = "ti,am654-usb2", "ti,omap-usb2"; 436 reg = <0x0 0x4110000 0x0 0x54>; 437 syscon-phy-power = <&scm_conf 0x4020>; 438 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 439 clock-names = "wkupclk", "refclk"; 440 #phy-cells = <0>; 441 }; 442 443 intr_main_gpio: interrupt-controller0 { 444 compatible = "ti,sci-intr"; 445 ti,intr-trigger-type = <1>; 446 interrupt-controller; 447 interrupt-parent = <&gic500>; 448 #interrupt-cells = <1>; 449 ti,sci = <&dmsc>; 450 ti,sci-dev-id = <100>; 451 ti,interrupt-ranges = <0 392 32>; 452 }; 453 454 main-navss { 455 compatible = "simple-mfd"; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 dma-coherent; 460 dma-ranges; 461 462 ti,sci-dev-id = <118>; 463 464 intr_main_navss: interrupt-controller1 { 465 compatible = "ti,sci-intr"; 466 ti,intr-trigger-type = <4>; 467 interrupt-controller; 468 interrupt-parent = <&gic500>; 469 #interrupt-cells = <1>; 470 ti,sci = <&dmsc>; 471 ti,sci-dev-id = <182>; 472 ti,interrupt-ranges = <0 64 64>, 473 <64 448 64>; 474 }; 475 476 inta_main_udmass: interrupt-controller@33d00000 { 477 compatible = "ti,sci-inta"; 478 reg = <0x0 0x33d00000 0x0 0x100000>; 479 interrupt-controller; 480 interrupt-parent = <&intr_main_navss>; 481 msi-controller; 482 #interrupt-cells = <0>; 483 ti,sci = <&dmsc>; 484 ti,sci-dev-id = <179>; 485 ti,interrupt-ranges = <0 0 256>; 486 }; 487 488 secure_proxy_main: mailbox@32c00000 { 489 compatible = "ti,am654-secure-proxy"; 490 #mbox-cells = <1>; 491 reg-names = "target_data", "rt", "scfg"; 492 reg = <0x00 0x32c00000 0x00 0x100000>, 493 <0x00 0x32400000 0x00 0x100000>, 494 <0x00 0x32800000 0x00 0x100000>; 495 interrupt-names = "rx_011"; 496 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 497 }; 498 499 hwspinlock: spinlock@30e00000 { 500 compatible = "ti,am654-hwspinlock"; 501 reg = <0x00 0x30e00000 0x00 0x1000>; 502 #hwlock-cells = <1>; 503 }; 504 505 mailbox0_cluster0: mailbox@31f80000 { 506 compatible = "ti,am654-mailbox"; 507 reg = <0x00 0x31f80000 0x00 0x200>; 508 #mbox-cells = <1>; 509 ti,mbox-num-users = <4>; 510 ti,mbox-num-fifos = <16>; 511 interrupt-parent = <&intr_main_navss>; 512 }; 513 514 mailbox0_cluster1: mailbox@31f81000 { 515 compatible = "ti,am654-mailbox"; 516 reg = <0x00 0x31f81000 0x00 0x200>; 517 #mbox-cells = <1>; 518 ti,mbox-num-users = <4>; 519 ti,mbox-num-fifos = <16>; 520 interrupt-parent = <&intr_main_navss>; 521 }; 522 523 mailbox0_cluster2: mailbox@31f82000 { 524 compatible = "ti,am654-mailbox"; 525 reg = <0x00 0x31f82000 0x00 0x200>; 526 #mbox-cells = <1>; 527 ti,mbox-num-users = <4>; 528 ti,mbox-num-fifos = <16>; 529 interrupt-parent = <&intr_main_navss>; 530 }; 531 532 mailbox0_cluster3: mailbox@31f83000 { 533 compatible = "ti,am654-mailbox"; 534 reg = <0x00 0x31f83000 0x00 0x200>; 535 #mbox-cells = <1>; 536 ti,mbox-num-users = <4>; 537 ti,mbox-num-fifos = <16>; 538 interrupt-parent = <&intr_main_navss>; 539 }; 540 541 mailbox0_cluster4: mailbox@31f84000 { 542 compatible = "ti,am654-mailbox"; 543 reg = <0x00 0x31f84000 0x00 0x200>; 544 #mbox-cells = <1>; 545 ti,mbox-num-users = <4>; 546 ti,mbox-num-fifos = <16>; 547 interrupt-parent = <&intr_main_navss>; 548 }; 549 550 mailbox0_cluster5: mailbox@31f85000 { 551 compatible = "ti,am654-mailbox"; 552 reg = <0x00 0x31f85000 0x00 0x200>; 553 #mbox-cells = <1>; 554 ti,mbox-num-users = <4>; 555 ti,mbox-num-fifos = <16>; 556 interrupt-parent = <&intr_main_navss>; 557 }; 558 559 mailbox0_cluster6: mailbox@31f86000 { 560 compatible = "ti,am654-mailbox"; 561 reg = <0x00 0x31f86000 0x00 0x200>; 562 #mbox-cells = <1>; 563 ti,mbox-num-users = <4>; 564 ti,mbox-num-fifos = <16>; 565 interrupt-parent = <&intr_main_navss>; 566 }; 567 568 mailbox0_cluster7: mailbox@31f87000 { 569 compatible = "ti,am654-mailbox"; 570 reg = <0x00 0x31f87000 0x00 0x200>; 571 #mbox-cells = <1>; 572 ti,mbox-num-users = <4>; 573 ti,mbox-num-fifos = <16>; 574 interrupt-parent = <&intr_main_navss>; 575 }; 576 577 mailbox0_cluster8: mailbox@31f88000 { 578 compatible = "ti,am654-mailbox"; 579 reg = <0x00 0x31f88000 0x00 0x200>; 580 #mbox-cells = <1>; 581 ti,mbox-num-users = <4>; 582 ti,mbox-num-fifos = <16>; 583 interrupt-parent = <&intr_main_navss>; 584 }; 585 586 mailbox0_cluster9: mailbox@31f89000 { 587 compatible = "ti,am654-mailbox"; 588 reg = <0x00 0x31f89000 0x00 0x200>; 589 #mbox-cells = <1>; 590 ti,mbox-num-users = <4>; 591 ti,mbox-num-fifos = <16>; 592 interrupt-parent = <&intr_main_navss>; 593 }; 594 595 mailbox0_cluster10: mailbox@31f8a000 { 596 compatible = "ti,am654-mailbox"; 597 reg = <0x00 0x31f8a000 0x00 0x200>; 598 #mbox-cells = <1>; 599 ti,mbox-num-users = <4>; 600 ti,mbox-num-fifos = <16>; 601 interrupt-parent = <&intr_main_navss>; 602 }; 603 604 mailbox0_cluster11: mailbox@31f8b000 { 605 compatible = "ti,am654-mailbox"; 606 reg = <0x00 0x31f8b000 0x00 0x200>; 607 #mbox-cells = <1>; 608 ti,mbox-num-users = <4>; 609 ti,mbox-num-fifos = <16>; 610 interrupt-parent = <&intr_main_navss>; 611 }; 612 613 ringacc: ringacc@3c000000 { 614 compatible = "ti,am654-navss-ringacc"; 615 reg = <0x0 0x3c000000 0x0 0x400000>, 616 <0x0 0x38000000 0x0 0x400000>, 617 <0x0 0x31120000 0x0 0x100>, 618 <0x0 0x33000000 0x0 0x40000>; 619 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 620 ti,num-rings = <818>; 621 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 622 ti,sci = <&dmsc>; 623 ti,sci-dev-id = <187>; 624 msi-parent = <&inta_main_udmass>; 625 }; 626 627 main_udmap: dma-controller@31150000 { 628 compatible = "ti,am654-navss-main-udmap"; 629 reg = <0x0 0x31150000 0x0 0x100>, 630 <0x0 0x34000000 0x0 0x100000>, 631 <0x0 0x35000000 0x0 0x100000>; 632 reg-names = "gcfg", "rchanrt", "tchanrt"; 633 msi-parent = <&inta_main_udmass>; 634 #dma-cells = <1>; 635 636 ti,sci = <&dmsc>; 637 ti,sci-dev-id = <188>; 638 ti,ringacc = <&ringacc>; 639 640 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 641 <0xd>; /* TX_CHAN */ 642 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 643 <0xa>; /* RX_CHAN */ 644 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 645 }; 646 647 cpts@310d0000 { 648 compatible = "ti,am65-cpts"; 649 reg = <0x0 0x310d0000 0x0 0x400>; 650 reg-names = "cpts"; 651 clocks = <&main_cpts_mux>; 652 clock-names = "cpts"; 653 interrupts-extended = <&intr_main_navss 391>; 654 interrupt-names = "cpts"; 655 ti,cpts-periodic-outputs = <6>; 656 ti,cpts-ext-ts-inputs = <8>; 657 658 main_cpts_mux: refclk-mux { 659 #clock-cells = <0>; 660 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 661 <&k3_clks 118 6>, <&k3_clks 118 3>, 662 <&k3_clks 118 8>, <&k3_clks 118 14>, 663 <&k3_clks 120 3>, <&k3_clks 121 3>; 664 assigned-clocks = <&main_cpts_mux>; 665 assigned-clock-parents = <&k3_clks 118 5>; 666 }; 667 }; 668 }; 669 670 main_gpio0: gpio@600000 { 671 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 672 reg = <0x0 0x600000 0x0 0x100>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 interrupt-parent = <&intr_main_gpio>; 676 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 ti,ngpio = <96>; 680 ti,davinci-gpio-unbanked = <0>; 681 clocks = <&k3_clks 57 0>; 682 clock-names = "gpio"; 683 }; 684 685 main_gpio1: gpio@601000 { 686 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 687 reg = <0x0 0x601000 0x0 0x100>; 688 gpio-controller; 689 #gpio-cells = <2>; 690 interrupt-parent = <&intr_main_gpio>; 691 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 ti,ngpio = <90>; 695 ti,davinci-gpio-unbanked = <0>; 696 clocks = <&k3_clks 58 0>; 697 clock-names = "gpio"; 698 }; 699 700 pcie0_rc: pcie@5500000 { 701 compatible = "ti,am654-pcie-rc"; 702 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 703 reg-names = "app", "dbics", "config", "atu"; 704 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 705 #address-cells = <3>; 706 #size-cells = <2>; 707 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 708 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 709 ti,syscon-pcie-id = <&pcie_devid>; 710 ti,syscon-pcie-mode = <&pcie0_mode>; 711 bus-range = <0x0 0xff>; 712 num-viewport = <16>; 713 max-link-speed = <2>; 714 dma-coherent; 715 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 716 msi-map = <0x0 &gic_its 0x0 0x10000>; 717 }; 718 719 pcie0_ep: pcie-ep@5500000 { 720 compatible = "ti,am654-pcie-ep"; 721 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 722 reg-names = "app", "dbics", "addr_space", "atu"; 723 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 724 ti,syscon-pcie-mode = <&pcie0_mode>; 725 num-ib-windows = <16>; 726 num-ob-windows = <16>; 727 max-link-speed = <2>; 728 dma-coherent; 729 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 730 }; 731 732 pcie1_rc: pcie@5600000 { 733 compatible = "ti,am654-pcie-rc"; 734 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 735 reg-names = "app", "dbics", "config", "atu"; 736 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 737 #address-cells = <3>; 738 #size-cells = <2>; 739 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 740 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 741 ti,syscon-pcie-id = <&pcie_devid>; 742 ti,syscon-pcie-mode = <&pcie1_mode>; 743 bus-range = <0x0 0xff>; 744 num-viewport = <16>; 745 max-link-speed = <2>; 746 dma-coherent; 747 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 748 msi-map = <0x0 &gic_its 0x10000 0x10000>; 749 }; 750 751 pcie1_ep: pcie-ep@5600000 { 752 compatible = "ti,am654-pcie-ep"; 753 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 754 reg-names = "app", "dbics", "addr_space", "atu"; 755 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 756 ti,syscon-pcie-mode = <&pcie1_mode>; 757 num-ib-windows = <16>; 758 num-ob-windows = <16>; 759 max-link-speed = <2>; 760 dma-coherent; 761 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 762 }; 763 764 mcasp0: mcasp@2b00000 { 765 compatible = "ti,am33xx-mcasp-audio"; 766 reg = <0x0 0x02b00000 0x0 0x2000>, 767 <0x0 0x02b08000 0x0 0x1000>; 768 reg-names = "mpu","dat"; 769 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-names = "tx", "rx"; 772 773 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 774 dma-names = "tx", "rx"; 775 776 clocks = <&k3_clks 104 0>; 777 clock-names = "fck"; 778 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 779 }; 780 781 mcasp1: mcasp@2b10000 { 782 compatible = "ti,am33xx-mcasp-audio"; 783 reg = <0x0 0x02b10000 0x0 0x2000>, 784 <0x0 0x02b18000 0x0 0x1000>; 785 reg-names = "mpu","dat"; 786 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "tx", "rx"; 789 790 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 791 dma-names = "tx", "rx"; 792 793 clocks = <&k3_clks 105 0>; 794 clock-names = "fck"; 795 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 796 }; 797 798 mcasp2: mcasp@2b20000 { 799 compatible = "ti,am33xx-mcasp-audio"; 800 reg = <0x0 0x02b20000 0x0 0x2000>, 801 <0x0 0x02b28000 0x0 0x1000>; 802 reg-names = "mpu","dat"; 803 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "tx", "rx"; 806 807 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 808 dma-names = "tx", "rx"; 809 810 clocks = <&k3_clks 106 0>; 811 clock-names = "fck"; 812 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 813 }; 814 815 cal: cal@6f03000 { 816 compatible = "ti,am654-cal"; 817 reg = <0x0 0x06f03000 0x0 0x400>, 818 <0x0 0x06f03800 0x0 0x40>; 819 reg-names = "cal_top", 820 "cal_rx_core0"; 821 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 822 ti,camerrx-control = <&scm_conf 0x40c0>; 823 clock-names = "fck"; 824 clocks = <&k3_clks 2 0>; 825 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 826 827 ports { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 csi2_0: port@0 { 832 reg = <0>; 833 }; 834 }; 835 }; 836 837 dss: dss@4a00000 { 838 compatible = "ti,am65x-dss"; 839 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 840 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 841 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 842 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 843 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 844 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 845 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 846 reg-names = "common", "vidl1", "vid", 847 "ovr1", "ovr2", "vp1", "vp2"; 848 849 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 850 851 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 852 853 clocks = <&k3_clks 67 1>, 854 <&k3_clks 216 1>, 855 <&k3_clks 67 2>; 856 clock-names = "fck", "vp1", "vp2"; 857 858 /* 859 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 860 * DIV1. See "Figure 12-3365. DSS Integration" 861 * in AM65x TRM for details. 862 */ 863 assigned-clocks = <&k3_clks 67 2>; 864 assigned-clock-parents = <&k3_clks 67 5>; 865 866 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 867 868 dma-coherent; 869 870 dss_ports: ports { 871 #address-cells = <1>; 872 #size-cells = <0>; 873 }; 874 }; 875 876 ehrpwm0: pwm@3000000 { 877 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 878 #pwm-cells = <3>; 879 reg = <0x0 0x3000000 0x0 0x100>; 880 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 881 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 882 clock-names = "tbclk", "fck"; 883 }; 884 885 ehrpwm1: pwm@3010000 { 886 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 887 #pwm-cells = <3>; 888 reg = <0x0 0x3010000 0x0 0x100>; 889 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 890 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 891 clock-names = "tbclk", "fck"; 892 }; 893 894 ehrpwm2: pwm@3020000 { 895 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 896 #pwm-cells = <3>; 897 reg = <0x0 0x3020000 0x0 0x100>; 898 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 899 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 900 clock-names = "tbclk", "fck"; 901 }; 902 903 ehrpwm3: pwm@3030000 { 904 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 905 #pwm-cells = <3>; 906 reg = <0x0 0x3030000 0x0 0x100>; 907 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 908 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 909 clock-names = "tbclk", "fck"; 910 }; 911 912 ehrpwm4: pwm@3040000 { 913 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 914 #pwm-cells = <3>; 915 reg = <0x0 0x3040000 0x0 0x100>; 916 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 917 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 918 clock-names = "tbclk", "fck"; 919 }; 920 921 ehrpwm5: pwm@3050000 { 922 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 923 #pwm-cells = <3>; 924 reg = <0x0 0x3050000 0x0 0x100>; 925 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 926 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 927 clock-names = "tbclk", "fck"; 928 }; 929}; 930