1&l4_abe {						/* 0x40100000 */
2	compatible = "ti,omap5-l4-abe", "simple-bus";
3	reg = <0x40100000 0x400>,
4	      <0x40100400 0x400>;
5	reg-names = "la", "ap";
6	#address-cells = <1>;
7	#size-cells = <1>;
8	ranges = <0x00000000 0x40100000 0x100000>,	/* segment 0 */
9		 <0x49000000 0x49000000 0x100000>;
10	segment@0 {					/* 0x40100000 */
11		compatible = "simple-bus";
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges =
15			 /* CPU to L4 ABE mapping */
16			 <0x00000000 0x00000000 0x000400>,	/* ap 0 */
17			 <0x00000400 0x00000400 0x000400>,	/* ap 1 */
18			 <0x00022000 0x00022000 0x001000>,	/* ap 2 */
19			 <0x00023000 0x00023000 0x001000>,	/* ap 3 */
20			 <0x00024000 0x00024000 0x001000>,	/* ap 4 */
21			 <0x00025000 0x00025000 0x001000>,	/* ap 5 */
22			 <0x00026000 0x00026000 0x001000>,	/* ap 6 */
23			 <0x00027000 0x00027000 0x001000>,	/* ap 7 */
24			 <0x00028000 0x00028000 0x001000>,	/* ap 8 */
25			 <0x00029000 0x00029000 0x001000>,	/* ap 9 */
26			 <0x0002a000 0x0002a000 0x001000>,	/* ap 10 */
27			 <0x0002b000 0x0002b000 0x001000>,	/* ap 11 */
28			 <0x0002e000 0x0002e000 0x001000>,	/* ap 12 */
29			 <0x0002f000 0x0002f000 0x001000>,	/* ap 13 */
30			 <0x00030000 0x00030000 0x001000>,	/* ap 14 */
31			 <0x00031000 0x00031000 0x001000>,	/* ap 15 */
32			 <0x00032000 0x00032000 0x001000>,	/* ap 16 */
33			 <0x00033000 0x00033000 0x001000>,	/* ap 17 */
34			 <0x00038000 0x00038000 0x001000>,	/* ap 18 */
35			 <0x00039000 0x00039000 0x001000>,	/* ap 19 */
36			 <0x0003a000 0x0003a000 0x001000>,	/* ap 20 */
37			 <0x0003b000 0x0003b000 0x001000>,	/* ap 21 */
38			 <0x0003c000 0x0003c000 0x001000>,	/* ap 22 */
39			 <0x0003d000 0x0003d000 0x001000>,	/* ap 23 */
40			 <0x0003e000 0x0003e000 0x001000>,	/* ap 24 */
41			 <0x0003f000 0x0003f000 0x001000>,	/* ap 25 */
42			 <0x00080000 0x00080000 0x010000>,	/* ap 26 */
43			 <0x00080000 0x00080000 0x001000>,	/* ap 27 */
44			 <0x000a0000 0x000a0000 0x010000>,	/* ap 28 */
45			 <0x000a0000 0x000a0000 0x001000>,	/* ap 29 */
46			 <0x000c0000 0x000c0000 0x010000>,	/* ap 30 */
47			 <0x000c0000 0x000c0000 0x001000>,	/* ap 31 */
48			 <0x000f1000 0x000f1000 0x001000>,	/* ap 32 */
49			 <0x000f2000 0x000f2000 0x001000>,	/* ap 33 */
50
51			 /* L3 to L4 ABE mapping */
52			 <0x49000000 0x49000000 0x000400>,	/* ap 0 */
53			 <0x49000400 0x49000400 0x000400>,	/* ap 1 */
54			 <0x49022000 0x49022000 0x001000>,	/* ap 2 */
55			 <0x49023000 0x49023000 0x001000>,	/* ap 3 */
56			 <0x49024000 0x49024000 0x001000>,	/* ap 4 */
57			 <0x49025000 0x49025000 0x001000>,	/* ap 5 */
58			 <0x49026000 0x49026000 0x001000>,	/* ap 6 */
59			 <0x49027000 0x49027000 0x001000>,	/* ap 7 */
60			 <0x49028000 0x49028000 0x001000>,	/* ap 8 */
61			 <0x49029000 0x49029000 0x001000>,	/* ap 9 */
62			 <0x4902a000 0x4902a000 0x001000>,	/* ap 10 */
63			 <0x4902b000 0x4902b000 0x001000>,	/* ap 11 */
64			 <0x4902e000 0x4902e000 0x001000>,	/* ap 12 */
65			 <0x4902f000 0x4902f000 0x001000>,	/* ap 13 */
66			 <0x49030000 0x49030000 0x001000>,	/* ap 14 */
67			 <0x49031000 0x49031000 0x001000>,	/* ap 15 */
68			 <0x49032000 0x49032000 0x001000>,	/* ap 16 */
69			 <0x49033000 0x49033000 0x001000>,	/* ap 17 */
70			 <0x49038000 0x49038000 0x001000>,	/* ap 18 */
71			 <0x49039000 0x49039000 0x001000>,	/* ap 19 */
72			 <0x4903a000 0x4903a000 0x001000>,	/* ap 20 */
73			 <0x4903b000 0x4903b000 0x001000>,	/* ap 21 */
74			 <0x4903c000 0x4903c000 0x001000>,	/* ap 22 */
75			 <0x4903d000 0x4903d000 0x001000>,	/* ap 23 */
76			 <0x4903e000 0x4903e000 0x001000>,	/* ap 24 */
77			 <0x4903f000 0x4903f000 0x001000>,	/* ap 25 */
78			 <0x49080000 0x49080000 0x010000>,	/* ap 26 */
79			 <0x49080000 0x49080000 0x001000>,	/* ap 27 */
80			 <0x490a0000 0x490a0000 0x010000>,	/* ap 28 */
81			 <0x490a0000 0x490a0000 0x001000>,	/* ap 29 */
82			 <0x490c0000 0x490c0000 0x010000>,	/* ap 30 */
83			 <0x490c0000 0x490c0000 0x001000>,	/* ap 31 */
84			 <0x490f1000 0x490f1000 0x001000>,	/* ap 32 */
85			 <0x490f2000 0x490f2000 0x001000>;	/* ap 33 */
86
87		target-module@22000 {			/* 0x40122000, ap 2 02.0 */
88			compatible = "ti,sysc-omap2", "ti,sysc";
89			reg = <0x2208c 0x4>;
90			reg-names = "sysc";
91			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
92					 SYSC_OMAP2_ENAWAKEUP |
93					 SYSC_OMAP2_SOFTRESET)>;
94			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
95					<SYSC_IDLE_NO>,
96					<SYSC_IDLE_SMART>;
97			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
98			clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
99			clock-names = "fck";
100			#address-cells = <1>;
101			#size-cells = <1>;
102			ranges = <0x0 0x22000 0x1000>,
103				 <0x49022000 0x49022000 0x1000>;
104
105			mcbsp1: mcbsp@0 {
106				compatible = "ti,omap4-mcbsp";
107				reg = <0x0 0xff>, /* MPU private access */
108				      <0x49022000 0xff>; /* L3 Interconnect */
109				reg-names = "mpu", "dma";
110				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
111				interrupt-names = "common";
112				ti,buffer-size = <128>;
113				dmas = <&sdma 33>,
114				       <&sdma 34>;
115				dma-names = "tx", "rx";
116				status = "disabled";
117			};
118		};
119
120		target-module@24000 {			/* 0x40124000, ap 4 04.0 */
121			compatible = "ti,sysc-omap2", "ti,sysc";
122			reg = <0x2408c 0x4>;
123			reg-names = "sysc";
124			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
125					 SYSC_OMAP2_ENAWAKEUP |
126					 SYSC_OMAP2_SOFTRESET)>;
127			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
128					<SYSC_IDLE_NO>,
129					<SYSC_IDLE_SMART>;
130			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
131			clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
132			clock-names = "fck";
133			#address-cells = <1>;
134			#size-cells = <1>;
135			ranges = <0x0 0x24000 0x1000>,
136				 <0x49024000 0x49024000 0x1000>;
137
138			mcbsp2: mcbsp@0 {
139				compatible = "ti,omap4-mcbsp";
140				reg = <0x0 0xff>, /* MPU private access */
141				      <0x49024000 0xff>; /* L3 Interconnect */
142				reg-names = "mpu", "dma";
143				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
144				interrupt-names = "common";
145				ti,buffer-size = <128>;
146				dmas = <&sdma 17>,
147				       <&sdma 18>;
148				dma-names = "tx", "rx";
149				status = "disabled";
150			};
151		};
152
153		target-module@26000 {			/* 0x40126000, ap 6 06.0 */
154			compatible = "ti,sysc-omap2", "ti,sysc";
155			reg = <0x2608c 0x4>;
156			reg-names = "sysc";
157			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
158					 SYSC_OMAP2_ENAWAKEUP |
159					 SYSC_OMAP2_SOFTRESET)>;
160			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
161					<SYSC_IDLE_NO>,
162					<SYSC_IDLE_SMART>;
163			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
164			clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
165			clock-names = "fck";
166			#address-cells = <1>;
167			#size-cells = <1>;
168			ranges = <0x0 0x26000 0x1000>,
169				 <0x49026000 0x49026000 0x1000>;
170
171			mcbsp3: mcbsp@0 {
172				compatible = "ti,omap4-mcbsp";
173				reg = <0x0 0xff>, /* MPU private access */
174				      <0x49026000 0xff>; /* L3 Interconnect */
175				reg-names = "mpu", "dma";
176				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
177				interrupt-names = "common";
178				ti,buffer-size = <128>;
179				dmas = <&sdma 19>,
180				       <&sdma 20>;
181				dma-names = "tx", "rx";
182				status = "disabled";
183			};
184		};
185
186		target-module@28000 {			/* 0x40128000, ap 8 08.0 */
187			compatible = "ti,sysc";
188			status = "disabled";
189			#address-cells = <1>;
190			#size-cells = <1>;
191			ranges = <0x0 0x28000 0x1000>,
192				 <0x49028000 0x49028000 0x1000>;
193		};
194
195		target-module@2a000 {			/* 0x4012a000, ap 10 0a.0 */
196			compatible = "ti,sysc";
197			status = "disabled";
198			#address-cells = <1>;
199			#size-cells = <1>;
200			ranges = <0x0 0x2a000 0x1000>,
201				 <0x4902a000 0x4902a000 0x1000>;
202		};
203
204		target-module@2e000 {			/* 0x4012e000, ap 12 0c.0 */
205			compatible = "ti,sysc-omap4", "ti,sysc";
206			reg = <0x2e000 0x4>,
207			      <0x2e010 0x4>;
208			reg-names = "rev", "sysc";
209			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
210					 SYSC_OMAP4_SOFTRESET)>;
211			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
212					<SYSC_IDLE_NO>,
213					<SYSC_IDLE_SMART>,
214					<SYSC_IDLE_SMART_WKUP>;
215			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
216			clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
217			clock-names = "fck";
218			#address-cells = <1>;
219			#size-cells = <1>;
220			ranges = <0x0 0x2e000 0x1000>,
221				 <0x4902e000 0x4902e000 0x1000>;
222
223			dmic: dmic@0 {
224				compatible = "ti,omap4-dmic";
225				reg = <0x0 0x7f>, /* MPU private access */
226				      <0x4902e000 0x7f>; /* L3 Interconnect */
227				reg-names = "mpu", "dma";
228				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
229				dmas = <&sdma 67>;
230				dma-names = "up_link";
231				status = "disabled";
232			};
233		};
234
235		target-module@30000 {			/* 0x40130000, ap 14 0e.0 */
236			compatible = "ti,sysc";
237			status = "disabled";
238			#address-cells = <1>;
239			#size-cells = <1>;
240			ranges = <0x0 0x30000 0x1000>,
241				 <0x49030000 0x49030000 0x1000>;
242		};
243
244		mcpdm_module: target-module@32000 {	/* 0x40132000, ap 16 10.0 */
245			compatible = "ti,sysc-omap4", "ti,sysc";
246			reg = <0x32000 0x4>,
247			      <0x32010 0x4>;
248			reg-names = "rev", "sysc";
249			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
250					 SYSC_OMAP4_SOFTRESET)>;
251			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
252					<SYSC_IDLE_NO>,
253					<SYSC_IDLE_SMART>,
254					<SYSC_IDLE_SMART_WKUP>;
255			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
256			clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
257			clock-names = "fck";
258			#address-cells = <1>;
259			#size-cells = <1>;
260			ranges = <0x0 0x32000 0x1000>,
261				 <0x49032000 0x49032000 0x1000>;
262
263			/* Must be only enabled for boards with pdmclk wired */
264			status = "disabled";
265
266			mcpdm: mcpdm@0 {
267				compatible = "ti,omap4-mcpdm";
268				reg = <0x0 0x7f>, /* MPU private access */
269				      <0x49032000 0x7f>; /* L3 Interconnect */
270				reg-names = "mpu", "dma";
271				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
272				dmas = <&sdma 65>,
273				       <&sdma 66>;
274				dma-names = "up_link", "dn_link";
275			};
276		};
277
278		target-module@38000 {			/* 0x40138000, ap 18 12.0 */
279			compatible = "ti,sysc-omap4-timer", "ti,sysc";
280			reg = <0x38000 0x4>,
281			      <0x38010 0x4>;
282			reg-names = "rev", "sysc";
283			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
284					 SYSC_OMAP4_SOFTRESET)>;
285			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
286					<SYSC_IDLE_NO>,
287					<SYSC_IDLE_SMART>,
288					<SYSC_IDLE_SMART_WKUP>;
289			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
290			clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
291			clock-names = "fck";
292			#address-cells = <1>;
293			#size-cells = <1>;
294			ranges = <0x0 0x38000 0x1000>,
295				 <0x49038000 0x49038000 0x1000>;
296
297			timer5: timer@0 {
298				compatible = "ti,omap5430-timer";
299				reg = <0x0 0x80>,
300				      <0x49038000 0x80>;
301				clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
302				clock-names = "fck";
303				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
304				ti,timer-dsp;
305				ti,timer-pwm;
306			};
307		};
308
309		target-module@3a000 {			/* 0x4013a000, ap 20 14.0 */
310			compatible = "ti,sysc-omap4-timer", "ti,sysc";
311			reg = <0x3a000 0x4>,
312			      <0x3a010 0x4>;
313			reg-names = "rev", "sysc";
314			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
315					 SYSC_OMAP4_SOFTRESET)>;
316			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
317					<SYSC_IDLE_NO>,
318					<SYSC_IDLE_SMART>,
319					<SYSC_IDLE_SMART_WKUP>;
320			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
321			clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
322			clock-names = "fck";
323			#address-cells = <1>;
324			#size-cells = <1>;
325			ranges = <0x0 0x3a000 0x1000>,
326				 <0x4903a000 0x4903a000 0x1000>;
327
328			timer6: timer@0 {
329				compatible = "ti,omap5430-timer";
330				reg = <0x0 0x80>,
331				      <0x4903a000 0x80>;
332				clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
333				clock-names = "fck";
334				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
335				ti,timer-dsp;
336				ti,timer-pwm;
337			};
338		};
339
340		target-module@3c000 {			/* 0x4013c000, ap 22 16.0 */
341			compatible = "ti,sysc-omap4-timer", "ti,sysc";
342			reg = <0x3c000 0x4>,
343			      <0x3c010 0x4>;
344			reg-names = "rev", "sysc";
345			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
346					 SYSC_OMAP4_SOFTRESET)>;
347			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
348					<SYSC_IDLE_NO>,
349					<SYSC_IDLE_SMART>,
350					<SYSC_IDLE_SMART_WKUP>;
351			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
352			clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
353			clock-names = "fck";
354			#address-cells = <1>;
355			#size-cells = <1>;
356			ranges = <0x0 0x3c000 0x1000>,
357				 <0x4903c000 0x4903c000 0x1000>;
358
359			timer7: timer@0 {
360				compatible = "ti,omap5430-timer";
361				reg = <0x0 0x80>,
362				      <0x4903c000 0x80>;
363				clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
364				clock-names = "fck";
365				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
366				ti,timer-dsp;
367			};
368		};
369
370		target-module@3e000 {			/* 0x4013e000, ap 24 18.0 */
371			compatible = "ti,sysc-omap4-timer", "ti,sysc";
372			reg = <0x3e000 0x4>,
373			      <0x3e010 0x4>;
374			reg-names = "rev", "sysc";
375			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
376					 SYSC_OMAP4_SOFTRESET)>;
377			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
378					<SYSC_IDLE_NO>,
379					<SYSC_IDLE_SMART>,
380					<SYSC_IDLE_SMART_WKUP>;
381			/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
382			clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
383			clock-names = "fck";
384			#address-cells = <1>;
385			#size-cells = <1>;
386			ranges = <0x0 0x3e000 0x1000>,
387				 <0x4903e000 0x4903e000 0x1000>;
388
389			timer8: timer@0 {
390				compatible = "ti,omap5430-timer";
391				reg = <0x0 0x80>,
392				      <0x4903e000 0x80>;
393				clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
394				clock-names = "fck";
395				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
396				ti,timer-dsp;
397				ti,timer-pwm;
398			};
399		};
400
401		target-module@80000 {			/* 0x40180000, ap 26 1a.0 */
402			compatible = "ti,sysc";
403			status = "disabled";
404			#address-cells = <1>;
405			#size-cells = <1>;
406			ranges = <0x0 0x80000 0x10000>,
407				 <0x49080000 0x49080000 0x10000>;
408		};
409
410		target-module@a0000 {			/* 0x401a0000, ap 28 1c.0 */
411			compatible = "ti,sysc";
412			status = "disabled";
413			#address-cells = <1>;
414			#size-cells = <1>;
415			ranges = <0x0 0xa0000 0x10000>,
416				 <0x490a0000 0x490a0000 0x10000>;
417		};
418
419		target-module@c0000 {			/* 0x401c0000, ap 30 1e.0 */
420			compatible = "ti,sysc";
421			status = "disabled";
422			#address-cells = <1>;
423			#size-cells = <1>;
424			ranges = <0x0 0xc0000 0x10000>,
425				 <0x490c0000 0x490c0000 0x10000>;
426		};
427
428		target-module@f1000 {			/* 0x401f1000, ap 32 20.0 */
429			compatible = "ti,sysc-omap4", "ti,sysc";
430			reg = <0xf1000 0x4>,
431			      <0xf1010 0x4>;
432			reg-names = "rev", "sysc";
433			ti,sysc-midle = <SYSC_IDLE_FORCE>,
434					<SYSC_IDLE_NO>,
435					<SYSC_IDLE_SMART>,
436					<SYSC_IDLE_SMART_WKUP>;
437			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
438					<SYSC_IDLE_NO>,
439					<SYSC_IDLE_SMART>;
440			/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
441			clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
442			clock-names = "fck";
443			#address-cells = <1>;
444			#size-cells = <1>;
445			ranges = <0x0 0xf1000 0x1000>,
446				 <0x490f1000 0x490f1000 0x1000>;
447		};
448	};
449};
450