1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier Pro5 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8/ {
9	compatible = "socionext,uniphier-pro5";
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-a9";
20			reg = <0>;
21			clocks = <&sys_clk 32>;
22			enable-method = "psci";
23			next-level-cache = <&l2>;
24			operating-points-v2 = <&cpu_opp>;
25		};
26
27		cpu@1 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a9";
30			reg = <1>;
31			clocks = <&sys_clk 32>;
32			enable-method = "psci";
33			next-level-cache = <&l2>;
34			operating-points-v2 = <&cpu_opp>;
35		};
36	};
37
38	cpu_opp: opp-table {
39		compatible = "operating-points-v2";
40		opp-shared;
41
42		opp-100000000 {
43			opp-hz = /bits/ 64 <100000000>;
44			clock-latency-ns = <300>;
45		};
46		opp-116667000 {
47			opp-hz = /bits/ 64 <116667000>;
48			clock-latency-ns = <300>;
49		};
50		opp-150000000 {
51			opp-hz = /bits/ 64 <150000000>;
52			clock-latency-ns = <300>;
53		};
54		opp-175000000 {
55			opp-hz = /bits/ 64 <175000000>;
56			clock-latency-ns = <300>;
57		};
58		opp-200000000 {
59			opp-hz = /bits/ 64 <200000000>;
60			clock-latency-ns = <300>;
61		};
62		opp-233334000 {
63			opp-hz = /bits/ 64 <233334000>;
64			clock-latency-ns = <300>;
65		};
66		opp-300000000 {
67			opp-hz = /bits/ 64 <300000000>;
68			clock-latency-ns = <300>;
69		};
70		opp-350000000 {
71			opp-hz = /bits/ 64 <350000000>;
72			clock-latency-ns = <300>;
73		};
74		opp-400000000 {
75			opp-hz = /bits/ 64 <400000000>;
76			clock-latency-ns = <300>;
77		};
78		opp-466667000 {
79			opp-hz = /bits/ 64 <466667000>;
80			clock-latency-ns = <300>;
81		};
82		opp-600000000 {
83			opp-hz = /bits/ 64 <600000000>;
84			clock-latency-ns = <300>;
85		};
86		opp-700000000 {
87			opp-hz = /bits/ 64 <700000000>;
88			clock-latency-ns = <300>;
89		};
90		opp-800000000 {
91			opp-hz = /bits/ 64 <800000000>;
92			clock-latency-ns = <300>;
93		};
94		opp-933334000 {
95			opp-hz = /bits/ 64 <933334000>;
96			clock-latency-ns = <300>;
97		};
98		opp-1200000000 {
99			opp-hz = /bits/ 64 <1200000000>;
100			clock-latency-ns = <300>;
101		};
102		opp-1400000000 {
103			opp-hz = /bits/ 64 <1400000000>;
104			clock-latency-ns = <300>;
105		};
106	};
107
108	psci {
109		compatible = "arm,psci-0.2";
110		method = "smc";
111	};
112
113	clocks {
114		refclk: ref {
115			compatible = "fixed-clock";
116			#clock-cells = <0>;
117			clock-frequency = <20000000>;
118		};
119
120		arm_timer_clk: arm-timer {
121			#clock-cells = <0>;
122			compatible = "fixed-clock";
123			clock-frequency = <50000000>;
124		};
125	};
126
127	soc {
128		compatible = "simple-bus";
129		#address-cells = <1>;
130		#size-cells = <1>;
131		ranges;
132		interrupt-parent = <&intc>;
133
134		l2: cache-controller@500c0000 {
135			compatible = "socionext,uniphier-system-cache";
136			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137			      <0x506c0000 0x400>;
138			interrupts = <0 190 4>, <0 191 4>;
139			cache-unified;
140			cache-size = <(2 * 1024 * 1024)>;
141			cache-sets = <512>;
142			cache-line-size = <128>;
143			cache-level = <2>;
144			next-level-cache = <&l3>;
145		};
146
147		l3: cache-controller@500c8000 {
148			compatible = "socionext,uniphier-system-cache";
149			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150			      <0x506c8000 0x400>;
151			interrupts = <0 174 4>, <0 175 4>;
152			cache-unified;
153			cache-size = <(2 * 1024 * 1024)>;
154			cache-sets = <512>;
155			cache-line-size = <256>;
156			cache-level = <3>;
157		};
158
159		spi0: spi@54006000 {
160			compatible = "socionext,uniphier-scssi";
161			status = "disabled";
162			reg = <0x54006000 0x100>;
163			#address-cells = <1>;
164			#size-cells = <0>;
165			interrupts = <0 39 4>;
166			pinctrl-names = "default";
167			pinctrl-0 = <&pinctrl_spi0>;
168			clocks = <&peri_clk 11>;
169			resets = <&peri_rst 11>;
170		};
171
172		spi1: spi@54006100 {
173			compatible = "socionext,uniphier-scssi";
174			status = "disabled";
175			reg = <0x54006100 0x100>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			interrupts = <0 216 4>;
179			pinctrl-names = "default";
180			pinctrl-0 = <&pinctrl_spi1>;
181			clocks = <&peri_clk 11>;	/* common with spi0 */
182			resets = <&peri_rst 12>;
183		};
184
185		serial0: serial@54006800 {
186			compatible = "socionext,uniphier-uart";
187			status = "disabled";
188			reg = <0x54006800 0x40>;
189			interrupts = <0 33 4>;
190			pinctrl-names = "default";
191			pinctrl-0 = <&pinctrl_uart0>;
192			clocks = <&peri_clk 0>;
193			resets = <&peri_rst 0>;
194		};
195
196		serial1: serial@54006900 {
197			compatible = "socionext,uniphier-uart";
198			status = "disabled";
199			reg = <0x54006900 0x40>;
200			interrupts = <0 35 4>;
201			pinctrl-names = "default";
202			pinctrl-0 = <&pinctrl_uart1>;
203			clocks = <&peri_clk 1>;
204			resets = <&peri_rst 1>;
205		};
206
207		serial2: serial@54006a00 {
208			compatible = "socionext,uniphier-uart";
209			status = "disabled";
210			reg = <0x54006a00 0x40>;
211			interrupts = <0 37 4>;
212			pinctrl-names = "default";
213			pinctrl-0 = <&pinctrl_uart2>;
214			clocks = <&peri_clk 2>;
215			resets = <&peri_rst 2>;
216		};
217
218		serial3: serial@54006b00 {
219			compatible = "socionext,uniphier-uart";
220			status = "disabled";
221			reg = <0x54006b00 0x40>;
222			interrupts = <0 177 4>;
223			pinctrl-names = "default";
224			pinctrl-0 = <&pinctrl_uart3>;
225			clocks = <&peri_clk 3>;
226			resets = <&peri_rst 3>;
227		};
228
229		gpio: gpio@55000000 {
230			compatible = "socionext,uniphier-gpio";
231			reg = <0x55000000 0x200>;
232			interrupt-parent = <&aidet>;
233			interrupt-controller;
234			#interrupt-cells = <2>;
235			gpio-controller;
236			#gpio-cells = <2>;
237			gpio-ranges = <&pinctrl 0 0 0>;
238			gpio-ranges-group-names = "gpio_range";
239			ngpios = <248>;
240			socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
241		};
242
243		i2c0: i2c@58780000 {
244			compatible = "socionext,uniphier-fi2c";
245			status = "disabled";
246			reg = <0x58780000 0x80>;
247			#address-cells = <1>;
248			#size-cells = <0>;
249			interrupts = <0 41 4>;
250			pinctrl-names = "default";
251			pinctrl-0 = <&pinctrl_i2c0>;
252			clocks = <&peri_clk 4>;
253			resets = <&peri_rst 4>;
254			clock-frequency = <100000>;
255		};
256
257		i2c1: i2c@58781000 {
258			compatible = "socionext,uniphier-fi2c";
259			status = "disabled";
260			reg = <0x58781000 0x80>;
261			#address-cells = <1>;
262			#size-cells = <0>;
263			interrupts = <0 42 4>;
264			pinctrl-names = "default";
265			pinctrl-0 = <&pinctrl_i2c1>;
266			clocks = <&peri_clk 5>;
267			resets = <&peri_rst 5>;
268			clock-frequency = <100000>;
269		};
270
271		i2c2: i2c@58782000 {
272			compatible = "socionext,uniphier-fi2c";
273			status = "disabled";
274			reg = <0x58782000 0x80>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			interrupts = <0 43 4>;
278			pinctrl-names = "default";
279			pinctrl-0 = <&pinctrl_i2c2>;
280			clocks = <&peri_clk 6>;
281			resets = <&peri_rst 6>;
282			clock-frequency = <100000>;
283		};
284
285		i2c3: i2c@58783000 {
286			compatible = "socionext,uniphier-fi2c";
287			status = "disabled";
288			reg = <0x58783000 0x80>;
289			#address-cells = <1>;
290			#size-cells = <0>;
291			interrupts = <0 44 4>;
292			pinctrl-names = "default";
293			pinctrl-0 = <&pinctrl_i2c3>;
294			clocks = <&peri_clk 7>;
295			resets = <&peri_rst 7>;
296			clock-frequency = <100000>;
297		};
298
299		/* i2c4 does not exist */
300
301		/* chip-internal connection for DMD */
302		i2c5: i2c@58785000 {
303			compatible = "socionext,uniphier-fi2c";
304			reg = <0x58785000 0x80>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307			interrupts = <0 25 4>;
308			clocks = <&peri_clk 9>;
309			resets = <&peri_rst 9>;
310			clock-frequency = <400000>;
311		};
312
313		/* chip-internal connection for HDMI */
314		i2c6: i2c@58786000 {
315			compatible = "socionext,uniphier-fi2c";
316			reg = <0x58786000 0x80>;
317			#address-cells = <1>;
318			#size-cells = <0>;
319			interrupts = <0 26 4>;
320			clocks = <&peri_clk 10>;
321			resets = <&peri_rst 10>;
322			clock-frequency = <400000>;
323		};
324
325		system_bus: system-bus@58c00000 {
326			compatible = "socionext,uniphier-system-bus";
327			status = "disabled";
328			reg = <0x58c00000 0x400>;
329			#address-cells = <2>;
330			#size-cells = <1>;
331			pinctrl-names = "default";
332			pinctrl-0 = <&pinctrl_system_bus>;
333		};
334
335		smpctrl@59801000 {
336			compatible = "socionext,uniphier-smpctrl";
337			reg = <0x59801000 0x400>;
338		};
339
340		sdctrl@59810000 {
341			compatible = "socionext,uniphier-pro5-sdctrl",
342				     "simple-mfd", "syscon";
343			reg = <0x59810000 0x400>;
344
345			sd_clk: clock {
346				compatible = "socionext,uniphier-pro5-sd-clock";
347				#clock-cells = <1>;
348			};
349
350			sd_rst: reset {
351				compatible = "socionext,uniphier-pro5-sd-reset";
352				#reset-cells = <1>;
353			};
354		};
355
356		perictrl@59820000 {
357			compatible = "socionext,uniphier-pro5-perictrl",
358				     "simple-mfd", "syscon";
359			reg = <0x59820000 0x200>;
360
361			peri_clk: clock {
362				compatible = "socionext,uniphier-pro5-peri-clock";
363				#clock-cells = <1>;
364			};
365
366			peri_rst: reset {
367				compatible = "socionext,uniphier-pro5-peri-reset";
368				#reset-cells = <1>;
369			};
370		};
371
372		soc-glue@5f800000 {
373			compatible = "socionext,uniphier-pro5-soc-glue",
374				     "simple-mfd", "syscon";
375			reg = <0x5f800000 0x2000>;
376
377			pinctrl: pinctrl {
378				compatible = "socionext,uniphier-pro5-pinctrl";
379			};
380		};
381
382		soc-glue@5f900000 {
383			compatible = "socionext,uniphier-pro5-soc-glue-debug",
384				     "simple-mfd";
385			#address-cells = <1>;
386			#size-cells = <1>;
387			ranges = <0 0x5f900000 0x2000>;
388
389			efuse@100 {
390				compatible = "socionext,uniphier-efuse";
391				reg = <0x100 0x28>;
392			};
393
394			efuse@130 {
395				compatible = "socionext,uniphier-efuse";
396				reg = <0x130 0x8>;
397			};
398
399			efuse@200 {
400				compatible = "socionext,uniphier-efuse";
401				reg = <0x200 0x28>;
402			};
403
404			efuse@300 {
405				compatible = "socionext,uniphier-efuse";
406				reg = <0x300 0x14>;
407			};
408
409			efuse@400 {
410				compatible = "socionext,uniphier-efuse";
411				reg = <0x400 0x8>;
412			};
413		};
414
415		xdmac: dma-controller@5fc10000 {
416			compatible = "socionext,uniphier-xdmac";
417			reg = <0x5fc10000 0x5300>;
418			interrupts = <0 188 4>;
419			dma-channels = <16>;
420			#dma-cells = <2>;
421		};
422
423		aidet: interrupt-controller@5fc20000 {
424			compatible = "socionext,uniphier-pro5-aidet";
425			reg = <0x5fc20000 0x200>;
426			interrupt-controller;
427			#interrupt-cells = <2>;
428		};
429
430		timer@60000200 {
431			compatible = "arm,cortex-a9-global-timer";
432			reg = <0x60000200 0x20>;
433			interrupts = <1 11 0x304>;
434			clocks = <&arm_timer_clk>;
435		};
436
437		timer@60000600 {
438			compatible = "arm,cortex-a9-twd-timer";
439			reg = <0x60000600 0x20>;
440			interrupts = <1 13 0x304>;
441			clocks = <&arm_timer_clk>;
442		};
443
444		intc: interrupt-controller@60001000 {
445			compatible = "arm,cortex-a9-gic";
446			reg = <0x60001000 0x1000>,
447			      <0x60000100 0x100>;
448			#interrupt-cells = <3>;
449			interrupt-controller;
450		};
451
452		sysctrl@61840000 {
453			compatible = "socionext,uniphier-pro5-sysctrl",
454				     "simple-mfd", "syscon";
455			reg = <0x61840000 0x10000>;
456
457			sys_clk: clock {
458				compatible = "socionext,uniphier-pro5-clock";
459				#clock-cells = <1>;
460			};
461
462			sys_rst: reset {
463				compatible = "socionext,uniphier-pro5-reset";
464				#reset-cells = <1>;
465			};
466		};
467
468		usb0: usb@65a00000 {
469			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
470			status = "disabled";
471			reg = <0x65a00000 0xcd00>;
472			interrupt-names = "host";
473			interrupts = <0 134 4>;
474			pinctrl-names = "default";
475			pinctrl-0 = <&pinctrl_usb0>;
476			clock-names = "ref", "bus_early", "suspend";
477			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
478			resets = <&usb0_rst 15>;
479			phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
480			dr_mode = "host";
481		};
482
483		usb-glue@65b00000 {
484			compatible = "socionext,uniphier-pro5-dwc3-glue",
485				     "simple-mfd";
486			#address-cells = <1>;
487			#size-cells = <1>;
488			ranges = <0 0x65b00000 0x400>;
489
490			usb0_rst: reset@0 {
491				compatible = "socionext,uniphier-pro5-usb3-reset";
492				reg = <0x0 0x4>;
493				#reset-cells = <1>;
494				clock-names = "gio", "link";
495				clocks = <&sys_clk 12>, <&sys_clk 14>;
496				reset-names = "gio", "link";
497				resets = <&sys_rst 12>, <&sys_rst 14>;
498			};
499
500			usb0_vbus0: regulator@100 {
501				compatible = "socionext,uniphier-pro5-usb3-regulator";
502				reg = <0x100 0x10>;
503				clock-names = "gio", "link";
504				clocks = <&sys_clk 12>, <&sys_clk 14>;
505				reset-names = "gio", "link";
506				resets = <&sys_rst 12>, <&sys_rst 14>;
507			};
508
509			usb0_hsphy0: hs-phy@280 {
510				compatible = "socionext,uniphier-pro5-usb3-hsphy";
511				reg = <0x280 0x10>;
512				#phy-cells = <0>;
513				clock-names = "gio", "link";
514				clocks = <&sys_clk 12>, <&sys_clk 14>;
515				reset-names = "gio", "link";
516				resets = <&sys_rst 12>, <&sys_rst 14>;
517				vbus-supply = <&usb0_vbus0>;
518			};
519
520			usb0_ssphy0: ss-phy@380 {
521				compatible = "socionext,uniphier-pro5-usb3-ssphy";
522				reg = <0x380 0x10>;
523				#phy-cells = <0>;
524				clock-names = "gio", "link";
525				clocks = <&sys_clk 12>, <&sys_clk 14>;
526				reset-names = "gio", "link";
527				resets = <&sys_rst 12>, <&sys_rst 14>;
528				vbus-supply = <&usb0_vbus0>;
529			};
530		};
531
532		usb1: usb@65c00000 {
533			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
534			status = "disabled";
535			reg = <0x65c00000 0xcd00>;
536			interrupt-names = "host";
537			interrupts = <0 137 4>;
538			pinctrl-names = "default";
539			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
540			clock-names = "ref", "bus_early", "suspend";
541			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
542			resets = <&usb1_rst 15>;
543			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
544			dr_mode = "host";
545		};
546
547		usb-glue@65d00000 {
548			compatible = "socionext,uniphier-pro5-dwc3-glue",
549				     "simple-mfd";
550			#address-cells = <1>;
551			#size-cells = <1>;
552			ranges = <0 0x65d00000 0x400>;
553
554			usb1_rst: reset@0 {
555				compatible = "socionext,uniphier-pro5-usb3-reset";
556				reg = <0x0 0x4>;
557				#reset-cells = <1>;
558				clock-names = "gio", "link";
559				clocks = <&sys_clk 12>, <&sys_clk 15>;
560				reset-names = "gio", "link";
561				resets = <&sys_rst 12>, <&sys_rst 15>;
562			};
563
564			usb1_vbus0: regulator@100 {
565				compatible = "socionext,uniphier-pro5-usb3-regulator";
566				reg = <0x100 0x10>;
567				clock-names = "gio", "link";
568				clocks = <&sys_clk 12>, <&sys_clk 15>;
569				reset-names = "gio", "link";
570				resets = <&sys_rst 12>, <&sys_rst 15>;
571			};
572
573			usb1_vbus1: regulator@110 {
574				compatible = "socionext,uniphier-pro5-usb3-regulator";
575				reg = <0x110 0x10>;
576				clock-names = "gio", "link";
577				clocks = <&sys_clk 12>, <&sys_clk 15>;
578				reset-names = "gio", "link";
579				resets = <&sys_rst 12>, <&sys_rst 15>;
580			};
581
582			usb1_hsphy0: hs-phy@280 {
583				compatible = "socionext,uniphier-pro5-usb3-hsphy";
584				reg = <0x280 0x10>;
585				#phy-cells = <0>;
586				clock-names = "gio", "link";
587				clocks = <&sys_clk 12>, <&sys_clk 15>;
588				reset-names = "gio", "link";
589				resets = <&sys_rst 12>, <&sys_rst 15>;
590				vbus-supply = <&usb1_vbus0>;
591			};
592
593			usb1_hsphy1: hs-phy@290 {
594				compatible = "socionext,uniphier-pro5-usb3-hsphy";
595				reg = <0x290 0x10>;
596				#phy-cells = <0>;
597				clock-names = "gio", "link";
598				clocks = <&sys_clk 12>, <&sys_clk 15>;
599				reset-names = "gio", "link";
600				resets = <&sys_rst 12>, <&sys_rst 15>;
601				vbus-supply = <&usb1_vbus1>;
602			};
603
604			usb1_ssphy0: ss-phy@380 {
605				compatible = "socionext,uniphier-pro5-usb3-ssphy";
606				reg = <0x380 0x10>;
607				#phy-cells = <0>;
608				clock-names = "gio", "link";
609				clocks = <&sys_clk 12>, <&sys_clk 15>;
610				reset-names = "gio", "link";
611				resets = <&sys_rst 12>, <&sys_rst 15>;
612				vbus-supply = <&usb1_vbus0>;
613			};
614		};
615
616		pcie_ep: pcie-ep@66000000 {
617			compatible = "socionext,uniphier-pro5-pcie-ep",
618				     "snps,dw-pcie-ep";
619			status = "disabled";
620			reg-names = "dbi", "dbi2", "link", "addr_space";
621			reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
622			      <0x66010000 0x10000>, <0x67000000 0x400000>;
623			pinctrl-names = "default";
624			pinctrl-0 = <&pinctrl_pcie>;
625			clock-names = "gio", "link";
626			clocks = <&sys_clk 12>, <&sys_clk 24>;
627			reset-names = "gio", "link";
628			resets = <&sys_rst 12>, <&sys_rst 24>;
629			num-ib-windows = <16>;
630			num-ob-windows = <16>;
631			num-lanes = <4>;
632			phy-names = "pcie-phy";
633			phys = <&pcie_phy>;
634		};
635
636		pcie_phy: phy@66038000 {
637			compatible = "socionext,uniphier-pro5-pcie-phy";
638			reg = <0x66038000 0x4000>;
639			#phy-cells = <0>;
640			clock-names = "gio", "link";
641			clocks = <&sys_clk 12>, <&sys_clk 24>;
642			reset-names = "gio", "link";
643			resets = <&sys_rst 12>, <&sys_rst 24>;
644		};
645
646		nand: nand-controller@68000000 {
647			compatible = "socionext,uniphier-denali-nand-v5b";
648			status = "disabled";
649			reg-names = "nand_data", "denali_reg";
650			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
651			interrupts = <0 65 4>;
652			pinctrl-names = "default";
653			pinctrl-0 = <&pinctrl_nand2cs>;
654			clock-names = "nand", "nand_x", "ecc";
655			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
656			reset-names = "nand", "reg";
657			resets = <&sys_rst 2>, <&sys_rst 2>;
658		};
659
660		emmc: mmc@68400000 {
661			compatible = "socionext,uniphier-sd-v3.1";
662			status = "disabled";
663			reg = <0x68400000 0x800>;
664			interrupts = <0 78 4>;
665			pinctrl-names = "default";
666			pinctrl-0 = <&pinctrl_emmc>;
667			clocks = <&sd_clk 1>;
668			reset-names = "host", "hw";
669			resets = <&sd_rst 1>, <&sd_rst 6>;
670			bus-width = <8>;
671			cap-mmc-highspeed;
672			cap-mmc-hw-reset;
673			non-removable;
674		};
675
676		sd: mmc@68800000 {
677			compatible = "socionext,uniphier-sd-v3.1";
678			status = "disabled";
679			reg = <0x68800000 0x800>;
680			interrupts = <0 76 4>;
681			pinctrl-names = "default", "uhs";
682			pinctrl-0 = <&pinctrl_sd>;
683			pinctrl-1 = <&pinctrl_sd_uhs>;
684			clocks = <&sd_clk 0>;
685			reset-names = "host";
686			resets = <&sd_rst 0>;
687			bus-width = <4>;
688			cap-sd-highspeed;
689			sd-uhs-sdr12;
690			sd-uhs-sdr25;
691			sd-uhs-sdr50;
692		};
693	};
694};
695
696#include "uniphier-pinctrl.dtsi"
697