1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU208 4 * 5 * (C) Copyright 2017 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU208 RevA"; 21 compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 gpio0 = &gpio; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &dcc; 32 spi0 = &qspi; 33 usb0 = &usb0; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 xlnx,eeprom = &eeprom; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 autorepeat; 50 sw19 { 51 label = "sw19"; 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_DOWN>; 54 wakeup-source; 55 autorepeat; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 heartbeat_led { 62 label = "heartbeat"; 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 ina226-vccint { 69 compatible = "iio-hwmon"; 70 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; 71 }; 72 ina226-vccint-io-bram-ps { 73 compatible = "iio-hwmon"; 74 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; 75 }; 76 ina226-vcc1v8 { 77 compatible = "iio-hwmon"; 78 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; 79 }; 80 ina226-vcc1v2 { 81 compatible = "iio-hwmon"; 82 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; 83 }; 84 ina226-vadj-fmc { 85 compatible = "iio-hwmon"; 86 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; 87 }; 88 ina226-mgtavcc { 89 compatible = "iio-hwmon"; 90 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; 91 }; 92 ina226-mgt1v2 { 93 compatible = "iio-hwmon"; 94 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; 95 }; 96 ina226-mgt1v8 { 97 compatible = "iio-hwmon"; 98 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; 99 }; 100 ina226-vccint-ams { 101 compatible = "iio-hwmon"; 102 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; 103 }; 104 ina226-dac-avtt { 105 compatible = "iio-hwmon"; 106 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; 107 }; 108 ina226-dac-avccaux { 109 compatible = "iio-hwmon"; 110 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; 111 }; 112 ina226-adc-avcc { 113 compatible = "iio-hwmon"; 114 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; 115 }; 116 ina226-adc-avccaux { 117 compatible = "iio-hwmon"; 118 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; 119 }; 120 ina226-dac-avcc { 121 compatible = "iio-hwmon"; 122 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; 123 }; 124 125 /* 48MHz reference crystal */ 126 ref48: ref48M { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <48000000>; 130 }; 131}; 132 133&dcc { 134 status = "okay"; 135}; 136 137&fpd_dma_chan1 { 138 status = "okay"; 139}; 140 141&fpd_dma_chan2 { 142 status = "okay"; 143}; 144 145&fpd_dma_chan3 { 146 status = "okay"; 147}; 148 149&fpd_dma_chan4 { 150 status = "okay"; 151}; 152 153&fpd_dma_chan5 { 154 status = "okay"; 155}; 156 157&fpd_dma_chan6 { 158 status = "okay"; 159}; 160 161&fpd_dma_chan7 { 162 status = "okay"; 163}; 164 165&fpd_dma_chan8 { 166 status = "okay"; 167}; 168 169&gem3 { 170 status = "okay"; 171 phy-handle = <&phy0>; 172 phy-mode = "rgmii-id"; 173 phy0: ethernet-phy@c { 174 reg = <0xc>; 175 ti,rx-internal-delay = <0x8>; 176 ti,tx-internal-delay = <0xa>; 177 ti,fifo-depth = <0x1>; 178 ti,dp83867-rxctrl-strap-quirk; 179 }; 180}; 181 182&gpio { 183 status = "okay"; 184 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ 185 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ 186 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ 187 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ 188 "", "", "BUTTON", "LED", "", /* 20 - 24 */ 189 "", "PMU_INPUT", "", "", "", /* 25 - 29 */ 190 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ 191 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ 192 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ 193 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ 194 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ 195 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ 196 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ 197 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ 198 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ 199 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ 200 "", "", /* 78 - 79 */ 201 "", "", "", "", "", /* 80 - 84 */ 202 "", "", "", "", "", /* 85 -89 */ 203 "", "", "", "", "", /* 90 - 94 */ 204 "", "", "", "", "", /* 95 - 99 */ 205 "", "", "", "", "", /* 100 - 104 */ 206 "", "", "", "", "", /* 105 - 109 */ 207 "", "", "", "", "", /* 110 - 114 */ 208 "", "", "", "", "", /* 115 - 119 */ 209 "", "", "", "", "", /* 120 - 124 */ 210 "", "", "", "", "", /* 125 - 129 */ 211 "", "", "", "", "", /* 130 - 134 */ 212 "", "", "", "", "", /* 135 - 139 */ 213 "", "", "", "", "", /* 140 - 144 */ 214 "", "", "", "", "", /* 145 - 149 */ 215 "", "", "", "", "", /* 150 - 154 */ 216 "", "", "", "", "", /* 155 - 159 */ 217 "", "", "", "", "", /* 160 - 164 */ 218 "", "", "", "", "", /* 165 - 169 */ 219 "", "", "", ""; /* 170 - 174 */ 220}; 221 222&i2c0 { 223 status = "okay"; 224 clock-frequency = <400000>; 225 pinctrl-names = "default", "gpio"; 226 pinctrl-0 = <&pinctrl_i2c0_default>; 227 pinctrl-1 = <&pinctrl_i2c0_gpio>; 228 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 229 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 230 231 tca6416_u15: gpio@20 { /* u15 */ 232 compatible = "ti,tca6416"; 233 reg = <0x20>; 234 gpio-controller; /* interrupt not connected */ 235 #gpio-cells = <2>; 236 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ 237 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ 238 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ 239 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ 240 }; 241 242 i2c-mux@75 { /* u17 */ 243 compatible = "nxp,pca9544"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 reg = <0x75>; 247 i2c@0 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 reg = <0>; 251 /* PS_PMBUS */ 252 /* PMBUS_ALERT done via pca9544 */ 253 vccint: ina226@40 { /* u65 */ 254 compatible = "ti,ina226"; 255 #io-channel-cells = <1>; 256 label = "ina226-vccint"; 257 reg = <0x40>; 258 shunt-resistor = <5000>; 259 }; 260 vccint_io_bram_ps: ina226@41 { /* u57 */ 261 compatible = "ti,ina226"; 262 #io-channel-cells = <1>; 263 label = "ina226-vccint-io-bram-ps"; 264 reg = <0x41>; 265 shunt-resistor = <5000>; 266 }; 267 vcc1v8: ina226@42 { /* u60 */ 268 compatible = "ti,ina226"; 269 #io-channel-cells = <1>; 270 label = "ina226-vcc1v8"; 271 reg = <0x42>; 272 shunt-resistor = <2000>; 273 }; 274 vcc1v2: ina226@43 { /* u58 */ 275 compatible = "ti,ina226"; 276 #io-channel-cells = <1>; 277 label = "ina226-vcc1v2"; 278 reg = <0x43>; 279 shunt-resistor = <5000>; 280 }; 281 vadj_fmc: ina226@45 { /* u62 */ 282 compatible = "ti,ina226"; 283 #io-channel-cells = <1>; 284 label = "ina226-vadj-fmc"; 285 reg = <0x45>; 286 shunt-resistor = <5000>; 287 }; 288 mgtavcc: ina226@46 { /* u67 */ 289 compatible = "ti,ina226"; 290 #io-channel-cells = <1>; 291 label = "ina226-mgtavcc"; 292 reg = <0x46>; 293 shunt-resistor = <2000>; 294 }; 295 mgt1v2: ina226@47 { /* u63 */ 296 compatible = "ti,ina226"; 297 #io-channel-cells = <1>; 298 label = "ina226-mgt1v2"; 299 reg = <0x47>; 300 shunt-resistor = <5000>; 301 }; 302 mgt1v8: ina226@48 { /* u64 */ 303 compatible = "ti,ina226"; 304 #io-channel-cells = <1>; 305 label = "ina226-mgt1v8"; 306 reg = <0x48>; 307 shunt-resistor = <5000>; 308 }; 309 vccint_ams: ina226@49 { /* u61 */ 310 compatible = "ti,ina226"; 311 #io-channel-cells = <1>; 312 label = "ina226-vccint-ams"; 313 reg = <0x49>; 314 shunt-resistor = <5000>; 315 }; 316 dac_avtt: ina226@4a { /* u59 */ 317 compatible = "ti,ina226"; 318 #io-channel-cells = <1>; 319 label = "ina226-dac-avtt"; 320 reg = <0x4a>; 321 shunt-resistor = <5000>; 322 }; 323 dac_avccaux: ina226@4b { /* u124 */ 324 compatible = "ti,ina226"; 325 #io-channel-cells = <1>; 326 label = "ina226-dac-avccaux"; 327 reg = <0x4b>; 328 shunt-resistor = <5000>; 329 }; 330 adc_avcc: ina226@4c { /* u75 */ 331 compatible = "ti,ina226"; 332 #io-channel-cells = <1>; 333 label = "ina226-adc-avcc"; 334 reg = <0x4c>; 335 shunt-resistor = <5000>; 336 }; 337 adc_avccaux: ina226@4d { /* u71 */ 338 compatible = "ti,ina226"; 339 #io-channel-cells = <1>; 340 label = "ina226-adc-avccaux"; 341 reg = <0x4d>; 342 shunt-resistor = <5000>; 343 }; 344 dac_avcc: ina226@4e { /* u77 */ 345 compatible = "ti,ina226"; 346 #io-channel-cells = <1>; 347 label = "ina226-dac-avcc"; 348 reg = <0x4e>; 349 shunt-resistor = <5000>; 350 }; 351 }; 352 i2c@1 { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 reg = <1>; 356 /* NC */ 357 }; 358 i2c@2 { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <2>; 362 /* u104 - ir35215 0x10/0x40 */ 363 /* u127 - ir38164 0x1b/0x4b */ 364 /* u112 - ir38164 0x13/0x43 */ 365 /* u123 - ir38164 0x1c/0x4c */ 366 367 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ 368 compatible = "infineon,irps5401"; 369 reg = <0x44>; /* i2c addr 0x14 */ 370 }; 371 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ 372 compatible = "infineon,irps5401"; 373 reg = <0x45>; /* i2c addr 0x15 */ 374 }; 375 /* J21 header too */ 376 377 }; 378 i2c@3 { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 reg = <3>; 382 /* SYSMON */ 383 }; 384 }; 385 /* u38 MPS430 */ 386}; 387 388&i2c1 { 389 status = "okay"; 390 clock-frequency = <400000>; 391 pinctrl-names = "default", "gpio"; 392 pinctrl-0 = <&pinctrl_i2c1_default>; 393 pinctrl-1 = <&pinctrl_i2c1_gpio>; 394 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 395 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 396 397 i2c-mux@74 { 398 compatible = "nxp,pca9548"; /* u20 */ 399 #address-cells = <1>; 400 #size-cells = <0>; 401 reg = <0x74>; 402 i2c-mux-idle-disconnect; 403 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ 404 i2c_eeprom: i2c@0 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 reg = <0>; 408 /* 409 * IIC_EEPROM 1kB memory which uses 256B blocks 410 * where every block has different address. 411 * 0 - 256B address 0x54 412 * 256B - 512B address 0x55 413 * 512B - 768B address 0x56 414 * 768B - 1024B address 0x57 415 */ 416 eeprom: eeprom@54 { /* u21 */ 417 compatible = "atmel,24c128"; 418 reg = <0x54>; 419 }; 420 }; 421 i2c_si5341: i2c@1 { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <1>; 425 si5341: clock-generator@36 { /* SI5341 - u43 */ 426 compatible = "silabs,si5341"; 427 reg = <0x36>; 428 #clock-cells = <2>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&ref48>; 432 clock-names = "xtal"; 433 clock-output-names = "si5341"; 434 435 si5341_2: out@2 { 436 /* refclk2 for PS-GT, used for USB3 */ 437 reg = <2>; 438 always-on; 439 }; 440 si5341_3: out@3 { 441 /* refclk3 for PS-GT, used for SATA */ 442 reg = <3>; 443 always-on; 444 }; 445 si5341_5: out@5 { 446 /* refclk5 PL CLK100 */ 447 reg = <5>; 448 always-on; 449 }; 450 si5341_6: out@6 { 451 /* refclk6 PL CLK125 */ 452 reg = <6>; 453 always-on; 454 }; 455 si5341_9: out@9 { 456 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 457 reg = <9>; 458 always-on; 459 }; 460 }; 461 }; 462 i2c_si570_user_c0: i2c@2 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 reg = <2>; 466 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ 467 #clock-cells = <0>; 468 compatible = "silabs,si570"; 469 reg = <0x5d>; 470 temperature-stability = <50>; 471 factory-fout = <300000000>; 472 clock-frequency = <300000000>; 473 clock-output-names = "si570_user_c0"; 474 }; 475 }; 476 i2c_si570_mgt: i2c@3 { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 reg = <3>; 480 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ 481 #clock-cells = <0>; 482 compatible = "silabs,si570"; 483 reg = <0x5d>; 484 temperature-stability = <50>; 485 factory-fout = <156250000>; 486 clock-frequency = <148500000>; 487 clock-output-names = "si570_mgt"; 488 }; 489 }; 490 i2c_8a34001: i2c@4 { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <4>; 494 idt_8a34001: phc@5b { 495 compatible = "idt,8a34001"; /* u409B */ 496 reg = <0x5b>; 497 }; 498 }; 499 i2c_clk104: i2c@5 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <5>; 503 /* CLK104_SDA */ 504 }; 505 i2c@6 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <6>; 509 /* RFMCP connector */ 510 }; 511 /* 7 NC */ 512 }; 513 514 i2c-mux@75 { 515 compatible = "nxp,pca9548"; /* u22 */ 516 #address-cells = <1>; 517 #size-cells = <0>; 518 reg = <0x75>; 519 i2c-mux-idle-disconnect; 520 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ 521 i2c@0 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0>; 525 /* FMCP_HSPC_IIC */ 526 }; 527 i2c_si570_user_c1: i2c@1 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 reg = <1>; 531 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ 532 #clock-cells = <0>; 533 compatible = "silabs,si570"; 534 reg = <0x5d>; 535 temperature-stability = <50>; 536 factory-fout = <300000000>; 537 clock-frequency = <300000000>; 538 clock-output-names = "si570_user_c1"; 539 }; 540 }; 541 i2c@2 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <2>; 545 /* SYSMON */ 546 }; 547 i2c@3 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <3>; 551 /* DDR4 SODIMM */ 552 }; 553 i2c@4 { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 reg = <4>; 557 /* SFP3 */ 558 }; 559 i2c@5 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <5>; 563 /* SFP2 */ 564 }; 565 i2c@6 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 reg = <6>; 569 /* SFP1 */ 570 }; 571 i2c@7 { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 reg = <7>; 575 /* SFP0 */ 576 }; 577 }; 578 /* MSP430 */ 579}; 580 581&pinctrl0 { 582 status = "okay"; 583 pinctrl_i2c0_default: i2c0-default { 584 mux { 585 groups = "i2c0_3_grp"; 586 function = "i2c0"; 587 }; 588 589 conf { 590 groups = "i2c0_3_grp"; 591 bias-pull-up; 592 slew-rate = <SLEW_RATE_SLOW>; 593 power-source = <IO_STANDARD_LVCMOS18>; 594 }; 595 }; 596 597 pinctrl_i2c0_gpio: i2c0-gpio { 598 mux { 599 groups = "gpio0_14_grp", "gpio0_15_grp"; 600 function = "gpio0"; 601 }; 602 603 conf { 604 groups = "gpio0_14_grp", "gpio0_15_grp"; 605 slew-rate = <SLEW_RATE_SLOW>; 606 power-source = <IO_STANDARD_LVCMOS18>; 607 }; 608 }; 609 610 pinctrl_i2c1_default: i2c1-default { 611 mux { 612 groups = "i2c1_4_grp"; 613 function = "i2c1"; 614 }; 615 616 conf { 617 groups = "i2c1_4_grp"; 618 bias-pull-up; 619 slew-rate = <SLEW_RATE_SLOW>; 620 power-source = <IO_STANDARD_LVCMOS18>; 621 }; 622 }; 623 624 pinctrl_i2c1_gpio: i2c1-gpio { 625 mux { 626 groups = "gpio0_16_grp", "gpio0_17_grp"; 627 function = "gpio0"; 628 }; 629 630 conf { 631 groups = "gpio0_16_grp", "gpio0_17_grp"; 632 slew-rate = <SLEW_RATE_SLOW>; 633 power-source = <IO_STANDARD_LVCMOS18>; 634 }; 635 }; 636}; 637 638&qspi { 639 status = "okay"; 640 is-dual = <1>; 641 flash@0 { 642 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ 643 #address-cells = <1>; 644 #size-cells = <1>; 645 reg = <0>; 646 spi-tx-bus-width = <1>; 647 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 648 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 649 }; 650}; 651 652&psgtr { 653 status = "okay"; 654 /* pcie, sata, usb3, dp */ 655 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 656 clock-names = "ref0", "ref1", "ref2", "ref3"; 657}; 658 659&rtc { 660 status = "okay"; 661}; 662 663&sata { 664 status = "okay"; 665 /* SATA OOB timing settings */ 666 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 667 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 668 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 669 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 670 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 671 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 672 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 673 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 674 phy-names = "sata-phy"; 675 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 676}; 677 678/* SD1 with level shifter */ 679&sdhci1 { 680 status = "okay"; 681 disable-wp; 682 /* 683 * This property should be removed for supporting UHS mode 684 */ 685 no-1-8-v; 686 xlnx,mio-bank = <1>; 687}; 688 689&uart0 { 690 status = "okay"; 691}; 692 693/* ULPI SMSC USB3320 */ 694&usb0 { 695 status = "okay"; 696}; 697 698&dwc3_0 { 699 status = "okay"; 700 dr_mode = "host"; 701 snps,usb3_lpm_capable; 702 phy-names = "usb3-phy"; 703 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 704}; 705