1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
4 *
5 * Copyright (C) 2011 Andreas Bießmann
6 * Copyright (C) 2005 David Brownell
7 * Copyright (C) 2005 Ivan Kokshaysky
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
9 */
10 #include <common.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/at91_pmc.h>
15 #include <asm/arch/clk.h>
16
17 #if !defined(CONFIG_AT91FAMILY)
18 # error You need to define CONFIG_AT91FAMILY in your board config!
19 #endif
20
21 #define EN_PLLB_TIMEOUT 500
22
23 DECLARE_GLOBAL_DATA_PTR;
24
at91_css_to_rate(unsigned long css)25 static unsigned long at91_css_to_rate(unsigned long css)
26 {
27 switch (css) {
28 case AT91_PMC_MCKR_CSS_SLOW:
29 return CONFIG_SYS_AT91_SLOW_CLOCK;
30 case AT91_PMC_MCKR_CSS_MAIN:
31 return gd->arch.main_clk_rate_hz;
32 case AT91_PMC_MCKR_CSS_PLLA:
33 return gd->arch.plla_rate_hz;
34 case AT91_PMC_MCKR_CSS_PLLB:
35 return gd->arch.pllb_rate_hz;
36 }
37
38 return 0;
39 }
40
41 #ifdef CONFIG_USB_ATMEL
at91_pll_calc(unsigned main_freq,unsigned out_freq)42 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
43 {
44 unsigned i, div = 0, mul = 0, diff = 1 << 30;
45 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
46
47 /* PLL output max 240 MHz (or 180 MHz per errata) */
48 if (out_freq > 240000000)
49 goto fail;
50
51 for (i = 1; i < 256; i++) {
52 int diff1;
53 unsigned input, mul1;
54
55 /*
56 * PLL input between 1MHz and 32MHz per spec, but lower
57 * frequences seem necessary in some cases so allow 100K.
58 * Warning: some newer products need 2MHz min.
59 */
60 input = main_freq / i;
61 if (input < 100000)
62 continue;
63 if (input > 32000000)
64 continue;
65
66 mul1 = out_freq / input;
67 if (mul1 > 2048)
68 continue;
69 if (mul1 < 2)
70 goto fail;
71
72 diff1 = out_freq - input * mul1;
73 if (diff1 < 0)
74 diff1 = -diff1;
75 if (diff > diff1) {
76 diff = diff1;
77 div = i;
78 mul = mul1;
79 if (diff == 0)
80 break;
81 }
82 }
83 if (i == 256 && diff > (out_freq >> 5))
84 goto fail;
85 return ret | ((mul - 1) << 16) | div;
86 fail:
87 return 0;
88 }
89 #endif
90
at91_pll_rate(u32 freq,u32 reg)91 static u32 at91_pll_rate(u32 freq, u32 reg)
92 {
93 unsigned mul, div;
94
95 div = reg & 0xff;
96 mul = (reg >> 16) & 0x7ff;
97 if (div && mul) {
98 freq /= div;
99 freq *= mul + 1;
100 } else
101 freq = 0;
102
103 return freq;
104 }
105
at91_clock_init(unsigned long main_clock)106 int at91_clock_init(unsigned long main_clock)
107 {
108 unsigned freq, mckr;
109 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
110 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
111 unsigned tmp;
112 /*
113 * When the bootloader initialized the main oscillator correctly,
114 * there's no problem using the cycle counter. But if it didn't,
115 * or when using oscillator bypass mode, we must be told the speed
116 * of the main clock.
117 */
118 if (!main_clock) {
119 do {
120 tmp = readl(&pmc->mcfr);
121 } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
122 tmp &= AT91_PMC_MCFR_MAINF_MASK;
123 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
124 }
125 #endif
126 gd->arch.main_clk_rate_hz = main_clock;
127
128 /* report if PLLA is more than mildly overclocked */
129 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
130
131 #ifdef CONFIG_USB_ATMEL
132 /*
133 * USB clock init: choose 48 MHz PLLB value,
134 * disable 48MHz clock during usb peripheral suspend.
135 *
136 * REVISIT: assumes MCK doesn't derive from PLLB!
137 */
138 gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
139 AT91_PMC_PLLBR_USBDIV_2;
140 gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
141 gd->arch.at91_pllb_usb_init);
142 #endif
143
144 /*
145 * MCK and CPU derive from one of those primary clocks.
146 * For now, assume this parentage won't change.
147 */
148 mckr = readl(&pmc->mckr);
149 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
150 freq = gd->arch.mck_rate_hz;
151
152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
153 /* mdiv */
154 gd->arch.mck_rate_hz = freq /
155 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
156 gd->arch.cpu_clk_rate_hz = freq;
157
158 return 0;
159 }
160
at91_pllb_clk_enable(u32 pllbr)161 int at91_pllb_clk_enable(u32 pllbr)
162 {
163 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
164 ulong start_time, tmp_time;
165
166 start_time = get_timer(0);
167 writel(pllbr, &pmc->pllbr);
168 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
169 tmp_time = get_timer(0);
170 if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
171 printf("ERROR: failed to enable PLLB\n");
172 return -1;
173 }
174 }
175
176 return 0;
177 }
178
at91_pllb_clk_disable(void)179 int at91_pllb_clk_disable(void)
180 {
181 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
182 ulong start_time, tmp_time;
183
184 start_time = get_timer(0);
185 writel(0, &pmc->pllbr);
186 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
187 tmp_time = get_timer(0);
188 if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
189 printf("ERROR: failed to disable PLLB\n");
190 return -1;
191 }
192 }
193
194 return 0;
195 }
196