1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
5 */
6
7 #include <common.h>
8 #include <ide.h>
9 #include <init.h>
10 #include <net.h>
11 #include <netdev.h>
12 #include <pci.h>
13 #include <pci_gt64120.h>
14 #include <pci_msc01.h>
15 #include <rtc.h>
16 #include <asm/global_data.h>
17 #include <linux/delay.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/io.h>
21 #include <asm/malta.h>
22
23 #include "superio.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 enum core_card {
28 CORE_UNKNOWN,
29 CORE_LV,
30 CORE_FPGA6,
31 };
32
33 enum sys_con {
34 SYSCON_UNKNOWN,
35 SYSCON_GT64120,
36 SYSCON_MSC01,
37 };
38
malta_lcd_puts(const char * str)39 static void malta_lcd_puts(const char *str)
40 {
41 int i;
42 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
43
44 /* print up to 8 characters of the string */
45 for (i = 0; i < min((int)strlen(str), 8); i++) {
46 __raw_writel(str[i], reg);
47 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
48 }
49
50 /* fill the rest of the display with spaces */
51 for (; i < 8; i++) {
52 __raw_writel(' ', reg);
53 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
54 }
55 }
56
malta_core_card(void)57 static enum core_card malta_core_card(void)
58 {
59 u32 corid, rev;
60 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
61
62 rev = __raw_readl(reg);
63 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
64
65 switch (corid) {
66 case MALTA_REVISION_CORID_CORE_LV:
67 return CORE_LV;
68
69 case MALTA_REVISION_CORID_CORE_FPGA6:
70 return CORE_FPGA6;
71
72 default:
73 return CORE_UNKNOWN;
74 }
75 }
76
malta_sys_con(void)77 static enum sys_con malta_sys_con(void)
78 {
79 switch (malta_core_card()) {
80 case CORE_LV:
81 return SYSCON_GT64120;
82
83 case CORE_FPGA6:
84 return SYSCON_MSC01;
85
86 default:
87 return SYSCON_UNKNOWN;
88 }
89 }
90
dram_init(void)91 int dram_init(void)
92 {
93 gd->ram_size = CONFIG_SYS_MEM_SIZE;
94
95 return 0;
96 }
97
checkboard(void)98 int checkboard(void)
99 {
100 enum core_card core;
101
102 malta_lcd_puts("U-Boot");
103 puts("Board: MIPS Malta");
104
105 core = malta_core_card();
106 switch (core) {
107 case CORE_LV:
108 puts(" CoreLV");
109 break;
110
111 case CORE_FPGA6:
112 puts(" CoreFPGA6");
113 break;
114
115 default:
116 puts(" CoreUnknown");
117 }
118
119 putc('\n');
120 return 0;
121 }
122
board_eth_init(struct bd_info * bis)123 int board_eth_init(struct bd_info *bis)
124 {
125 return pci_eth_init(bis);
126 }
127
_machine_restart(void)128 void _machine_restart(void)
129 {
130 void __iomem *reset_base;
131
132 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
133 __raw_writel(GORESET, reset_base);
134 mdelay(1000);
135 }
136
board_early_init_f(void)137 int board_early_init_f(void)
138 {
139 ulong io_base;
140
141 /* choose correct PCI I/O base */
142 switch (malta_sys_con()) {
143 case SYSCON_GT64120:
144 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
145 break;
146
147 case SYSCON_MSC01:
148 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
149 break;
150
151 default:
152 return -1;
153 }
154
155 set_io_port_base(io_base);
156
157 /* setup FDC37M817 super I/O controller */
158 malta_superio_init();
159
160 return 0;
161 }
162
misc_init_r(void)163 int misc_init_r(void)
164 {
165 rtc_reset();
166
167 return 0;
168 }
169
pci_init_board(void)170 void pci_init_board(void)
171 {
172 pci_dev_t bdf;
173 u32 val32;
174 u8 val8;
175
176 switch (malta_sys_con()) {
177 case SYSCON_GT64120:
178 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
179 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
180 0x10000000, 0x10000000, 128 * 1024 * 1024,
181 0x00000000, 0x00000000, 0x20000);
182 break;
183
184 default:
185 case SYSCON_MSC01:
186 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
187 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
188 MALTA_MSC01_PCIMEM_MAP,
189 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
190 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
191 0x00000000, MALTA_MSC01_PCIIO_SIZE);
192 break;
193 }
194
195 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
196 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
197 if (bdf == -1)
198 panic("Failed to find PIIX4 PCI bridge\n");
199
200 /* setup PCI interrupt routing */
201 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
202 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
203 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
204 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
205
206 /* mux SERIRQ onto SERIRQ pin */
207 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
208 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
209 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
210
211 /* enable SERIRQ - Linux currently depends upon this */
212 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
213 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
214 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
215
216 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
217 PCI_DEVICE_ID_INTEL_82371AB, 0);
218 if (bdf == -1)
219 panic("Failed to find PIIX4 IDE controller\n");
220
221 /* enable bus master & IO access */
222 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
223 pci_write_config_dword(bdf, PCI_COMMAND, val32);
224
225 /* set latency */
226 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
227
228 /* enable IDE/ATA */
229 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
230 PCI_CFG_PIIX4_IDETIM_IDE);
231 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
232 PCI_CFG_PIIX4_IDETIM_IDE);
233 }
234