1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
6 *
7 * (C) Copyright 2010
8 * Marvell Semiconductor <www.marvell.com>
9 * Contributor: Mahavir Jain <mjain@marvell.com>
10 */
11
12 #include <common.h>
13 #include <log.h>
14 #include <net.h>
15 #include <malloc.h>
16 #include <miiphy.h>
17 #include <netdev.h>
18 #include <asm/types.h>
19 #include <asm/byteorder.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/mii.h>
23 #include <asm/io.h>
24 #include <asm/arch/armada100.h>
25 #include "armada100_fec.h"
26
27 #define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
28
29 #ifdef DEBUG
eth_dump_regs(struct eth_device * dev)30 static int eth_dump_regs(struct eth_device *dev)
31 {
32 struct armdfec_device *darmdfec = to_darmdfec(dev);
33 struct armdfec_reg *regs = darmdfec->regs;
34 unsigned int i = 0;
35
36 printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
37 printf("offset: smi, value: 0x%x\n", readl(®s->smi));
38 for (i = 0x400; i <= 0x4e4; i += 4)
39 printf("offset: 0x%x, value: 0x%x\n",
40 i, readl(ARMD1_FEC_BASE + i));
41 return 0;
42 }
43 #endif
44
armdfec_phy_timeout(u32 * reg,u32 flag,int cond)45 static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
46 {
47 u32 timeout = PHY_WAIT_ITERATIONS;
48 u32 reg_val;
49
50 while (--timeout) {
51 reg_val = readl(reg);
52 if (cond && (reg_val & flag))
53 break;
54 else if (!cond && !(reg_val & flag))
55 break;
56 udelay(PHY_WAIT_MICRO_SECONDS);
57 }
58 return !timeout;
59 }
60
smi_reg_read(struct mii_dev * bus,int phy_addr,int devad,int phy_reg)61 static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
62 int phy_reg)
63 {
64 u16 value = 0;
65 struct eth_device *dev = eth_get_dev_by_name(bus->name);
66 struct armdfec_device *darmdfec = to_darmdfec(dev);
67 struct armdfec_reg *regs = darmdfec->regs;
68 u32 val;
69
70 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
71 val = readl(®s->phyadr);
72 value = val & 0x1f;
73 return value;
74 }
75
76 /* check parameters */
77 if (phy_addr > PHY_MASK) {
78 printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
79 __func__, phy_addr);
80 return -EINVAL;
81 }
82 if (phy_reg > PHY_MASK) {
83 printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
84 __func__, phy_reg);
85 return -EINVAL;
86 }
87
88 /* wait for the SMI register to become available */
89 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
90 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
91 return -1;
92 }
93
94 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
95
96 /* now wait for the data to be valid */
97 if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
98 val = readl(®s->smi);
99 printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
100 __func__, val);
101 return -1;
102 }
103 val = readl(®s->smi);
104 value = val & 0xffff;
105
106 return value;
107 }
108
smi_reg_write(struct mii_dev * bus,int phy_addr,int devad,int phy_reg,u16 value)109 static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
110 int phy_reg, u16 value)
111 {
112 struct eth_device *dev = eth_get_dev_by_name(bus->name);
113 struct armdfec_device *darmdfec = to_darmdfec(dev);
114 struct armdfec_reg *regs = darmdfec->regs;
115
116 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
117 clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
118 return 0;
119 }
120
121 /* check parameters */
122 if (phy_addr > PHY_MASK) {
123 printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
124 return -EINVAL;
125 }
126 if (phy_reg > PHY_MASK) {
127 printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
128 return -EINVAL;
129 }
130
131 /* wait for the SMI register to become available */
132 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
133 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
134 return -1;
135 }
136
137 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
138 ®s->smi);
139 return 0;
140 }
141
142 /*
143 * Abort any transmit and receive operations and put DMA
144 * in idle state. AT and AR bits are cleared upon entering
145 * in IDLE state. So poll those bits to verify operation.
146 */
abortdma(struct eth_device * dev)147 static void abortdma(struct eth_device *dev)
148 {
149 struct armdfec_device *darmdfec = to_darmdfec(dev);
150 struct armdfec_reg *regs = darmdfec->regs;
151 int delay;
152 int maxretries = 40;
153 u32 tmp;
154
155 while (--maxretries) {
156 writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
157 udelay(100);
158
159 delay = 10;
160 while (--delay) {
161 tmp = readl(®s->sdma_cmd);
162 if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
163 break;
164 udelay(10);
165 }
166 if (delay)
167 break;
168 }
169
170 if (!maxretries)
171 printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
172 }
173
nibble_swapping_32_bit(u32 x)174 static inline u32 nibble_swapping_32_bit(u32 x)
175 {
176 return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
177 }
178
nibble_swapping_16_bit(u32 x)179 static inline u32 nibble_swapping_16_bit(u32 x)
180 {
181 return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
182 }
183
flip_4_bits(u32 x)184 static inline u32 flip_4_bits(u32 x)
185 {
186 return ((x & 0x01) << 3) | ((x & 0x002) << 1)
187 | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
188 }
189
190 /*
191 * This function will calculate the hash function of the address.
192 * depends on the hash mode and hash size.
193 * Inputs
194 * mach - the 2 most significant bytes of the MAC address.
195 * macl - the 4 least significant bytes of the MAC address.
196 * Outputs
197 * return the calculated entry.
198 */
hash_function(u32 mach,u32 macl)199 static u32 hash_function(u32 mach, u32 macl)
200 {
201 u32 hashresult;
202 u32 addrh;
203 u32 addrl;
204 u32 addr0;
205 u32 addr1;
206 u32 addr2;
207 u32 addr3;
208 u32 addrhswapped;
209 u32 addrlswapped;
210
211 addrh = nibble_swapping_16_bit(mach);
212 addrl = nibble_swapping_32_bit(macl);
213
214 addrhswapped = flip_4_bits(addrh & 0xf)
215 + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
216 + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
217 + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
218
219 addrlswapped = flip_4_bits(addrl & 0xf)
220 + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
221 + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
222 + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
223 + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
224 + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
225 + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
226 + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
227
228 addrh = addrhswapped;
229 addrl = addrlswapped;
230
231 addr0 = (addrl >> 2) & 0x03f;
232 addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
233 addr2 = (addrl >> 15) & 0x1ff;
234 addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
235
236 hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
237 hashresult = hashresult & 0x07ff;
238 return hashresult;
239 }
240
241 /*
242 * This function will add an entry to the address table.
243 * depends on the hash mode and hash size that was initialized.
244 * Inputs
245 * mach - the 2 most significant bytes of the MAC address.
246 * macl - the 4 least significant bytes of the MAC address.
247 * skip - if 1, skip this address.
248 * rd - the RD field in the address table.
249 * Outputs
250 * address table entry is added.
251 * 0 if success.
252 * -ENOSPC if table full
253 */
add_del_hash_entry(struct armdfec_device * darmdfec,u32 mach,u32 macl,u32 rd,u32 skip,int del)254 static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
255 u32 macl, u32 rd, u32 skip, int del)
256 {
257 struct addr_table_entry_t *entry, *start;
258 u32 newhi;
259 u32 newlo;
260 u32 i;
261
262 newlo = (((mach >> 4) & 0xf) << 15)
263 | (((mach >> 0) & 0xf) << 11)
264 | (((mach >> 12) & 0xf) << 7)
265 | (((mach >> 8) & 0xf) << 3)
266 | (((macl >> 20) & 0x1) << 31)
267 | (((macl >> 16) & 0xf) << 27)
268 | (((macl >> 28) & 0xf) << 23)
269 | (((macl >> 24) & 0xf) << 19)
270 | (skip << HTESKIP) | (rd << HTERDBIT)
271 | HTEVALID;
272
273 newhi = (((macl >> 4) & 0xf) << 15)
274 | (((macl >> 0) & 0xf) << 11)
275 | (((macl >> 12) & 0xf) << 7)
276 | (((macl >> 8) & 0xf) << 3)
277 | (((macl >> 21) & 0x7) << 0);
278
279 /*
280 * Pick the appropriate table, start scanning for free/reusable
281 * entries at the index obtained by hashing the specified MAC address
282 */
283 start = (struct addr_table_entry_t *)(darmdfec->htpr);
284 entry = start + hash_function(mach, macl);
285 for (i = 0; i < HOP_NUMBER; i++) {
286 if (!(entry->lo & HTEVALID)) {
287 break;
288 } else {
289 /* if same address put in same position */
290 if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
291 && (entry->hi == newhi))
292 break;
293 }
294 if (entry == start + 0x7ff)
295 entry = start;
296 else
297 entry++;
298 }
299
300 if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
301 (entry->hi != newhi) && del)
302 return 0;
303
304 if (i == HOP_NUMBER) {
305 if (!del) {
306 printf("ARMD100 FEC: (%s) table section is full\n",
307 __func__);
308 return -ENOSPC;
309 } else {
310 return 0;
311 }
312 }
313
314 /*
315 * Update the selected entry
316 */
317 if (del) {
318 entry->hi = 0;
319 entry->lo = 0;
320 } else {
321 entry->hi = newhi;
322 entry->lo = newlo;
323 }
324
325 return 0;
326 }
327
328 /*
329 * Create an addressTable entry from MAC address info
330 * found in the specifed net_device struct
331 *
332 * Input : pointer to ethernet interface network device structure
333 * Output : N/A
334 */
update_hash_table_mac_address(struct armdfec_device * darmdfec,u8 * oaddr,u8 * addr)335 static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
336 u8 *oaddr, u8 *addr)
337 {
338 u32 mach;
339 u32 macl;
340
341 /* Delete old entry */
342 if (oaddr) {
343 mach = (oaddr[0] << 8) | oaddr[1];
344 macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
345 (oaddr[4] << 8) | oaddr[5];
346 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
347 }
348
349 /* Add new entry */
350 mach = (addr[0] << 8) | addr[1];
351 macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
352 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
353 }
354
355 /* Address Table Initialization */
init_hashtable(struct eth_device * dev)356 static void init_hashtable(struct eth_device *dev)
357 {
358 struct armdfec_device *darmdfec = to_darmdfec(dev);
359 struct armdfec_reg *regs = darmdfec->regs;
360 memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
361 writel((u32)darmdfec->htpr, ®s->htpr);
362 }
363
364 /*
365 * This detects PHY chip from address 0-31 by reading PHY status
366 * registers. PHY chip can be connected at any of this address.
367 */
ethernet_phy_detect(struct eth_device * dev)368 static int ethernet_phy_detect(struct eth_device *dev)
369 {
370 u32 val;
371 u16 tmp, mii_status;
372 u8 addr;
373
374 for (addr = 0; addr < 32; addr++) {
375 if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
376 /* try next phy */
377 continue;
378
379 /* invalid MII status. More validation required here... */
380 if (mii_status == 0 || mii_status == 0xffff)
381 /* try next phy */
382 continue;
383
384 if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
385 /* try next phy */
386 continue;
387
388 val = tmp << 16;
389 if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
390 /* try next phy */
391 continue;
392
393 val |= tmp;
394
395 if ((val & 0xfffffff0) != 0)
396 return addr;
397 }
398 return -1;
399 }
400
armdfec_init_rx_desc_ring(struct armdfec_device * darmdfec)401 static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
402 {
403 struct rx_desc *p_rx_desc;
404 int i;
405
406 /* initialize the Rx descriptors ring */
407 p_rx_desc = darmdfec->p_rxdesc;
408 for (i = 0; i < RINGSZ; i++) {
409 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
410 p_rx_desc->buf_size = PKTSIZE_ALIGN;
411 p_rx_desc->byte_cnt = 0;
412 p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
413 if (i == (RINGSZ - 1)) {
414 p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
415 } else {
416 p_rx_desc->nxtdesc_p = (struct rx_desc *)
417 ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
418 p_rx_desc = p_rx_desc->nxtdesc_p;
419 }
420 }
421 darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
422 }
423
armdfec_init(struct eth_device * dev,struct bd_info * bd)424 static int armdfec_init(struct eth_device *dev, struct bd_info *bd)
425 {
426 struct armdfec_device *darmdfec = to_darmdfec(dev);
427 struct armdfec_reg *regs = darmdfec->regs;
428 int phy_adr;
429 u32 temp;
430
431 armdfec_init_rx_desc_ring(darmdfec);
432
433 /* Disable interrupts */
434 writel(0, ®s->im);
435 writel(0, ®s->ic);
436 /* Write to ICR to clear interrupts. */
437 writel(0, ®s->iwc);
438
439 /*
440 * Abort any transmit and receive operations and put DMA
441 * in idle state.
442 */
443 abortdma(dev);
444
445 /* Initialize address hash table */
446 init_hashtable(dev);
447
448 /* SDMA configuration */
449 writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
450 SDCR_RIFB | /* Rx interrupt on frame */
451 SDCR_BLMT | /* Little endian transmit */
452 SDCR_BLMR | /* Little endian receive */
453 SDCR_RC_MAX_RETRANS, /* Max retransmit count */
454 ®s->sdma_conf);
455 /* Port Configuration */
456 writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
457
458 /* Set extended port configuration */
459 writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
460 PCXR_DSCP_EN | /* Enable DSCP in IP */
461 PCXR_MFL_1536 | /* Set MTU = 1536 */
462 PCXR_FLP | /* do not force link pass */
463 PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
464 ®s->pconf_ext);
465
466 update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
467
468 /* Update TX and RX queue descriptor register */
469 temp = (u32)®s->txcdp[TXQ];
470 writel((u32)darmdfec->p_txdesc, temp);
471 temp = (u32)®s->rxfdp[RXQ];
472 writel((u32)darmdfec->p_rxdesc, temp);
473 temp = (u32)®s->rxcdp[RXQ];
474 writel((u32)darmdfec->p_rxdesc_curr, temp);
475
476 /* Enable Interrupts */
477 writel(ALL_INTS, ®s->im);
478
479 /* Enable Ethernet Port */
480 setbits_le32(®s->pconf, PCR_EN);
481
482 /* Enable RX DMA engine */
483 setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
484
485 #ifdef DEBUG
486 eth_dump_regs(dev);
487 #endif
488
489 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
490
491 #if defined(CONFIG_PHY_BASE_ADR)
492 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
493 #else
494 /* Search phy address from range 0-31 */
495 phy_adr = ethernet_phy_detect(dev);
496 if (phy_adr < 0) {
497 printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
498 return -1;
499 } else {
500 debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
501 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
502 }
503 #endif
504
505 #if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
506 /* Wait up to 5s for the link status */
507 for (i = 0; i < 5; i++) {
508 u16 phy_adr;
509
510 miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
511 /* Return if we get link up */
512 if (miiphy_link(dev->name, phy_adr))
513 return 0;
514 udelay(1000000);
515 }
516
517 printf("ARMD100 FEC: No link on %s\n", dev->name);
518 return -1;
519 #endif
520 #endif
521 return 0;
522 }
523
armdfec_halt(struct eth_device * dev)524 static void armdfec_halt(struct eth_device *dev)
525 {
526 struct armdfec_device *darmdfec = to_darmdfec(dev);
527 struct armdfec_reg *regs = darmdfec->regs;
528
529 /* Stop RX DMA */
530 clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
531
532 /*
533 * Abort any transmit and receive operations and put DMA
534 * in idle state.
535 */
536 abortdma(dev);
537
538 /* Disable interrupts */
539 writel(0, ®s->im);
540 writel(0, ®s->ic);
541 writel(0, ®s->iwc);
542
543 /* Disable Port */
544 clrbits_le32(®s->pconf, PCR_EN);
545 }
546
armdfec_send(struct eth_device * dev,void * dataptr,int datasize)547 static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
548 {
549 struct armdfec_device *darmdfec = to_darmdfec(dev);
550 struct armdfec_reg *regs = darmdfec->regs;
551 struct tx_desc *p_txdesc = darmdfec->p_txdesc;
552 void *p = (void *)dataptr;
553 int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
554 u32 cmd_sts, temp;
555
556 /* Copy buffer if it's misaligned */
557 if ((u32)dataptr & 0x07) {
558 if (datasize > PKTSIZE_ALIGN) {
559 printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
560 datasize);
561 return -1;
562 }
563 memcpy(darmdfec->p_aligned_txbuf, p, datasize);
564 p = darmdfec->p_aligned_txbuf;
565 }
566
567 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
568 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
569 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
570 p_txdesc->cmd_sts |= TX_EN_INT;
571 p_txdesc->buf_ptr = p;
572 p_txdesc->byte_cnt = datasize;
573
574 /* Apply send command using high priority TX queue */
575 temp = (u32)®s->txcdp[TXQ];
576 writel((u32)p_txdesc, temp);
577 writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
578
579 /*
580 * wait for packet xmit completion
581 */
582 cmd_sts = readl(&p_txdesc->cmd_sts);
583 while (cmd_sts & BUF_OWNED_BY_DMA) {
584 /* return fail if error is detected */
585 if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
586 (TX_ERROR | TX_LAST_DESC)) {
587 printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
588 return -1;
589 }
590 cmd_sts = readl(&p_txdesc->cmd_sts);
591 if (!(retry--)) {
592 printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
593 __func__);
594 return -1;
595 }
596 }
597
598 return 0;
599 }
600
armdfec_recv(struct eth_device * dev)601 static int armdfec_recv(struct eth_device *dev)
602 {
603 struct armdfec_device *darmdfec = to_darmdfec(dev);
604 struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
605 u32 cmd_sts;
606 u32 timeout = 0;
607 u32 temp;
608
609 /* wait untill rx packet available or timeout */
610 do {
611 if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
612 timeout++;
613 } else {
614 debug("ARMD100 FEC: %s time out...\n", __func__);
615 return -1;
616 }
617 } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
618
619 if (p_rxdesc_curr->byte_cnt != 0) {
620 debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
621 "(cmd_sts= %08x)\n", __func__,
622 (u32)p_rxdesc_curr->byte_cnt,
623 (u32)p_rxdesc_curr->buf_ptr,
624 (u32)p_rxdesc_curr->cmd_sts);
625 }
626
627 /*
628 * In case received a packet without first/last bits on
629 * OR the error summary bit is on,
630 * the packets needs to be dropeed.
631 */
632 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
633
634 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
635 (RX_FIRST_DESC | RX_LAST_DESC)) {
636 printf("ARMD100 FEC: (%s) Dropping packet spread on"
637 " multiple descriptors\n", __func__);
638 } else if (cmd_sts & RX_ERROR) {
639 printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
640 __func__);
641 } else {
642 /* !!! call higher layer processing */
643 debug("ARMD100 FEC: (%s) Sending Received packet to"
644 " upper layer (net_process_received_packet)\n", __func__);
645
646 /*
647 * let the upper layer handle the packet, subtract offset
648 * as two dummy bytes are added in received buffer see
649 * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
650 */
651 net_process_received_packet(
652 p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
653 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
654 }
655 /*
656 * free these descriptors and point next in the ring
657 */
658 p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
659 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
660 p_rxdesc_curr->byte_cnt = 0;
661
662 temp = (u32)&darmdfec->p_rxdesc_curr;
663 writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
664
665 return 0;
666 }
667
armada100_fec_register(unsigned long base_addr)668 int armada100_fec_register(unsigned long base_addr)
669 {
670 struct armdfec_device *darmdfec;
671 struct eth_device *dev;
672
673 darmdfec = malloc(sizeof(struct armdfec_device));
674 if (!darmdfec)
675 goto error;
676
677 memset(darmdfec, 0, sizeof(struct armdfec_device));
678
679 darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
680 if (!darmdfec->htpr)
681 goto error1;
682
683 darmdfec->p_rxdesc = memalign(PKTALIGN,
684 ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
685
686 if (!darmdfec->p_rxdesc)
687 goto error1;
688
689 darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
690 if (!darmdfec->p_rxbuf)
691 goto error1;
692
693 darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
694 if (!darmdfec->p_aligned_txbuf)
695 goto error1;
696
697 darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
698 if (!darmdfec->p_txdesc)
699 goto error1;
700
701 dev = &darmdfec->dev;
702 /* Assign ARMADA100 Fast Ethernet Controller Base Address */
703 darmdfec->regs = (void *)base_addr;
704
705 /* must be less than sizeof(dev->name) */
706 strcpy(dev->name, "armd-fec0");
707
708 dev->init = armdfec_init;
709 dev->halt = armdfec_halt;
710 dev->send = armdfec_send;
711 dev->recv = armdfec_recv;
712
713 eth_register(dev);
714
715 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
716 int retval;
717 struct mii_dev *mdiodev = mdio_alloc();
718 if (!mdiodev)
719 return -ENOMEM;
720 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
721 mdiodev->read = smi_reg_read;
722 mdiodev->write = smi_reg_write;
723
724 retval = mdio_register(mdiodev);
725 if (retval < 0)
726 return retval;
727 #endif
728 return 0;
729
730 error1:
731 free(darmdfec->p_aligned_txbuf);
732 free(darmdfec->p_rxbuf);
733 free(darmdfec->p_rxdesc);
734 free(darmdfec->htpr);
735 error:
736 free(darmdfec);
737 printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
738 return -1;
739 }
740