1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 */
6
7 /*
8 * Designware ethernet IP driver for U-Boot
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <cpu_func.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <log.h>
17 #include <miiphy.h>
18 #include <malloc.h>
19 #include <net.h>
20 #include <pci.h>
21 #include <reset.h>
22 #include <asm/cache.h>
23 #include <dm/device_compat.h>
24 #include <dm/device-internal.h>
25 #include <dm/devres.h>
26 #include <dm/lists.h>
27 #include <linux/compiler.h>
28 #include <linux/delay.h>
29 #include <linux/err.h>
30 #include <linux/kernel.h>
31 #include <asm/io.h>
32 #include <power/regulator.h>
33 #include "designware.h"
34
dw_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)35 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
36 {
37 #ifdef CONFIG_DM_ETH
38 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
39 struct eth_mac_regs *mac_p = priv->mac_regs_p;
40 #else
41 struct eth_mac_regs *mac_p = bus->priv;
42 #endif
43 ulong start;
44 u16 miiaddr;
45 int timeout = CONFIG_MDIO_TIMEOUT;
46
47 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
48 ((reg << MIIREGSHIFT) & MII_REGMSK);
49
50 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
51
52 start = get_timer(0);
53 while (get_timer(start) < timeout) {
54 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
55 return readl(&mac_p->miidata);
56 udelay(10);
57 };
58
59 return -ETIMEDOUT;
60 }
61
dw_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)62 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
63 u16 val)
64 {
65 #ifdef CONFIG_DM_ETH
66 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
67 struct eth_mac_regs *mac_p = priv->mac_regs_p;
68 #else
69 struct eth_mac_regs *mac_p = bus->priv;
70 #endif
71 ulong start;
72 u16 miiaddr;
73 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
74
75 writel(val, &mac_p->miidata);
76 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
77 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
78
79 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
80
81 start = get_timer(0);
82 while (get_timer(start) < timeout) {
83 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
84 ret = 0;
85 break;
86 }
87 udelay(10);
88 };
89
90 return ret;
91 }
92
93 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
__dw_mdio_reset(struct udevice * dev)94 static int __dw_mdio_reset(struct udevice *dev)
95 {
96 struct dw_eth_dev *priv = dev_get_priv(dev);
97 struct dw_eth_pdata *pdata = dev_get_plat(dev);
98 int ret;
99
100 if (!dm_gpio_is_valid(&priv->reset_gpio))
101 return 0;
102
103 /* reset the phy */
104 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
105 if (ret)
106 return ret;
107
108 udelay(pdata->reset_delays[0]);
109
110 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
111 if (ret)
112 return ret;
113
114 udelay(pdata->reset_delays[1]);
115
116 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
117 if (ret)
118 return ret;
119
120 udelay(pdata->reset_delays[2]);
121
122 return 0;
123 }
124
dw_mdio_reset(struct mii_dev * bus)125 static int dw_mdio_reset(struct mii_dev *bus)
126 {
127 struct udevice *dev = bus->priv;
128
129 return __dw_mdio_reset(dev);
130 }
131 #endif
132
133 #if IS_ENABLED(CONFIG_DM_MDIO)
designware_eth_mdio_read(struct udevice * mdio_dev,int addr,int devad,int reg)134 int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
135 {
136 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
137
138 return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
139 }
140
designware_eth_mdio_write(struct udevice * mdio_dev,int addr,int devad,int reg,u16 val)141 int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
142 {
143 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
144
145 return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
146 }
147
148 #if CONFIG_IS_ENABLED(DM_GPIO)
designware_eth_mdio_reset(struct udevice * mdio_dev)149 int designware_eth_mdio_reset(struct udevice *mdio_dev)
150 {
151 struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
152 struct udevice *dev = mdio_pdata->mii_bus->priv;
153
154 return __dw_mdio_reset(dev->parent);
155 }
156 #endif
157
158 static const struct mdio_ops designware_eth_mdio_ops = {
159 .read = designware_eth_mdio_read,
160 .write = designware_eth_mdio_write,
161 #if CONFIG_IS_ENABLED(DM_GPIO)
162 .reset = designware_eth_mdio_reset,
163 #endif
164 };
165
designware_eth_mdio_probe(struct udevice * dev)166 static int designware_eth_mdio_probe(struct udevice *dev)
167 {
168 /* Use the priv data of parent */
169 dev_set_priv(dev, dev_get_priv(dev->parent));
170
171 return 0;
172 }
173
174 U_BOOT_DRIVER(designware_eth_mdio) = {
175 .name = "eth_designware_mdio",
176 .id = UCLASS_MDIO,
177 .probe = designware_eth_mdio_probe,
178 .ops = &designware_eth_mdio_ops,
179 .plat_auto = sizeof(struct mdio_perdev_priv),
180 };
181 #endif
182
dw_mdio_init(const char * name,void * priv)183 static int dw_mdio_init(const char *name, void *priv)
184 {
185 struct mii_dev *bus = mdio_alloc();
186
187 if (!bus) {
188 printf("Failed to allocate MDIO bus\n");
189 return -ENOMEM;
190 }
191
192 bus->read = dw_mdio_read;
193 bus->write = dw_mdio_write;
194 snprintf(bus->name, sizeof(bus->name), "%s", name);
195 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
196 bus->reset = dw_mdio_reset;
197 #endif
198
199 bus->priv = priv;
200
201 return mdio_register(bus);
202 }
203
204 #if IS_ENABLED(CONFIG_DM_MDIO)
dw_dm_mdio_init(const char * name,void * priv)205 static int dw_dm_mdio_init(const char *name, void *priv)
206 {
207 struct udevice *dev = priv;
208 ofnode node;
209 int ret;
210
211 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
212 const char *subnode_name = ofnode_get_name(node);
213 struct udevice *mdiodev;
214
215 if (strcmp(subnode_name, "mdio"))
216 continue;
217
218 ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
219 subnode_name, node, &mdiodev);
220 if (ret)
221 debug("%s: not able to bind mdio device node\n", __func__);
222
223 return 0;
224 }
225
226 printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
227
228 return dw_mdio_init(name, priv);
229 }
230 #endif
231
tx_descs_init(struct dw_eth_dev * priv)232 static void tx_descs_init(struct dw_eth_dev *priv)
233 {
234 struct eth_dma_regs *dma_p = priv->dma_regs_p;
235 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
236 char *txbuffs = &priv->txbuffs[0];
237 struct dmamacdescr *desc_p;
238 u32 idx;
239
240 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
241 desc_p = &desc_table_p[idx];
242 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
243 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
244
245 #if defined(CONFIG_DW_ALTDESCRIPTOR)
246 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
247 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
248 DESC_TXSTS_TXCHECKINSCTRL |
249 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
250
251 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
252 desc_p->dmamac_cntl = 0;
253 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
254 #else
255 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
256 desc_p->txrx_status = 0;
257 #endif
258 }
259
260 /* Correcting the last pointer of the chain */
261 desc_p->dmamac_next = (ulong)&desc_table_p[0];
262
263 /* Flush all Tx buffer descriptors at once */
264 flush_dcache_range((ulong)priv->tx_mac_descrtable,
265 (ulong)priv->tx_mac_descrtable +
266 sizeof(priv->tx_mac_descrtable));
267
268 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
269 priv->tx_currdescnum = 0;
270 }
271
rx_descs_init(struct dw_eth_dev * priv)272 static void rx_descs_init(struct dw_eth_dev *priv)
273 {
274 struct eth_dma_regs *dma_p = priv->dma_regs_p;
275 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
276 char *rxbuffs = &priv->rxbuffs[0];
277 struct dmamacdescr *desc_p;
278 u32 idx;
279
280 /* Before passing buffers to GMAC we need to make sure zeros
281 * written there right after "priv" structure allocation were
282 * flushed into RAM.
283 * Otherwise there's a chance to get some of them flushed in RAM when
284 * GMAC is already pushing data to RAM via DMA. This way incoming from
285 * GMAC data will be corrupted. */
286 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
287
288 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
289 desc_p = &desc_table_p[idx];
290 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
291 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
292
293 desc_p->dmamac_cntl =
294 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
295 DESC_RXCTRL_RXCHAIN;
296
297 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
298 }
299
300 /* Correcting the last pointer of the chain */
301 desc_p->dmamac_next = (ulong)&desc_table_p[0];
302
303 /* Flush all Rx buffer descriptors at once */
304 flush_dcache_range((ulong)priv->rx_mac_descrtable,
305 (ulong)priv->rx_mac_descrtable +
306 sizeof(priv->rx_mac_descrtable));
307
308 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
309 priv->rx_currdescnum = 0;
310 }
311
_dw_write_hwaddr(struct dw_eth_dev * priv,u8 * mac_id)312 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
313 {
314 struct eth_mac_regs *mac_p = priv->mac_regs_p;
315 u32 macid_lo, macid_hi;
316
317 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
318 (mac_id[3] << 24);
319 macid_hi = mac_id[4] + (mac_id[5] << 8);
320
321 writel(macid_hi, &mac_p->macaddr0hi);
322 writel(macid_lo, &mac_p->macaddr0lo);
323
324 return 0;
325 }
326
dw_adjust_link(struct dw_eth_dev * priv,struct eth_mac_regs * mac_p,struct phy_device * phydev)327 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
328 struct phy_device *phydev)
329 {
330 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
331
332 if (!phydev->link) {
333 printf("%s: No link.\n", phydev->dev->name);
334 return 0;
335 }
336
337 if (phydev->speed != 1000)
338 conf |= MII_PORTSELECT;
339 else
340 conf &= ~MII_PORTSELECT;
341
342 if (phydev->speed == 100)
343 conf |= FES_100;
344
345 if (phydev->duplex)
346 conf |= FULLDPLXMODE;
347
348 writel(conf, &mac_p->conf);
349
350 printf("Speed: %d, %s duplex%s\n", phydev->speed,
351 (phydev->duplex) ? "full" : "half",
352 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
353
354 return 0;
355 }
356
_dw_eth_halt(struct dw_eth_dev * priv)357 static void _dw_eth_halt(struct dw_eth_dev *priv)
358 {
359 struct eth_mac_regs *mac_p = priv->mac_regs_p;
360 struct eth_dma_regs *dma_p = priv->dma_regs_p;
361
362 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
363 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
364
365 phy_shutdown(priv->phydev);
366 }
367
designware_eth_init(struct dw_eth_dev * priv,u8 * enetaddr)368 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
369 {
370 struct eth_mac_regs *mac_p = priv->mac_regs_p;
371 struct eth_dma_regs *dma_p = priv->dma_regs_p;
372 unsigned int start;
373 int ret;
374
375 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
376
377 /*
378 * When a MII PHY is used, we must set the PS bit for the DMA
379 * reset to succeed.
380 */
381 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
382 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
383 else
384 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
385
386 start = get_timer(0);
387 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
388 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
389 printf("DMA reset timeout\n");
390 return -ETIMEDOUT;
391 }
392
393 mdelay(100);
394 };
395
396 /*
397 * Soft reset above clears HW address registers.
398 * So we have to set it here once again.
399 */
400 _dw_write_hwaddr(priv, enetaddr);
401
402 rx_descs_init(priv);
403 tx_descs_init(priv);
404
405 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
406
407 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
408 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
409 &dma_p->opmode);
410 #else
411 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
412 &dma_p->opmode);
413 #endif
414
415 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
416
417 #ifdef CONFIG_DW_AXI_BURST_LEN
418 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
419 #endif
420
421 /* Start up the PHY */
422 ret = phy_startup(priv->phydev);
423 if (ret) {
424 printf("Could not initialize PHY %s\n",
425 priv->phydev->dev->name);
426 return ret;
427 }
428
429 ret = dw_adjust_link(priv, mac_p, priv->phydev);
430 if (ret)
431 return ret;
432
433 return 0;
434 }
435
designware_eth_enable(struct dw_eth_dev * priv)436 int designware_eth_enable(struct dw_eth_dev *priv)
437 {
438 struct eth_mac_regs *mac_p = priv->mac_regs_p;
439
440 if (!priv->phydev->link)
441 return -EIO;
442
443 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
444
445 return 0;
446 }
447
448 #define ETH_ZLEN 60
449
_dw_eth_send(struct dw_eth_dev * priv,void * packet,int length)450 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
451 {
452 struct eth_dma_regs *dma_p = priv->dma_regs_p;
453 u32 desc_num = priv->tx_currdescnum;
454 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
455 ulong desc_start = (ulong)desc_p;
456 ulong desc_end = desc_start +
457 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
458 ulong data_start = desc_p->dmamac_addr;
459 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
460 /*
461 * Strictly we only need to invalidate the "txrx_status" field
462 * for the following check, but on some platforms we cannot
463 * invalidate only 4 bytes, so we flush the entire descriptor,
464 * which is 16 bytes in total. This is safe because the
465 * individual descriptors in the array are each aligned to
466 * ARCH_DMA_MINALIGN and padded appropriately.
467 */
468 invalidate_dcache_range(desc_start, desc_end);
469
470 /* Check if the descriptor is owned by CPU */
471 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
472 printf("CPU not owner of tx frame\n");
473 return -EPERM;
474 }
475
476 memcpy((void *)data_start, packet, length);
477 if (length < ETH_ZLEN) {
478 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
479 length = ETH_ZLEN;
480 }
481
482 /* Flush data to be sent */
483 flush_dcache_range(data_start, data_end);
484
485 #if defined(CONFIG_DW_ALTDESCRIPTOR)
486 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
487 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
488 ((length << DESC_TXCTRL_SIZE1SHFT) &
489 DESC_TXCTRL_SIZE1MASK);
490
491 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
492 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
493 #else
494 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
495 ((length << DESC_TXCTRL_SIZE1SHFT) &
496 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
497 DESC_TXCTRL_TXFIRST;
498
499 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
500 #endif
501
502 /* Flush modified buffer descriptor */
503 flush_dcache_range(desc_start, desc_end);
504
505 /* Test the wrap-around condition. */
506 if (++desc_num >= CONFIG_TX_DESCR_NUM)
507 desc_num = 0;
508
509 priv->tx_currdescnum = desc_num;
510
511 /* Start the transmission */
512 writel(POLL_DATA, &dma_p->txpolldemand);
513
514 return 0;
515 }
516
_dw_eth_recv(struct dw_eth_dev * priv,uchar ** packetp)517 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
518 {
519 u32 status, desc_num = priv->rx_currdescnum;
520 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
521 int length = -EAGAIN;
522 ulong desc_start = (ulong)desc_p;
523 ulong desc_end = desc_start +
524 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
525 ulong data_start = desc_p->dmamac_addr;
526 ulong data_end;
527
528 /* Invalidate entire buffer descriptor */
529 invalidate_dcache_range(desc_start, desc_end);
530
531 status = desc_p->txrx_status;
532
533 /* Check if the owner is the CPU */
534 if (!(status & DESC_RXSTS_OWNBYDMA)) {
535
536 length = (status & DESC_RXSTS_FRMLENMSK) >>
537 DESC_RXSTS_FRMLENSHFT;
538
539 /* Invalidate received data */
540 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
541 invalidate_dcache_range(data_start, data_end);
542 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
543 }
544
545 return length;
546 }
547
_dw_free_pkt(struct dw_eth_dev * priv)548 static int _dw_free_pkt(struct dw_eth_dev *priv)
549 {
550 u32 desc_num = priv->rx_currdescnum;
551 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
552 ulong desc_start = (ulong)desc_p;
553 ulong desc_end = desc_start +
554 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
555
556 /*
557 * Make the current descriptor valid again and go to
558 * the next one
559 */
560 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
561
562 /* Flush only status field - others weren't changed */
563 flush_dcache_range(desc_start, desc_end);
564
565 /* Test the wrap-around condition. */
566 if (++desc_num >= CONFIG_RX_DESCR_NUM)
567 desc_num = 0;
568 priv->rx_currdescnum = desc_num;
569
570 return 0;
571 }
572
dw_phy_init(struct dw_eth_dev * priv,void * dev)573 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
574 {
575 struct phy_device *phydev;
576 int ret;
577
578 #if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
579 phydev = dm_eth_phy_connect(dev);
580 if (!phydev)
581 return -ENODEV;
582 #else
583 int phy_addr = -1;
584
585 #ifdef CONFIG_PHY_ADDR
586 phy_addr = CONFIG_PHY_ADDR;
587 #endif
588
589 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
590 if (!phydev)
591 return -ENODEV;
592 #endif
593
594 phydev->supported &= PHY_GBIT_FEATURES;
595 if (priv->max_speed) {
596 ret = phy_set_supported(phydev, priv->max_speed);
597 if (ret)
598 return ret;
599 }
600 phydev->advertising = phydev->supported;
601
602 priv->phydev = phydev;
603 phy_config(phydev);
604
605 return 0;
606 }
607
608 #ifndef CONFIG_DM_ETH
dw_eth_init(struct eth_device * dev,struct bd_info * bis)609 static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
610 {
611 int ret;
612
613 ret = designware_eth_init(dev->priv, dev->enetaddr);
614 if (!ret)
615 ret = designware_eth_enable(dev->priv);
616
617 return ret;
618 }
619
dw_eth_send(struct eth_device * dev,void * packet,int length)620 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
621 {
622 return _dw_eth_send(dev->priv, packet, length);
623 }
624
dw_eth_recv(struct eth_device * dev)625 static int dw_eth_recv(struct eth_device *dev)
626 {
627 uchar *packet;
628 int length;
629
630 length = _dw_eth_recv(dev->priv, &packet);
631 if (length == -EAGAIN)
632 return 0;
633 net_process_received_packet(packet, length);
634
635 _dw_free_pkt(dev->priv);
636
637 return 0;
638 }
639
dw_eth_halt(struct eth_device * dev)640 static void dw_eth_halt(struct eth_device *dev)
641 {
642 return _dw_eth_halt(dev->priv);
643 }
644
dw_write_hwaddr(struct eth_device * dev)645 static int dw_write_hwaddr(struct eth_device *dev)
646 {
647 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
648 }
649
designware_initialize(ulong base_addr,u32 interface)650 int designware_initialize(ulong base_addr, u32 interface)
651 {
652 struct eth_device *dev;
653 struct dw_eth_dev *priv;
654
655 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
656 if (!dev)
657 return -ENOMEM;
658
659 /*
660 * Since the priv structure contains the descriptors which need a strict
661 * buswidth alignment, memalign is used to allocate memory
662 */
663 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
664 sizeof(struct dw_eth_dev));
665 if (!priv) {
666 free(dev);
667 return -ENOMEM;
668 }
669
670 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
671 printf("designware: buffers are outside DMA memory\n");
672 return -EINVAL;
673 }
674
675 memset(dev, 0, sizeof(struct eth_device));
676 memset(priv, 0, sizeof(struct dw_eth_dev));
677
678 sprintf(dev->name, "dwmac.%lx", base_addr);
679 dev->iobase = (int)base_addr;
680 dev->priv = priv;
681
682 priv->dev = dev;
683 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
684 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
685 DW_DMA_BASE_OFFSET);
686
687 dev->init = dw_eth_init;
688 dev->send = dw_eth_send;
689 dev->recv = dw_eth_recv;
690 dev->halt = dw_eth_halt;
691 dev->write_hwaddr = dw_write_hwaddr;
692
693 eth_register(dev);
694
695 priv->interface = interface;
696
697 dw_mdio_init(dev->name, priv->mac_regs_p);
698 priv->bus = miiphy_get_dev_by_name(dev->name);
699
700 return dw_phy_init(priv, dev);
701 }
702 #endif
703
704 #ifdef CONFIG_DM_ETH
designware_eth_start(struct udevice * dev)705 static int designware_eth_start(struct udevice *dev)
706 {
707 struct eth_pdata *pdata = dev_get_plat(dev);
708 struct dw_eth_dev *priv = dev_get_priv(dev);
709 int ret;
710
711 ret = designware_eth_init(priv, pdata->enetaddr);
712 if (ret)
713 return ret;
714 ret = designware_eth_enable(priv);
715 if (ret)
716 return ret;
717
718 return 0;
719 }
720
designware_eth_send(struct udevice * dev,void * packet,int length)721 int designware_eth_send(struct udevice *dev, void *packet, int length)
722 {
723 struct dw_eth_dev *priv = dev_get_priv(dev);
724
725 return _dw_eth_send(priv, packet, length);
726 }
727
designware_eth_recv(struct udevice * dev,int flags,uchar ** packetp)728 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
729 {
730 struct dw_eth_dev *priv = dev_get_priv(dev);
731
732 return _dw_eth_recv(priv, packetp);
733 }
734
designware_eth_free_pkt(struct udevice * dev,uchar * packet,int length)735 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
736 {
737 struct dw_eth_dev *priv = dev_get_priv(dev);
738
739 return _dw_free_pkt(priv);
740 }
741
designware_eth_stop(struct udevice * dev)742 void designware_eth_stop(struct udevice *dev)
743 {
744 struct dw_eth_dev *priv = dev_get_priv(dev);
745
746 return _dw_eth_halt(priv);
747 }
748
designware_eth_write_hwaddr(struct udevice * dev)749 int designware_eth_write_hwaddr(struct udevice *dev)
750 {
751 struct eth_pdata *pdata = dev_get_plat(dev);
752 struct dw_eth_dev *priv = dev_get_priv(dev);
753
754 return _dw_write_hwaddr(priv, pdata->enetaddr);
755 }
756
designware_eth_bind(struct udevice * dev)757 static int designware_eth_bind(struct udevice *dev)
758 {
759 #ifdef CONFIG_DM_PCI
760 static int num_cards;
761 char name[20];
762
763 /* Create a unique device name for PCI type devices */
764 if (device_is_on_pci_bus(dev)) {
765 sprintf(name, "eth_designware#%u", num_cards++);
766 device_set_name(dev, name);
767 }
768 #endif
769
770 return 0;
771 }
772
designware_eth_probe(struct udevice * dev)773 int designware_eth_probe(struct udevice *dev)
774 {
775 struct eth_pdata *pdata = dev_get_plat(dev);
776 struct dw_eth_dev *priv = dev_get_priv(dev);
777 u32 iobase = pdata->iobase;
778 ulong ioaddr;
779 int ret, err;
780 struct reset_ctl_bulk reset_bulk;
781 #ifdef CONFIG_CLK
782 int i, clock_nb;
783
784 priv->clock_count = 0;
785 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
786 0);
787 if (clock_nb > 0) {
788 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
789 GFP_KERNEL);
790 if (!priv->clocks)
791 return -ENOMEM;
792
793 for (i = 0; i < clock_nb; i++) {
794 err = clk_get_by_index(dev, i, &priv->clocks[i]);
795 if (err < 0)
796 break;
797
798 err = clk_enable(&priv->clocks[i]);
799 if (err && err != -ENOSYS && err != -ENOTSUPP) {
800 pr_err("failed to enable clock %d\n", i);
801 clk_free(&priv->clocks[i]);
802 goto clk_err;
803 }
804 priv->clock_count++;
805 }
806 } else if (clock_nb != -ENOENT) {
807 pr_err("failed to get clock phandle(%d)\n", clock_nb);
808 return clock_nb;
809 }
810 #endif
811
812 #if defined(CONFIG_DM_REGULATOR)
813 struct udevice *phy_supply;
814
815 ret = device_get_supply_regulator(dev, "phy-supply",
816 &phy_supply);
817 if (ret) {
818 debug("%s: No phy supply\n", dev->name);
819 } else {
820 ret = regulator_set_enable(phy_supply, true);
821 if (ret) {
822 puts("Error enabling phy supply\n");
823 return ret;
824 }
825 }
826 #endif
827
828 ret = reset_get_bulk(dev, &reset_bulk);
829 if (ret)
830 dev_warn(dev, "Can't get reset: %d\n", ret);
831 else
832 reset_deassert_bulk(&reset_bulk);
833
834 #ifdef CONFIG_DM_PCI
835 /*
836 * If we are on PCI bus, either directly attached to a PCI root port,
837 * or via a PCI bridge, fill in plat before we probe the hardware.
838 */
839 if (device_is_on_pci_bus(dev)) {
840 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
841 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
842 iobase = dm_pci_mem_to_phys(dev, iobase);
843
844 pdata->iobase = iobase;
845 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
846 }
847 #endif
848
849 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
850 ioaddr = iobase;
851 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
852 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
853 priv->interface = pdata->phy_interface;
854 priv->max_speed = pdata->max_speed;
855
856 #if IS_ENABLED(CONFIG_DM_MDIO)
857 ret = dw_dm_mdio_init(dev->name, dev);
858 #else
859 ret = dw_mdio_init(dev->name, dev);
860 #endif
861 if (ret) {
862 err = ret;
863 goto mdio_err;
864 }
865 priv->bus = miiphy_get_dev_by_name(dev->name);
866
867 ret = dw_phy_init(priv, dev);
868 debug("%s, ret=%d\n", __func__, ret);
869 if (!ret)
870 return 0;
871
872 /* continue here for cleanup if no PHY found */
873 err = ret;
874 mdio_unregister(priv->bus);
875 mdio_free(priv->bus);
876 mdio_err:
877
878 #ifdef CONFIG_CLK
879 clk_err:
880 ret = clk_release_all(priv->clocks, priv->clock_count);
881 if (ret)
882 pr_err("failed to disable all clocks\n");
883
884 #endif
885 return err;
886 }
887
designware_eth_remove(struct udevice * dev)888 static int designware_eth_remove(struct udevice *dev)
889 {
890 struct dw_eth_dev *priv = dev_get_priv(dev);
891
892 free(priv->phydev);
893 mdio_unregister(priv->bus);
894 mdio_free(priv->bus);
895
896 #ifdef CONFIG_CLK
897 return clk_release_all(priv->clocks, priv->clock_count);
898 #else
899 return 0;
900 #endif
901 }
902
903 const struct eth_ops designware_eth_ops = {
904 .start = designware_eth_start,
905 .send = designware_eth_send,
906 .recv = designware_eth_recv,
907 .free_pkt = designware_eth_free_pkt,
908 .stop = designware_eth_stop,
909 .write_hwaddr = designware_eth_write_hwaddr,
910 };
911
designware_eth_of_to_plat(struct udevice * dev)912 int designware_eth_of_to_plat(struct udevice *dev)
913 {
914 struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
915 #if CONFIG_IS_ENABLED(DM_GPIO)
916 struct dw_eth_dev *priv = dev_get_priv(dev);
917 #endif
918 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
919 const char *phy_mode;
920 #if CONFIG_IS_ENABLED(DM_GPIO)
921 int reset_flags = GPIOD_IS_OUT;
922 #endif
923 int ret = 0;
924
925 pdata->iobase = dev_read_addr(dev);
926 pdata->phy_interface = -1;
927 phy_mode = dev_read_string(dev, "phy-mode");
928 if (phy_mode)
929 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
930 if (pdata->phy_interface == -1) {
931 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
932 return -EINVAL;
933 }
934
935 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
936
937 #if CONFIG_IS_ENABLED(DM_GPIO)
938 if (dev_read_bool(dev, "snps,reset-active-low"))
939 reset_flags |= GPIOD_ACTIVE_LOW;
940
941 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
942 &priv->reset_gpio, reset_flags);
943 if (ret == 0) {
944 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
945 dw_pdata->reset_delays, 3);
946 } else if (ret == -ENOENT) {
947 ret = 0;
948 }
949 #endif
950
951 return ret;
952 }
953
954 static const struct udevice_id designware_eth_ids[] = {
955 { .compatible = "allwinner,sun7i-a20-gmac" },
956 { .compatible = "amlogic,meson6-dwmac" },
957 { .compatible = "st,stm32-dwmac" },
958 { .compatible = "snps,arc-dwmac-3.70a" },
959 { }
960 };
961
962 U_BOOT_DRIVER(eth_designware) = {
963 .name = "eth_designware",
964 .id = UCLASS_ETH,
965 .of_match = designware_eth_ids,
966 .of_to_plat = designware_eth_of_to_plat,
967 .bind = designware_eth_bind,
968 .probe = designware_eth_probe,
969 .remove = designware_eth_remove,
970 .ops = &designware_eth_ops,
971 .priv_auto = sizeof(struct dw_eth_dev),
972 .plat_auto = sizeof(struct dw_eth_pdata),
973 .flags = DM_FLAG_ALLOC_PRIV_DMA,
974 };
975
976 static struct pci_device_id supported[] = {
977 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
978 { }
979 };
980
981 U_BOOT_PCI_DEVICE(eth_designware, supported);
982 #endif
983