1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Faraday FTGMAC100 Ethernet 4 * 5 * (C) Copyright 2010 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 * 8 * (C) Copyright 2010 Andes Technology 9 * Macpaul Lin <macpaul@andestech.com> 10 */ 11 12 #ifndef __FTGMAC100_H 13 #define __FTGMAC100_H 14 15 /* The registers offset table of ftgmac100 */ 16 #include <linux/bitops.h> 17 struct ftgmac100 { 18 unsigned int isr; /* 0x00 */ 19 unsigned int ier; /* 0x04 */ 20 unsigned int mac_madr; /* 0x08 */ 21 unsigned int mac_ladr; /* 0x0c */ 22 unsigned int maht0; /* 0x10 */ 23 unsigned int maht1; /* 0x14 */ 24 unsigned int txpd; /* 0x18 */ 25 unsigned int rxpd; /* 0x1c */ 26 unsigned int txr_badr; /* 0x20 */ 27 unsigned int rxr_badr; /* 0x24 */ 28 unsigned int hptxpd; /* 0x28 */ 29 unsigned int hptxpd_badr; /* 0x2c */ 30 unsigned int itc; /* 0x30 */ 31 unsigned int aptc; /* 0x34 */ 32 unsigned int dblac; /* 0x38 */ 33 unsigned int dmafifos; /* 0x3c */ 34 unsigned int revr; /* 0x40 */ 35 unsigned int fear; /* 0x44 */ 36 unsigned int tpafcr; /* 0x48 */ 37 unsigned int rbsr; /* 0x4c */ 38 unsigned int maccr; /* 0x50 */ 39 unsigned int macsr; /* 0x54 */ 40 unsigned int tm; /* 0x58 */ 41 unsigned int resv1; /* 0x5c */ /* not defined in spec */ 42 unsigned int phycr; /* 0x60 */ 43 unsigned int phydata; /* 0x64 */ 44 unsigned int fcr; /* 0x68 */ 45 unsigned int bpr; /* 0x6c */ 46 unsigned int wolcr; /* 0x70 */ 47 unsigned int wolsr; /* 0x74 */ 48 unsigned int wfcrc; /* 0x78 */ 49 unsigned int resv2; /* 0x7c */ /* not defined in spec */ 50 unsigned int wfbm1; /* 0x80 */ 51 unsigned int wfbm2; /* 0x84 */ 52 unsigned int wfbm3; /* 0x88 */ 53 unsigned int wfbm4; /* 0x8c */ 54 unsigned int nptxr_ptr; /* 0x90 */ 55 unsigned int hptxr_ptr; /* 0x94 */ 56 unsigned int rxr_ptr; /* 0x98 */ 57 unsigned int resv3; /* 0x9c */ /* not defined in spec */ 58 unsigned int tx; /* 0xa0 */ 59 unsigned int tx_mcol_scol; /* 0xa4 */ 60 unsigned int tx_ecol_fail; /* 0xa8 */ 61 unsigned int tx_lcol_und; /* 0xac */ 62 unsigned int rx; /* 0xb0 */ 63 unsigned int rx_bc; /* 0xb4 */ 64 unsigned int rx_mc; /* 0xb8 */ 65 unsigned int rx_pf_aep; /* 0xbc */ 66 unsigned int rx_runt; /* 0xc0 */ 67 unsigned int rx_crcer_ftl; /* 0xc4 */ 68 unsigned int rx_col_lost; /* 0xc8 */ 69 }; 70 71 /* 72 * Interrupt status register & interrupt enable register 73 */ 74 #define FTGMAC100_INT_RPKT_BUF BIT(0) 75 #define FTGMAC100_INT_RPKT_FIFO BIT(1) 76 #define FTGMAC100_INT_NO_RXBUF BIT(2) 77 #define FTGMAC100_INT_RPKT_LOST BIT(3) 78 #define FTGMAC100_INT_XPKT_ETH BIT(4) 79 #define FTGMAC100_INT_XPKT_FIFO BIT(5) 80 #define FTGMAC100_INT_NO_NPTXBUF BIT(6) 81 #define FTGMAC100_INT_XPKT_LOST BIT(7) 82 #define FTGMAC100_INT_AHB_ERR BIT(8) 83 #define FTGMAC100_INT_PHYSTS_CHG BIT(9) 84 #define FTGMAC100_INT_NO_HPTXBUF BIT(10) 85 86 /* 87 * Interrupt timer control register 88 */ 89 #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 90 #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 91 #define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) 92 #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 93 #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 94 #define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) 95 96 /* 97 * Automatic polling timer control register 98 */ 99 #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 100 #define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) 101 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 102 #define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) 103 104 /* 105 * DMA burst length and arbitration control register 106 */ 107 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) 108 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) 109 #define FTGMAC100_DBLAC_RX_THR_EN BIT(6) 110 #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) 111 #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) 112 #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) 113 #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) 114 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) 115 #define FTGMAC100_DBLAC_IFG_INC BIT(23) 116 117 /* 118 * DMA FIFO status register 119 */ 120 #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) 121 #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) 122 #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) 123 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) 124 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) 125 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) 126 #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) 127 #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) 128 #define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) 129 #define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) 130 #define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) 131 #define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) 132 133 /* 134 * Receive buffer size register 135 */ 136 #define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) 137 138 /* 139 * MAC control register 140 */ 141 #define FTGMAC100_MACCR_TXDMA_EN BIT(0) 142 #define FTGMAC100_MACCR_RXDMA_EN BIT(1) 143 #define FTGMAC100_MACCR_TXMAC_EN BIT(2) 144 #define FTGMAC100_MACCR_RXMAC_EN BIT(3) 145 #define FTGMAC100_MACCR_RM_VLAN BIT(4) 146 #define FTGMAC100_MACCR_HPTXR_EN BIT(5) 147 #define FTGMAC100_MACCR_LOOP_EN BIT(6) 148 #define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) 149 #define FTGMAC100_MACCR_FULLDUP BIT(8) 150 #define FTGMAC100_MACCR_GIGA_MODE BIT(9) 151 #define FTGMAC100_MACCR_CRC_APD BIT(10) 152 #define FTGMAC100_MACCR_RX_RUNT BIT(12) 153 #define FTGMAC100_MACCR_JUMBO_LF BIT(13) 154 #define FTGMAC100_MACCR_RX_ALL BIT(14) 155 #define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) 156 #define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) 157 #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) 158 #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) 159 #define FTGMAC100_MACCR_FAST_MODE BIT(19) 160 #define FTGMAC100_MACCR_SW_RST BIT(31) 161 162 /* 163 * PHY control register 164 */ 165 #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f 166 #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) 167 #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 168 #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 169 #define FTGMAC100_PHYCR_MIIRD BIT(26) 170 #define FTGMAC100_PHYCR_MIIWR BIT(27) 171 172 /* 173 * PHY data register 174 */ 175 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 176 #define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) 177 178 /* 179 * Transmit descriptor, aligned to 16 bytes 180 */ 181 struct ftgmac100_txdes { 182 unsigned int txdes0; 183 unsigned int txdes1; 184 unsigned int txdes2; /* not used by HW */ 185 unsigned int txdes3; /* TXBUF_BADR */ 186 } __aligned(16); 187 188 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 189 #define FTGMAC100_TXDES0_EDOTR BIT(15) 190 #define FTGMAC100_TXDES0_CRC_ERR BIT(19) 191 #define FTGMAC100_TXDES0_LTS BIT(28) 192 #define FTGMAC100_TXDES0_FTS BIT(29) 193 #define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) 194 195 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 196 #define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) 197 #define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) 198 #define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) 199 #define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) 200 #define FTGMAC100_TXDES1_LLC BIT(22) 201 #define FTGMAC100_TXDES1_TX2FIC BIT(30) 202 #define FTGMAC100_TXDES1_TXIC BIT(31) 203 204 /* 205 * Receive descriptor, aligned to 16 bytes 206 */ 207 struct ftgmac100_rxdes { 208 unsigned int rxdes0; 209 unsigned int rxdes1; 210 unsigned int rxdes2; /* not used by HW */ 211 unsigned int rxdes3; /* RXBUF_BADR */ 212 } __aligned(16); 213 214 #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) 215 #define FTGMAC100_RXDES0_EDORR BIT(15) 216 #define FTGMAC100_RXDES0_MULTICAST BIT(16) 217 #define FTGMAC100_RXDES0_BROADCAST BIT(17) 218 #define FTGMAC100_RXDES0_RX_ERR BIT(18) 219 #define FTGMAC100_RXDES0_CRC_ERR BIT(19) 220 #define FTGMAC100_RXDES0_FTL BIT(20) 221 #define FTGMAC100_RXDES0_RUNT BIT(21) 222 #define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) 223 #define FTGMAC100_RXDES0_FIFO_FULL BIT(23) 224 #define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) 225 #define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) 226 #define FTGMAC100_RXDES0_LRS BIT(28) 227 #define FTGMAC100_RXDES0_FRS BIT(29) 228 #define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) 229 230 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 231 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 232 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 233 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 234 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 235 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 236 #define FTGMAC100_RXDES1_LLC BIT(22) 237 #define FTGMAC100_RXDES1_DF BIT(23) 238 #define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) 239 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) 240 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) 241 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) 242 243 #endif /* __FTGMAC100_H */ 244