1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 *
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <memalign.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <asm/cache.h>
18 #include <asm/io.h>
19 #include <pci.h>
20 #include <linux/delay.h>
21
22 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
23
24 #define PCNET_DEBUG1(fmt,args...) \
25 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
26 #define PCNET_DEBUG2(fmt,args...) \
27 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
28
29 /*
30 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
31 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
32 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
33 */
34 #define PCNET_LOG_TX_BUFFERS 0
35 #define PCNET_LOG_RX_BUFFERS 2
36
37 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
38 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
39
40 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
41 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
42
43 #define PKT_BUF_SZ 1544
44
45 /* The PCNET Rx and Tx ring descriptors. */
46 struct pcnet_rx_head {
47 u32 base;
48 s16 buf_length;
49 s16 status;
50 u32 msg_length;
51 u32 reserved;
52 };
53
54 struct pcnet_tx_head {
55 u32 base;
56 s16 length;
57 s16 status;
58 u32 misc;
59 u32 reserved;
60 };
61
62 /* The PCNET 32-Bit initialization block, described in databook. */
63 struct pcnet_init_block {
64 u16 mode;
65 u16 tlen_rlen;
66 u8 phys_addr[6];
67 u16 reserved;
68 u32 filter[2];
69 /* Receive and transmit ring base, along with extra bits. */
70 u32 rx_ring;
71 u32 tx_ring;
72 u32 reserved2;
73 };
74
75 struct pcnet_uncached_priv {
76 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
77 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
78 struct pcnet_init_block init_block;
79 } __aligned(ARCH_DMA_MINALIGN);
80
81 struct pcnet_priv {
82 struct pcnet_uncached_priv ucp;
83 /* Receive Buffer space */
84 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
85 struct pcnet_uncached_priv *uc;
86 #ifdef CONFIG_DM_ETH
87 struct udevice *dev;
88 const char *name;
89 #else
90 pci_dev_t dev;
91 char *name;
92 #endif
93 void __iomem *iobase;
94 u8 *enetaddr;
95 u16 status;
96 int cur_rx;
97 int cur_tx;
98 };
99
100 /* Offsets from base I/O address for WIO mode */
101 #define PCNET_RDP 0x10
102 #define PCNET_RAP 0x12
103 #define PCNET_RESET 0x14
104 #define PCNET_BDP 0x16
105
pcnet_read_csr(struct pcnet_priv * lp,int index)106 static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
107 {
108 writew(index, lp->iobase + PCNET_RAP);
109 return readw(lp->iobase + PCNET_RDP);
110 }
111
pcnet_write_csr(struct pcnet_priv * lp,int index,u16 val)112 static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
113 {
114 writew(index, lp->iobase + PCNET_RAP);
115 writew(val, lp->iobase + PCNET_RDP);
116 }
117
pcnet_read_bcr(struct pcnet_priv * lp,int index)118 static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
119 {
120 writew(index, lp->iobase + PCNET_RAP);
121 return readw(lp->iobase + PCNET_BDP);
122 }
123
pcnet_write_bcr(struct pcnet_priv * lp,int index,u16 val)124 static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
125 {
126 writew(index, lp->iobase + PCNET_RAP);
127 writew(val, lp->iobase + PCNET_BDP);
128 }
129
pcnet_reset(struct pcnet_priv * lp)130 static void pcnet_reset(struct pcnet_priv *lp)
131 {
132 readw(lp->iobase + PCNET_RESET);
133 }
134
pcnet_check(struct pcnet_priv * lp)135 static int pcnet_check(struct pcnet_priv *lp)
136 {
137 writew(88, lp->iobase + PCNET_RAP);
138 return readw(lp->iobase + PCNET_RAP) == 88;
139 }
140
pcnet_virt_to_mem(struct pcnet_priv * lp,void * addr)141 static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
142 {
143 void *virt_addr = addr;
144
145 #ifdef CONFIG_DM_ETH
146 return dm_pci_virt_to_mem(lp->dev, virt_addr);
147 #else
148 return pci_virt_to_mem(lp->dev, virt_addr);
149 #endif
150 }
151
152 static struct pci_device_id supported[] = {
153 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
154 {}
155 };
156
pcnet_probe_common(struct pcnet_priv * lp)157 static int pcnet_probe_common(struct pcnet_priv *lp)
158 {
159 int chip_version;
160 char *chipname;
161 int i;
162
163 /* Reset the PCnet controller */
164 pcnet_reset(lp);
165
166 /* Check if register access is working */
167 if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
168 printf("%s: CSR register access check failed\n", lp->name);
169 return -1;
170 }
171
172 /* Identify the chip */
173 chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
174 if ((chip_version & 0xfff) != 0x003)
175 return -1;
176 chip_version = (chip_version >> 12) & 0xffff;
177 switch (chip_version) {
178 case 0x2621:
179 chipname = "PCnet/PCI II 79C970A"; /* PCI */
180 break;
181 case 0x2625:
182 chipname = "PCnet/FAST III 79C973"; /* PCI */
183 break;
184 case 0x2627:
185 chipname = "PCnet/FAST III 79C975"; /* PCI */
186 break;
187 default:
188 printf("%s: PCnet version %#x not supported\n",
189 lp->name, chip_version);
190 return -1;
191 }
192
193 PCNET_DEBUG1("AMD %s\n", chipname);
194
195 /*
196 * In most chips, after a chip reset, the ethernet address is read from
197 * the station address PROM at the base address and programmed into the
198 * "Physical Address Registers" CSR12-14.
199 */
200 for (i = 0; i < 3; i++) {
201 unsigned int val;
202
203 val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
204 /* There may be endianness issues here. */
205 lp->enetaddr[2 * i] = val & 0x0ff;
206 lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
207 }
208
209 return 0;
210 }
211
pcnet_init_common(struct pcnet_priv * lp)212 static int pcnet_init_common(struct pcnet_priv *lp)
213 {
214 struct pcnet_uncached_priv *uc;
215 int i, val;
216 unsigned long addr;
217
218 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
219
220 /* Switch pcnet to 32bit mode */
221 pcnet_write_bcr(lp, 20, 2);
222
223 /* Set/reset autoselect bit */
224 val = pcnet_read_bcr(lp, 2) & ~2;
225 val |= 2;
226 pcnet_write_bcr(lp, 2, val);
227
228 /* Enable auto negotiate, setup, disable fd */
229 val = pcnet_read_bcr(lp, 32) & ~0x98;
230 val |= 0x20;
231 pcnet_write_bcr(lp, 32, val);
232
233 /*
234 * Enable NOUFLO on supported controllers, with the transmit
235 * start point set to the full packet. This will cause entire
236 * packets to be buffered by the ethernet controller before
237 * transmission, eliminating underflows which are common on
238 * slower devices. Controllers which do not support NOUFLO will
239 * simply be left with a larger transmit FIFO threshold.
240 */
241 val = pcnet_read_bcr(lp, 18);
242 val |= 1 << 11;
243 pcnet_write_bcr(lp, 18, val);
244 val = pcnet_read_csr(lp, 80);
245 val |= 0x3 << 10;
246 pcnet_write_csr(lp, 80, val);
247
248 uc = lp->uc;
249
250 uc->init_block.mode = cpu_to_le16(0x0000);
251 uc->init_block.filter[0] = 0x00000000;
252 uc->init_block.filter[1] = 0x00000000;
253
254 /*
255 * Initialize the Rx ring.
256 */
257 lp->cur_rx = 0;
258 for (i = 0; i < RX_RING_SIZE; i++) {
259 addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
260 uc->rx_ring[i].base = cpu_to_le32(addr);
261 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
262 uc->rx_ring[i].status = cpu_to_le16(0x8000);
263 PCNET_DEBUG1
264 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
265 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
266 uc->rx_ring[i].status);
267 }
268
269 /*
270 * Initialize the Tx ring. The Tx buffer address is filled in as
271 * needed, but we do need to clear the upper ownership bit.
272 */
273 lp->cur_tx = 0;
274 for (i = 0; i < TX_RING_SIZE; i++) {
275 uc->tx_ring[i].base = 0;
276 uc->tx_ring[i].status = 0;
277 }
278
279 /*
280 * Setup Init Block.
281 */
282 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
283
284 for (i = 0; i < 6; i++) {
285 lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
286 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
287 }
288
289 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
290 RX_RING_LEN_BITS);
291 addr = pcnet_virt_to_mem(lp, uc->rx_ring);
292 uc->init_block.rx_ring = cpu_to_le32(addr);
293 addr = pcnet_virt_to_mem(lp, uc->tx_ring);
294 uc->init_block.tx_ring = cpu_to_le32(addr);
295
296 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
297 uc->init_block.tlen_rlen,
298 uc->init_block.rx_ring, uc->init_block.tx_ring);
299
300 /*
301 * Tell the controller where the Init Block is located.
302 */
303 barrier();
304 addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
305 pcnet_write_csr(lp, 1, addr & 0xffff);
306 pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
307
308 pcnet_write_csr(lp, 4, 0x0915);
309 pcnet_write_csr(lp, 0, 0x0001); /* start */
310
311 /* Wait for Init Done bit */
312 for (i = 10000; i > 0; i--) {
313 if (pcnet_read_csr(lp, 0) & 0x0100)
314 break;
315 udelay(10);
316 }
317 if (i <= 0) {
318 printf("%s: TIMEOUT: controller init failed\n", lp->name);
319 pcnet_reset(lp);
320 return -1;
321 }
322
323 /*
324 * Finally start network controller operation.
325 */
326 pcnet_write_csr(lp, 0, 0x0002);
327
328 return 0;
329 }
330
pcnet_send_common(struct pcnet_priv * lp,void * packet,int pkt_len)331 static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
332 {
333 int i, status;
334 u32 addr;
335 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
336
337 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
338 packet);
339
340 flush_dcache_range((unsigned long)packet,
341 (unsigned long)packet + pkt_len);
342
343 /* Wait for completion by testing the OWN bit */
344 for (i = 1000; i > 0; i--) {
345 status = readw(&entry->status);
346 if ((status & 0x8000) == 0)
347 break;
348 udelay(100);
349 PCNET_DEBUG2(".");
350 }
351 if (i <= 0) {
352 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
353 lp->name, lp->cur_tx, status);
354 pkt_len = 0;
355 goto failure;
356 }
357
358 /*
359 * Setup Tx ring. Caution: the write order is important here,
360 * set the status with the "ownership" bits last.
361 */
362 addr = pcnet_virt_to_mem(lp, packet);
363 writew(-pkt_len, &entry->length);
364 writel(0, &entry->misc);
365 writel(addr, &entry->base);
366 writew(0x8300, &entry->status);
367
368 /* Trigger an immediate send poll. */
369 pcnet_write_csr(lp, 0, 0x0008);
370
371 failure:
372 if (++lp->cur_tx >= TX_RING_SIZE)
373 lp->cur_tx = 0;
374
375 PCNET_DEBUG2("done\n");
376 return pkt_len;
377 }
378
pcnet_recv_common(struct pcnet_priv * lp,unsigned char ** bufp)379 static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
380 {
381 struct pcnet_rx_head *entry;
382 unsigned char *buf;
383 int pkt_len = 0;
384 u16 err_status;
385
386 entry = &lp->uc->rx_ring[lp->cur_rx];
387 /*
388 * If we own the next entry, it's a new packet. Send it up.
389 */
390 lp->status = readw(&entry->status);
391 if ((lp->status & 0x8000) != 0)
392 return 0;
393 err_status = lp->status >> 8;
394
395 if (err_status != 0x03) { /* There was an error. */
396 printf("%s: Rx%d", lp->name, lp->cur_rx);
397 PCNET_DEBUG1(" (status=0x%x)", err_status);
398 if (err_status & 0x20)
399 printf(" Frame");
400 if (err_status & 0x10)
401 printf(" Overflow");
402 if (err_status & 0x08)
403 printf(" CRC");
404 if (err_status & 0x04)
405 printf(" Fifo");
406 printf(" Error\n");
407 lp->status &= 0x03ff;
408 return 0;
409 }
410
411 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
412 if (pkt_len < 60) {
413 printf("%s: Rx%d: invalid packet length %d\n",
414 lp->name, lp->cur_rx, pkt_len);
415 return 0;
416 }
417
418 *bufp = lp->rx_buf[lp->cur_rx];
419 invalidate_dcache_range((unsigned long)*bufp,
420 (unsigned long)*bufp + pkt_len);
421
422 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
423 lp->cur_rx, pkt_len, buf);
424
425 return pkt_len;
426 }
427
pcnet_free_pkt_common(struct pcnet_priv * lp,unsigned int len)428 static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
429 {
430 struct pcnet_rx_head *entry;
431
432 entry = &lp->uc->rx_ring[lp->cur_rx];
433
434 lp->status |= 0x8000;
435 writew(lp->status, &entry->status);
436
437 if (++lp->cur_rx >= RX_RING_SIZE)
438 lp->cur_rx = 0;
439 }
440
pcnet_halt_common(struct pcnet_priv * lp)441 static void pcnet_halt_common(struct pcnet_priv *lp)
442 {
443 int i;
444
445 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
446
447 /* Reset the PCnet controller */
448 pcnet_reset(lp);
449
450 /* Wait for Stop bit */
451 for (i = 1000; i > 0; i--) {
452 if (pcnet_read_csr(lp, 0) & 0x4)
453 break;
454 udelay(10);
455 }
456 if (i <= 0)
457 printf("%s: TIMEOUT: controller reset failed\n", lp->name);
458 }
459
460 #ifndef CONFIG_DM_ETH
pcnet_init(struct eth_device * dev,struct bd_info * bis)461 static int pcnet_init(struct eth_device *dev, struct bd_info *bis)
462 {
463 struct pcnet_priv *lp = dev->priv;
464
465 return pcnet_init_common(lp);
466 }
467
pcnet_send(struct eth_device * dev,void * packet,int pkt_len)468 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
469 {
470 struct pcnet_priv *lp = dev->priv;
471
472 return pcnet_send_common(lp, packet, pkt_len);
473 }
474
pcnet_recv(struct eth_device * dev)475 static int pcnet_recv(struct eth_device *dev)
476 {
477 struct pcnet_priv *lp = dev->priv;
478 uchar *packet;
479 int ret;
480
481 ret = pcnet_recv_common(lp, &packet);
482 if (ret > 0)
483 net_process_received_packet(packet, ret);
484 if (ret)
485 pcnet_free_pkt_common(lp, ret);
486
487 return ret;
488 }
489
pcnet_halt(struct eth_device * dev)490 static void pcnet_halt(struct eth_device *dev)
491 {
492 struct pcnet_priv *lp = dev->priv;
493
494 pcnet_halt_common(lp);
495 }
496
pcnet_initialize(struct bd_info * bis)497 int pcnet_initialize(struct bd_info *bis)
498 {
499 pci_dev_t devbusfn;
500 struct eth_device *dev;
501 struct pcnet_priv *lp;
502 u16 command, status;
503 int dev_nr = 0;
504 u32 bar;
505
506 PCNET_DEBUG1("\n%s...\n", __func__);
507
508 for (dev_nr = 0; ; dev_nr++) {
509 /*
510 * Find the PCnet PCI device(s).
511 */
512 devbusfn = pci_find_devices(supported, dev_nr);
513 if (devbusfn < 0)
514 break;
515
516 /*
517 * Allocate and pre-fill the device structure.
518 */
519 dev = calloc(1, sizeof(*dev));
520 if (!dev) {
521 printf("pcnet: Can not allocate memory\n");
522 break;
523 }
524
525 /*
526 * We only maintain one structure because the drivers will
527 * never be used concurrently. In 32bit mode the RX and TX
528 * ring entries must be aligned on 16-byte boundaries.
529 */
530 lp = malloc_cache_aligned(sizeof(*lp));
531 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
532 sizeof(lp->ucp), MAP_NOCACHE);
533 lp->dev = devbusfn;
534 flush_dcache_range((unsigned long)lp,
535 (unsigned long)lp + sizeof(*lp));
536 dev->priv = lp;
537 sprintf(dev->name, "pcnet#%d", dev_nr);
538 lp->name = dev->name;
539 lp->enetaddr = dev->enetaddr;
540
541 /*
542 * Setup the PCI device.
543 */
544 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
545 lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
546
547 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
548 lp->name, devbusfn, lp->iobase);
549
550 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
551 pci_write_config_word(devbusfn, PCI_COMMAND, command);
552 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
553 if ((status & command) != command) {
554 printf("%s: Couldn't enable IO access or Bus Mastering\n",
555 lp->name);
556 free(dev);
557 continue;
558 }
559
560 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
561
562 /*
563 * Probe the PCnet chip.
564 */
565 if (pcnet_probe_common(lp) < 0) {
566 free(dev);
567 continue;
568 }
569
570 /*
571 * Setup device structure and register the driver.
572 */
573 dev->init = pcnet_init;
574 dev->halt = pcnet_halt;
575 dev->send = pcnet_send;
576 dev->recv = pcnet_recv;
577
578 eth_register(dev);
579 }
580
581 udelay(10 * 1000);
582
583 return dev_nr;
584 }
585 #else /* DM_ETH */
pcnet_start(struct udevice * dev)586 static int pcnet_start(struct udevice *dev)
587 {
588 struct eth_pdata *plat = dev_get_plat(dev);
589 struct pcnet_priv *priv = dev_get_priv(dev);
590
591 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
592
593 return pcnet_init_common(priv);
594 }
595
pcnet_stop(struct udevice * dev)596 static void pcnet_stop(struct udevice *dev)
597 {
598 struct pcnet_priv *priv = dev_get_priv(dev);
599
600 pcnet_halt_common(priv);
601 }
602
pcnet_send(struct udevice * dev,void * packet,int length)603 static int pcnet_send(struct udevice *dev, void *packet, int length)
604 {
605 struct pcnet_priv *priv = dev_get_priv(dev);
606 int ret;
607
608 ret = pcnet_send_common(priv, packet, length);
609
610 return ret ? 0 : -ETIMEDOUT;
611 }
612
pcnet_recv(struct udevice * dev,int flags,uchar ** packetp)613 static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
614 {
615 struct pcnet_priv *priv = dev_get_priv(dev);
616
617 return pcnet_recv_common(priv, packetp);
618 }
619
pcnet_free_pkt(struct udevice * dev,uchar * packet,int length)620 static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
621 {
622 struct pcnet_priv *priv = dev_get_priv(dev);
623
624 pcnet_free_pkt_common(priv, length);
625
626 return 0;
627 }
628
pcnet_bind(struct udevice * dev)629 static int pcnet_bind(struct udevice *dev)
630 {
631 static int card_number;
632 char name[16];
633
634 sprintf(name, "pcnet#%u", card_number++);
635
636 return device_set_name(dev, name);
637 }
638
pcnet_probe(struct udevice * dev)639 static int pcnet_probe(struct udevice *dev)
640 {
641 struct eth_pdata *plat = dev_get_plat(dev);
642 struct pcnet_priv *lp = dev_get_priv(dev);
643 u16 command, status;
644 u32 iobase;
645 int ret;
646
647 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
648 iobase &= ~0xf;
649
650 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
651 sizeof(lp->ucp), MAP_NOCACHE);
652 lp->dev = dev;
653 lp->name = dev->name;
654 lp->enetaddr = plat->enetaddr;
655 lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
656
657 flush_dcache_range((unsigned long)lp,
658 (unsigned long)lp + sizeof(*lp));
659
660 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
661 dm_pci_write_config16(dev, PCI_COMMAND, command);
662 dm_pci_read_config16(dev, PCI_COMMAND, &status);
663 if ((status & command) != command) {
664 printf("%s: Couldn't enable IO access or Bus Mastering\n",
665 lp->name);
666 return -EINVAL;
667 }
668
669 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
670
671 ret = pcnet_probe_common(lp);
672 if (ret)
673 return ret;
674
675 return 0;
676 }
677
678 static const struct eth_ops pcnet_ops = {
679 .start = pcnet_start,
680 .send = pcnet_send,
681 .recv = pcnet_recv,
682 .stop = pcnet_stop,
683 .free_pkt = pcnet_free_pkt,
684 };
685
686 U_BOOT_DRIVER(eth_pcnet) = {
687 .name = "eth_pcnet",
688 .id = UCLASS_ETH,
689 .bind = pcnet_bind,
690 .probe = pcnet_probe,
691 .ops = &pcnet_ops,
692 .priv_auto = sizeof(struct pcnet_priv),
693 .plat_auto = sizeof(struct eth_pdata),
694 .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
695 };
696
697 U_BOOT_PCI_DEVICE(eth_pcnet, supported);
698 #endif
699