1 // SPDX-License-Identifier: GPL-2.0+
2 /*------------------------------------------------------------------------
3 . smc91111.c
4 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
5 .
6 . (C) Copyright 2002
7 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 . Rolf Offermanns <rof@sysgo.de>
9 .
10 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
11 . Developed by Simple Network Magic Corporation (SNMC)
12 . Copyright (C) 1996 by Erik Stahlman (ES)
13 .
14 .
15 . Information contained in this file was obtained from the LAN91C111
16 . manual from SMC. To get a copy, if you really want one, you can find
17 . information under www.smsc.com.
18 .
19 .
20 . "Features" of the SMC chip:
21 . Integrated PHY/MAC for 10/100BaseT Operation
22 . Supports internal and external MII
23 . Integrated 8K packet memory
24 . EEPROM interface for configuration
25 .
26 . Arguments:
27 . io = for the base address
28 . irq = for the IRQ
29 .
30 . author:
31 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
33 .
34 .
35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
36 .
37 . Sources:
38 . o SMSC LAN91C111 databook (www.smsc.com)
39 . o smc9194.c by Erik Stahlman
40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
41 .
42 . History:
43 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
44 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
45 . 07/25/01 Woojung Huh Modify for ADS Bitsy
46 . 04/25/01 Daris A Nevil Initial public release through SMSC
47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
48 ----------------------------------------------------------------------------*/
49
50 #include <common.h>
51 #include <command.h>
52 #include <config.h>
53 #include <malloc.h>
54 #include <linux/delay.h>
55 #include "smc91111.h"
56 #include <net.h>
57
58 /* Use power-down feature of the chip */
59 #define POWER_DOWN 0
60
61 #define NO_AUTOPROBE
62
63 #define SMC_DEBUG 0
64
65 #if SMC_DEBUG > 1
66 static const char version[] =
67 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
68 #endif
69
70 /* Autonegotiation timeout in seconds */
71 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
72 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
73 #endif
74
75 /*------------------------------------------------------------------------
76 .
77 . Configuration options, for the experienced user to change.
78 .
79 -------------------------------------------------------------------------*/
80
81 /*
82 . Wait time for memory to be free. This probably shouldn't be
83 . tuned that much, as waiting for this means nothing else happens
84 . in the system
85 */
86 #define MEMORY_WAIT_TIME 16
87
88
89 #if (SMC_DEBUG > 2 )
90 #define PRINTK3(args...) printf(args)
91 #else
92 #define PRINTK3(args...)
93 #endif
94
95 #if SMC_DEBUG > 1
96 #define PRINTK2(args...) printf(args)
97 #else
98 #define PRINTK2(args...)
99 #endif
100
101 #ifdef SMC_DEBUG
102 #define PRINTK(args...) printf(args)
103 #else
104 #define PRINTK(args...)
105 #endif
106
107
108 /*------------------------------------------------------------------------
109 .
110 . The internal workings of the driver. If you are changing anything
111 . here with the SMC stuff, you should have the datasheet and know
112 . what you are doing.
113 .
114 -------------------------------------------------------------------------*/
115
116 /* Memory sizing constant */
117 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
118
119 #ifndef CONFIG_SMC91111_BASE
120 #error "SMC91111 Base address must be passed to initialization funciton"
121 /* #define CONFIG_SMC91111_BASE 0x20000300 */
122 #endif
123
124 #define SMC_DEV_NAME "SMC91111"
125 #define SMC_PHY_ADDR 0x0000
126 #define SMC_ALLOC_MAX_TRY 5
127 #define SMC_TX_TIMEOUT 30
128
129 #define SMC_PHY_CLOCK_DELAY 1000
130
131 #define ETH_ZLEN 60
132
133 #ifdef CONFIG_SMC_USE_32_BIT
134 #define USE_32_BIT 1
135 #else
136 #undef USE_32_BIT
137 #endif
138
139 #ifdef SHARED_RESOURCES
140 extern void swap_to(int device_id);
141 #else
142 # define swap_to(x)
143 #endif
144
145 #ifndef CONFIG_SMC91111_EXT_PHY
146 static void smc_phy_configure(struct eth_device *dev);
147 #endif /* !CONFIG_SMC91111_EXT_PHY */
148
149 /*
150 ------------------------------------------------------------
151 .
152 . Internal routines
153 .
154 ------------------------------------------------------------
155 */
156
157 #ifdef CONFIG_SMC_USE_IOFUNCS
158 /*
159 * input and output functions
160 *
161 * Implemented due to inx,outx macros accessing the device improperly
162 * and putting the device into an unkown state.
163 *
164 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
165 * could not be free'd (hence the alloc failures), duplicate packets,
166 * packets being corrupt (shifted) on the wire, etc. Switching to the
167 * inx,outx functions fixed this problem.
168 */
169
SMC_inw(struct eth_device * dev,dword offset)170 static inline word SMC_inw(struct eth_device *dev, dword offset)
171 {
172 word v;
173 v = *((volatile word*)(dev->iobase + offset));
174 barrier(); *(volatile u32*)(0xc0000000);
175 return v;
176 }
177
SMC_outw(struct eth_device * dev,word value,dword offset)178 static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
179 {
180 *((volatile word*)(dev->iobase + offset)) = value;
181 barrier(); *(volatile u32*)(0xc0000000);
182 }
183
SMC_inb(struct eth_device * dev,dword offset)184 static inline byte SMC_inb(struct eth_device *dev, dword offset)
185 {
186 word _w;
187
188 _w = SMC_inw(dev, offset & ~((dword)1));
189 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
190 }
191
SMC_outb(struct eth_device * dev,byte value,dword offset)192 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
193 {
194 word _w;
195
196 _w = SMC_inw(dev, offset & ~((dword)1));
197 if (offset & 1)
198 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
199 (value<<8) | (_w & 0x00ff);
200 else
201 *((volatile word*)(dev->iobase + offset)) =
202 value | (_w & 0xff00);
203 }
204
SMC_insw(struct eth_device * dev,dword offset,volatile uchar * buf,dword len)205 static inline void SMC_insw(struct eth_device *dev, dword offset,
206 volatile uchar* buf, dword len)
207 {
208 volatile word *p = (volatile word *)buf;
209
210 while (len-- > 0) {
211 *p++ = SMC_inw(dev, offset);
212 barrier();
213 *((volatile u32*)(0xc0000000));
214 }
215 }
216
SMC_outsw(struct eth_device * dev,dword offset,uchar * buf,dword len)217 static inline void SMC_outsw(struct eth_device *dev, dword offset,
218 uchar* buf, dword len)
219 {
220 volatile word *p = (volatile word *)buf;
221
222 while (len-- > 0) {
223 SMC_outw(dev, *p++, offset);
224 barrier();
225 *(volatile u32*)(0xc0000000);
226 }
227 }
228 #endif /* CONFIG_SMC_USE_IOFUNCS */
229
230 /*
231 . A rather simple routine to print out a packet for debugging purposes.
232 */
233 #if SMC_DEBUG > 2
234 static void print_packet( byte *, int );
235 #endif
236
237 #define tx_done(dev) 1
238
poll4int(struct eth_device * dev,byte mask,int timeout)239 static int poll4int (struct eth_device *dev, byte mask, int timeout)
240 {
241 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
242 int is_timeout = 0;
243 word old_bank = SMC_inw (dev, BSR_REG);
244
245 PRINTK2 ("Polling...\n");
246 SMC_SELECT_BANK (dev, 2);
247 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
248 if (get_timer (0) >= tmo) {
249 is_timeout = 1;
250 break;
251 }
252 }
253
254 /* restore old bank selection */
255 SMC_SELECT_BANK (dev, old_bank);
256
257 if (is_timeout)
258 return 1;
259 else
260 return 0;
261 }
262
263 /* Only one release command at a time, please */
smc_wait_mmu_release_complete(struct eth_device * dev)264 static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
265 {
266 int count = 0;
267
268 /* assume bank 2 selected */
269 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
270 udelay(1); /* Wait until not busy */
271 if (++count > 200)
272 break;
273 }
274 }
275
276 /*
277 . Function: smc_reset( void )
278 . Purpose:
279 . This sets the SMC91111 chip to its normal state, hopefully from whatever
280 . mess that any other DOS driver has put it in.
281 .
282 . Maybe I should reset more registers to defaults in here? SOFTRST should
283 . do that for me.
284 .
285 . Method:
286 . 1. send a SOFT RESET
287 . 2. wait for it to finish
288 . 3. enable autorelease mode
289 . 4. reset the memory management unit
290 . 5. clear all interrupts
291 .
292 */
smc_reset(struct eth_device * dev)293 static void smc_reset (struct eth_device *dev)
294 {
295 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
296
297 /* This resets the registers mostly to defaults, but doesn't
298 affect EEPROM. That seems unnecessary */
299 SMC_SELECT_BANK (dev, 0);
300 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
301
302 /* Setup the Configuration Register */
303 /* This is necessary because the CONFIG_REG is not affected */
304 /* by a soft reset */
305
306 SMC_SELECT_BANK (dev, 1);
307 #if defined(CONFIG_SMC91111_EXT_PHY)
308 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
309 #else
310 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
311 #endif
312
313
314 /* Release from possible power-down state */
315 /* Configuration register is not affected by Soft Reset */
316 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
317 CONFIG_REG);
318
319 SMC_SELECT_BANK (dev, 0);
320
321 /* this should pause enough for the chip to be happy */
322 udelay(10);
323
324 /* Disable transmit and receive functionality */
325 SMC_outw (dev, RCR_CLEAR, RCR_REG);
326 SMC_outw (dev, TCR_CLEAR, TCR_REG);
327
328 /* set the control register */
329 SMC_SELECT_BANK (dev, 1);
330 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
331
332 /* Reset the MMU */
333 SMC_SELECT_BANK (dev, 2);
334 smc_wait_mmu_release_complete (dev);
335 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
336 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
337 udelay(1); /* Wait until not busy */
338
339 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
340 but this is a place where future chipsets _COULD_ break. Be wary
341 of issuing another MMU command right after this */
342
343 /* Disable all interrupts */
344 SMC_outb (dev, 0, IM_REG);
345 }
346
347 /*
348 . Function: smc_enable
349 . Purpose: let the chip talk to the outside work
350 . Method:
351 . 1. Enable the transmitter
352 . 2. Enable the receiver
353 . 3. Enable interrupts
354 */
smc_enable(struct eth_device * dev)355 static void smc_enable(struct eth_device *dev)
356 {
357 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
358 SMC_SELECT_BANK( dev, 0 );
359 /* see the header file for options in TCR/RCR DEFAULT*/
360 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
361 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
362
363 /* clear MII_DIS */
364 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
365 }
366
367 /*
368 . Function: smc_halt
369 . Purpose: closes down the SMC91xxx chip.
370 . Method:
371 . 1. zero the interrupt mask
372 . 2. clear the enable receive flag
373 . 3. clear the enable xmit flags
374 .
375 . TODO:
376 . (1) maybe utilize power down mode.
377 . Why not yet? Because while the chip will go into power down mode,
378 . the manual says that it will wake up in response to any I/O requests
379 . in the register space. Empirical results do not show this working.
380 */
smc_halt(struct eth_device * dev)381 static void smc_halt(struct eth_device *dev)
382 {
383 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
384
385 /* no more interrupts for me */
386 SMC_SELECT_BANK( dev, 2 );
387 SMC_outb( dev, 0, IM_REG );
388
389 /* and tell the card to stay away from that nasty outside world */
390 SMC_SELECT_BANK( dev, 0 );
391 SMC_outb( dev, RCR_CLEAR, RCR_REG );
392 SMC_outb( dev, TCR_CLEAR, TCR_REG );
393
394 swap_to(FLASH);
395 }
396
397
398 /*
399 . Function: smc_send(struct net_device * )
400 . Purpose:
401 . This sends the actual packet to the SMC9xxx chip.
402 .
403 . Algorithm:
404 . First, see if a saved_skb is available.
405 . ( this should NOT be called if there is no 'saved_skb'
406 . Now, find the packet number that the chip allocated
407 . Point the data pointers at it in memory
408 . Set the length word in the chip's memory
409 . Dump the packet to chip memory
410 . Check if a last byte is needed ( odd length packet )
411 . if so, set the control flag right
412 . Tell the card to send it
413 . Enable the transmit interrupt, so I know if it failed
414 . Free the kernel data if I actually sent it.
415 */
smc_send(struct eth_device * dev,void * packet,int packet_length)416 static int smc_send(struct eth_device *dev, void *packet, int packet_length)
417 {
418 byte packet_no;
419 byte *buf;
420 int length;
421 int numPages;
422 int try = 0;
423 int time_out;
424 byte status;
425 byte saved_pnr;
426 word saved_ptr;
427
428 /* save PTR and PNR registers before manipulation */
429 SMC_SELECT_BANK (dev, 2);
430 saved_pnr = SMC_inb( dev, PN_REG );
431 saved_ptr = SMC_inw( dev, PTR_REG );
432
433 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
434
435 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
436
437 /* allocate memory
438 ** The MMU wants the number of pages to be the number of 256 bytes
439 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
440 **
441 ** The 91C111 ignores the size bits, but the code is left intact
442 ** for backwards and future compatibility.
443 **
444 ** Pkt size for allocating is data length +6 (for additional status
445 ** words, length and ctl!)
446 **
447 ** If odd size then last byte is included in this header.
448 */
449 numPages = ((length & 0xfffe) + 6);
450 numPages >>= 8; /* Divide by 256 */
451
452 if (numPages > 7) {
453 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
454 return 0;
455 }
456
457 /* now, try to allocate the memory */
458 SMC_SELECT_BANK (dev, 2);
459 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
460
461 /* FIXME: the ALLOC_INT bit never gets set *
462 * so the following will always give a *
463 * memory allocation error. *
464 * same code works in armboot though *
465 * -ro
466 */
467
468 again:
469 try++;
470 time_out = MEMORY_WAIT_TIME;
471 do {
472 status = SMC_inb (dev, SMC91111_INT_REG);
473 if (status & IM_ALLOC_INT) {
474 /* acknowledge the interrupt */
475 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
476 break;
477 }
478 } while (--time_out);
479
480 if (!time_out) {
481 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
482 SMC_DEV_NAME, try);
483 if (try < SMC_ALLOC_MAX_TRY)
484 goto again;
485 else
486 return 0;
487 }
488
489 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
490 SMC_DEV_NAME, try);
491
492 buf = (byte *) packet;
493
494 /* If I get here, I _know_ there is a packet slot waiting for me */
495 packet_no = SMC_inb (dev, AR_REG);
496 if (packet_no & AR_FAILED) {
497 /* or isn't there? BAD CHIP! */
498 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
499 return 0;
500 }
501
502 /* we have a packet address, so tell the card to use it */
503 SMC_outb (dev, packet_no, PN_REG);
504
505 /* do not write new ptr value if Write data fifo not empty */
506 while ( saved_ptr & PTR_NOTEMPTY )
507 printf ("Write data fifo not empty!\n");
508
509 /* point to the beginning of the packet */
510 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
511
512 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
513 SMC_DEV_NAME, length);
514
515 #if SMC_DEBUG > 2
516 printf ("Transmitting Packet\n");
517 print_packet (buf, length);
518 #endif
519
520 /* send the packet length ( +6 for status, length and ctl byte )
521 and the status word ( set to zeros ) */
522 #ifdef USE_32_BIT
523 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
524 #else
525 SMC_outw (dev, 0, SMC91111_DATA_REG);
526 /* send the packet length ( +6 for status words, length, and ctl */
527 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
528 #endif
529
530 /* send the actual data
531 . I _think_ it's faster to send the longs first, and then
532 . mop up by sending the last word. It depends heavily
533 . on alignment, at least on the 486. Maybe it would be
534 . a good idea to check which is optimal? But that could take
535 . almost as much time as is saved?
536 */
537 #ifdef USE_32_BIT
538 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
539 if (length & 0x2)
540 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
541 SMC91111_DATA_REG);
542 #else
543 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
544 #endif /* USE_32_BIT */
545
546 /* Send the last byte, if there is one. */
547 if ((length & 1) == 0) {
548 SMC_outw (dev, 0, SMC91111_DATA_REG);
549 } else {
550 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
551 }
552
553 /* and let the chipset deal with it */
554 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
555
556 /* poll for TX INT */
557 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
558 /* poll for TX_EMPTY INT - autorelease enabled */
559 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
560 /* sending failed */
561 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
562
563 /* release packet */
564 /* no need to release, MMU does that now */
565
566 /* wait for MMU getting ready (low) */
567 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
568 udelay(10);
569 }
570
571 PRINTK2 ("MMU ready\n");
572
573
574 return 0;
575 } else {
576 /* ack. int */
577 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
578 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
579 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
580 length);
581
582 /* release packet */
583 /* no need to release, MMU does that now */
584
585 /* wait for MMU getting ready (low) */
586 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
587 udelay(10);
588 }
589
590 PRINTK2 ("MMU ready\n");
591
592
593 }
594
595 /* restore previously saved registers */
596 SMC_outb( dev, saved_pnr, PN_REG );
597 SMC_outw( dev, saved_ptr, PTR_REG );
598
599 return length;
600 }
601
smc_write_hwaddr(struct eth_device * dev)602 static int smc_write_hwaddr(struct eth_device *dev)
603 {
604 int i;
605
606 swap_to(ETHERNET);
607 SMC_SELECT_BANK (dev, 1);
608 #ifdef USE_32_BIT
609 for (i = 0; i < 6; i += 2) {
610 word address;
611
612 address = dev->enetaddr[i + 1] << 8;
613 address |= dev->enetaddr[i];
614 SMC_outw(dev, address, (ADDR0_REG + i));
615 }
616 #else
617 for (i = 0; i < 6; i++)
618 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
619 #endif
620 swap_to(FLASH);
621 return 0;
622 }
623
624 /*
625 * Open and Initialize the board
626 *
627 * Set up everything, reset the card, etc ..
628 *
629 */
smc_init(struct eth_device * dev,struct bd_info * bd)630 static int smc_init(struct eth_device *dev, struct bd_info *bd)
631 {
632 swap_to(ETHERNET);
633
634 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
635
636 /* reset the hardware */
637 smc_reset (dev);
638 smc_enable (dev);
639
640 /* Configure the PHY */
641 #ifndef CONFIG_SMC91111_EXT_PHY
642 smc_phy_configure (dev);
643 #endif
644
645 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
646 /* SMC_SELECT_BANK(dev, 0); */
647 /* SMC_outw(dev, 0, RPC_REG); */
648
649 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
650
651 return 0;
652 }
653
654 /*-------------------------------------------------------------
655 .
656 . smc_rcv - receive a packet from the card
657 .
658 . There is ( at least ) a packet waiting to be read from
659 . chip-memory.
660 .
661 . o Read the status
662 . o If an error, record it
663 . o otherwise, read in the packet
664 --------------------------------------------------------------
665 */
smc_rcv(struct eth_device * dev)666 static int smc_rcv(struct eth_device *dev)
667 {
668 int packet_number;
669 word status;
670 word packet_length;
671 int is_error = 0;
672 #ifdef USE_32_BIT
673 dword stat_len;
674 #endif
675 byte saved_pnr;
676 word saved_ptr;
677
678 SMC_SELECT_BANK(dev, 2);
679 /* save PTR and PTR registers */
680 saved_pnr = SMC_inb( dev, PN_REG );
681 saved_ptr = SMC_inw( dev, PTR_REG );
682
683 packet_number = SMC_inw( dev, RXFIFO_REG );
684
685 if ( packet_number & RXFIFO_REMPTY ) {
686
687 return 0;
688 }
689
690 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
691 /* start reading from the start of the packet */
692 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
693
694 /* First two words are status and packet_length */
695 #ifdef USE_32_BIT
696 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
697 status = stat_len & 0xffff;
698 packet_length = stat_len >> 16;
699 #else
700 status = SMC_inw( dev, SMC91111_DATA_REG );
701 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
702 #endif
703
704 packet_length &= 0x07ff; /* mask off top bits */
705
706 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
707
708 if ( !(status & RS_ERRORS ) ){
709 /* Adjust for having already read the first two words */
710 packet_length -= 4; /*4; */
711
712
713 /* set odd length for bug in LAN91C111, */
714 /* which never sets RS_ODDFRAME */
715 /* TODO ? */
716
717
718 #ifdef USE_32_BIT
719 PRINTK3(" Reading %d dwords (and %d bytes)\n",
720 packet_length >> 2, packet_length & 3 );
721 /* QUESTION: Like in the TX routine, do I want
722 to send the DWORDs or the bytes first, or some
723 mixture. A mixture might improve already slow PIO
724 performance */
725 SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
726 packet_length >> 2);
727 /* read the left over bytes */
728 if (packet_length & 3) {
729 int i;
730
731 byte *tail = (byte *)(net_rx_packets[0] +
732 (packet_length & ~3));
733 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
734 for (i=0; i<(packet_length & 3); i++)
735 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
736 }
737 #else
738 PRINTK3(" Reading %d words and %d byte(s)\n",
739 (packet_length >> 1 ), packet_length & 1 );
740 SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
741 packet_length >> 1);
742
743 #endif /* USE_32_BIT */
744
745 #if SMC_DEBUG > 2
746 printf("Receiving Packet\n");
747 print_packet(net_rx_packets[0], packet_length);
748 #endif
749 } else {
750 /* error ... */
751 /* TODO ? */
752 is_error = 1;
753 }
754
755 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
756 udelay(1); /* Wait until not busy */
757
758 /* error or good, tell the card to get rid of this packet */
759 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
760
761 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
762 udelay(1); /* Wait until not busy */
763
764 /* restore saved registers */
765 SMC_outb( dev, saved_pnr, PN_REG );
766 SMC_outw( dev, saved_ptr, PTR_REG );
767
768 if (!is_error) {
769 /* Pass the packet up to the protocol layers. */
770 net_process_received_packet(net_rx_packets[0], packet_length);
771 return packet_length;
772 } else {
773 return 0;
774 }
775
776 }
777
778
779 #if 0
780 /*------------------------------------------------------------
781 . Modify a bit in the LAN91C111 register set
782 .-------------------------------------------------------------*/
783 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
784 unsigned int bit, int val)
785 {
786 word regval;
787
788 SMC_SELECT_BANK( dev, bank );
789
790 regval = SMC_inw( dev, reg );
791 if (val)
792 regval |= bit;
793 else
794 regval &= ~bit;
795
796 SMC_outw( dev, regval, 0 );
797 return(regval);
798 }
799
800
801 /*------------------------------------------------------------
802 . Retrieve a bit in the LAN91C111 register set
803 .-------------------------------------------------------------*/
804 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
805 {
806 SMC_SELECT_BANK( dev, bank );
807 if ( SMC_inw( dev, reg ) & bit)
808 return(1);
809 else
810 return(0);
811 }
812
813
814 /*------------------------------------------------------------
815 . Modify a LAN91C111 register (word access only)
816 .-------------------------------------------------------------*/
817 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
818 {
819 SMC_SELECT_BANK( dev, bank );
820 SMC_outw( dev, val, reg );
821 }
822
823
824 /*------------------------------------------------------------
825 . Retrieve a LAN91C111 register (word access only)
826 .-------------------------------------------------------------*/
827 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
828 {
829 SMC_SELECT_BANK( dev, bank );
830 return(SMC_inw( dev, reg ));
831 }
832
833 #endif /* 0 */
834
835 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
836
837 #if (SMC_DEBUG > 2 )
838
839 /*------------------------------------------------------------
840 . Debugging function for viewing MII Management serial bitstream
841 .-------------------------------------------------------------*/
smc_dump_mii_stream(byte * bits,int size)842 static void smc_dump_mii_stream (byte * bits, int size)
843 {
844 int i;
845
846 printf ("BIT#:");
847 for (i = 0; i < size; ++i) {
848 printf ("%d", i % 10);
849 }
850
851 printf ("\nMDOE:");
852 for (i = 0; i < size; ++i) {
853 if (bits[i] & MII_MDOE)
854 printf ("1");
855 else
856 printf ("0");
857 }
858
859 printf ("\nMDO :");
860 for (i = 0; i < size; ++i) {
861 if (bits[i] & MII_MDO)
862 printf ("1");
863 else
864 printf ("0");
865 }
866
867 printf ("\nMDI :");
868 for (i = 0; i < size; ++i) {
869 if (bits[i] & MII_MDI)
870 printf ("1");
871 else
872 printf ("0");
873 }
874
875 printf ("\n");
876 }
877 #endif
878
879 /*------------------------------------------------------------
880 . Reads a register from the MII Management serial interface
881 .-------------------------------------------------------------*/
882 #ifndef CONFIG_SMC91111_EXT_PHY
smc_read_phy_register(struct eth_device * dev,byte phyreg)883 static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
884 {
885 int oldBank;
886 int i;
887 byte mask;
888 word mii_reg;
889 byte bits[64];
890 int clk_idx = 0;
891 int input_idx;
892 word phydata;
893 byte phyaddr = SMC_PHY_ADDR;
894
895 /* 32 consecutive ones on MDO to establish sync */
896 for (i = 0; i < 32; ++i)
897 bits[clk_idx++] = MII_MDOE | MII_MDO;
898
899 /* Start code <01> */
900 bits[clk_idx++] = MII_MDOE;
901 bits[clk_idx++] = MII_MDOE | MII_MDO;
902
903 /* Read command <10> */
904 bits[clk_idx++] = MII_MDOE | MII_MDO;
905 bits[clk_idx++] = MII_MDOE;
906
907 /* Output the PHY address, msb first */
908 mask = (byte) 0x10;
909 for (i = 0; i < 5; ++i) {
910 if (phyaddr & mask)
911 bits[clk_idx++] = MII_MDOE | MII_MDO;
912 else
913 bits[clk_idx++] = MII_MDOE;
914
915 /* Shift to next lowest bit */
916 mask >>= 1;
917 }
918
919 /* Output the phy register number, msb first */
920 mask = (byte) 0x10;
921 for (i = 0; i < 5; ++i) {
922 if (phyreg & mask)
923 bits[clk_idx++] = MII_MDOE | MII_MDO;
924 else
925 bits[clk_idx++] = MII_MDOE;
926
927 /* Shift to next lowest bit */
928 mask >>= 1;
929 }
930
931 /* Tristate and turnaround (2 bit times) */
932 bits[clk_idx++] = 0;
933 /*bits[clk_idx++] = 0; */
934
935 /* Input starts at this bit time */
936 input_idx = clk_idx;
937
938 /* Will input 16 bits */
939 for (i = 0; i < 16; ++i)
940 bits[clk_idx++] = 0;
941
942 /* Final clock bit */
943 bits[clk_idx++] = 0;
944
945 /* Save the current bank */
946 oldBank = SMC_inw (dev, BANK_SELECT);
947
948 /* Select bank 3 */
949 SMC_SELECT_BANK (dev, 3);
950
951 /* Get the current MII register value */
952 mii_reg = SMC_inw (dev, MII_REG);
953
954 /* Turn off all MII Interface bits */
955 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
956
957 /* Clock all 64 cycles */
958 for (i = 0; i < sizeof bits; ++i) {
959 /* Clock Low - output data */
960 SMC_outw (dev, mii_reg | bits[i], MII_REG);
961 udelay(SMC_PHY_CLOCK_DELAY);
962
963
964 /* Clock Hi - input data */
965 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
966 udelay(SMC_PHY_CLOCK_DELAY);
967 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
968 }
969
970 /* Return to idle state */
971 /* Set clock to low, data to low, and output tristated */
972 SMC_outw (dev, mii_reg, MII_REG);
973 udelay(SMC_PHY_CLOCK_DELAY);
974
975 /* Restore original bank select */
976 SMC_SELECT_BANK (dev, oldBank);
977
978 /* Recover input data */
979 phydata = 0;
980 for (i = 0; i < 16; ++i) {
981 phydata <<= 1;
982
983 if (bits[input_idx++] & MII_MDI)
984 phydata |= 0x0001;
985 }
986
987 #if (SMC_DEBUG > 2 )
988 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
989 phyaddr, phyreg, phydata);
990 smc_dump_mii_stream (bits, sizeof bits);
991 #endif
992
993 return (phydata);
994 }
995
996
997 /*------------------------------------------------------------
998 . Writes a register to the MII Management serial interface
999 .-------------------------------------------------------------*/
smc_write_phy_register(struct eth_device * dev,byte phyreg,word phydata)1000 static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1001 word phydata)
1002 {
1003 int oldBank;
1004 int i;
1005 word mask;
1006 word mii_reg;
1007 byte bits[65];
1008 int clk_idx = 0;
1009 byte phyaddr = SMC_PHY_ADDR;
1010
1011 /* 32 consecutive ones on MDO to establish sync */
1012 for (i = 0; i < 32; ++i)
1013 bits[clk_idx++] = MII_MDOE | MII_MDO;
1014
1015 /* Start code <01> */
1016 bits[clk_idx++] = MII_MDOE;
1017 bits[clk_idx++] = MII_MDOE | MII_MDO;
1018
1019 /* Write command <01> */
1020 bits[clk_idx++] = MII_MDOE;
1021 bits[clk_idx++] = MII_MDOE | MII_MDO;
1022
1023 /* Output the PHY address, msb first */
1024 mask = (byte) 0x10;
1025 for (i = 0; i < 5; ++i) {
1026 if (phyaddr & mask)
1027 bits[clk_idx++] = MII_MDOE | MII_MDO;
1028 else
1029 bits[clk_idx++] = MII_MDOE;
1030
1031 /* Shift to next lowest bit */
1032 mask >>= 1;
1033 }
1034
1035 /* Output the phy register number, msb first */
1036 mask = (byte) 0x10;
1037 for (i = 0; i < 5; ++i) {
1038 if (phyreg & mask)
1039 bits[clk_idx++] = MII_MDOE | MII_MDO;
1040 else
1041 bits[clk_idx++] = MII_MDOE;
1042
1043 /* Shift to next lowest bit */
1044 mask >>= 1;
1045 }
1046
1047 /* Tristate and turnaround (2 bit times) */
1048 bits[clk_idx++] = 0;
1049 bits[clk_idx++] = 0;
1050
1051 /* Write out 16 bits of data, msb first */
1052 mask = 0x8000;
1053 for (i = 0; i < 16; ++i) {
1054 if (phydata & mask)
1055 bits[clk_idx++] = MII_MDOE | MII_MDO;
1056 else
1057 bits[clk_idx++] = MII_MDOE;
1058
1059 /* Shift to next lowest bit */
1060 mask >>= 1;
1061 }
1062
1063 /* Final clock bit (tristate) */
1064 bits[clk_idx++] = 0;
1065
1066 /* Save the current bank */
1067 oldBank = SMC_inw (dev, BANK_SELECT);
1068
1069 /* Select bank 3 */
1070 SMC_SELECT_BANK (dev, 3);
1071
1072 /* Get the current MII register value */
1073 mii_reg = SMC_inw (dev, MII_REG);
1074
1075 /* Turn off all MII Interface bits */
1076 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1077
1078 /* Clock all cycles */
1079 for (i = 0; i < sizeof bits; ++i) {
1080 /* Clock Low - output data */
1081 SMC_outw (dev, mii_reg | bits[i], MII_REG);
1082 udelay(SMC_PHY_CLOCK_DELAY);
1083
1084
1085 /* Clock Hi - input data */
1086 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1087 udelay(SMC_PHY_CLOCK_DELAY);
1088 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1089 }
1090
1091 /* Return to idle state */
1092 /* Set clock to low, data to low, and output tristated */
1093 SMC_outw (dev, mii_reg, MII_REG);
1094 udelay(SMC_PHY_CLOCK_DELAY);
1095
1096 /* Restore original bank select */
1097 SMC_SELECT_BANK (dev, oldBank);
1098
1099 #if (SMC_DEBUG > 2 )
1100 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1101 phyaddr, phyreg, phydata);
1102 smc_dump_mii_stream (bits, sizeof bits);
1103 #endif
1104 }
1105 #endif /* !CONFIG_SMC91111_EXT_PHY */
1106
1107
1108 /*------------------------------------------------------------
1109 . Configures the specified PHY using Autonegotiation. Calls
1110 . smc_phy_fixed() if the user has requested a certain config.
1111 .-------------------------------------------------------------*/
1112 #ifndef CONFIG_SMC91111_EXT_PHY
smc_phy_configure(struct eth_device * dev)1113 static void smc_phy_configure (struct eth_device *dev)
1114 {
1115 int timeout;
1116 word my_phy_caps; /* My PHY capabilities */
1117 word my_ad_caps; /* My Advertised capabilities */
1118 word status = 0; /*;my status = 0 */
1119
1120 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1121
1122 /* Reset the PHY, setting all other bits to zero */
1123 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
1124
1125 /* Wait for the reset to complete, or time out */
1126 timeout = 6; /* Wait up to 3 seconds */
1127 while (timeout--) {
1128 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
1129 & PHY_CNTL_RST)) {
1130 /* reset complete */
1131 break;
1132 }
1133
1134 mdelay(500); /* wait 500 millisecs */
1135 }
1136
1137 if (timeout < 1) {
1138 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1139 goto smc_phy_configure_exit;
1140 }
1141
1142 /* Read PHY Register 18, Status Output */
1143 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1144
1145 /* Enable PHY Interrupts (for register 18) */
1146 /* Interrupts listed here are disabled */
1147 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
1148
1149 /* Configure the Receive/Phy Control register */
1150 SMC_SELECT_BANK (dev, 0);
1151 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1152
1153 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1154 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
1155 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1156
1157 if (my_phy_caps & PHY_STAT_CAP_T4)
1158 my_ad_caps |= PHY_AD_T4;
1159
1160 if (my_phy_caps & PHY_STAT_CAP_TXF)
1161 my_ad_caps |= PHY_AD_TX_FDX;
1162
1163 if (my_phy_caps & PHY_STAT_CAP_TXH)
1164 my_ad_caps |= PHY_AD_TX_HDX;
1165
1166 if (my_phy_caps & PHY_STAT_CAP_TF)
1167 my_ad_caps |= PHY_AD_10_FDX;
1168
1169 if (my_phy_caps & PHY_STAT_CAP_TH)
1170 my_ad_caps |= PHY_AD_10_HDX;
1171
1172 /* Update our Auto-Neg Advertisement Register */
1173 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
1174
1175 /* Read the register back. Without this, it appears that when */
1176 /* auto-negotiation is restarted, sometimes it isn't ready and */
1177 /* the link does not come up. */
1178 smc_read_phy_register(dev, PHY_AD_REG);
1179
1180 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1181 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1182
1183 /* Restart auto-negotiation process in order to advertise my caps */
1184 smc_write_phy_register (dev, PHY_CNTL_REG,
1185 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1186
1187 /* Wait for the auto-negotiation to complete. This may take from */
1188 /* 2 to 3 seconds. */
1189 /* Wait for the reset to complete, or time out */
1190 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1191 while (timeout--) {
1192
1193 status = smc_read_phy_register (dev, PHY_STAT_REG);
1194 if (status & PHY_STAT_ANEG_ACK) {
1195 /* auto-negotiate complete */
1196 break;
1197 }
1198
1199 mdelay(500); /* wait 500 millisecs */
1200
1201 /* Restart auto-negotiation if remote fault */
1202 if (status & PHY_STAT_REM_FLT) {
1203 printf ("%s: PHY remote fault detected\n",
1204 SMC_DEV_NAME);
1205
1206 /* Restart auto-negotiation */
1207 printf ("%s: PHY restarting auto-negotiation\n",
1208 SMC_DEV_NAME);
1209 smc_write_phy_register (dev, PHY_CNTL_REG,
1210 PHY_CNTL_ANEG_EN |
1211 PHY_CNTL_ANEG_RST |
1212 PHY_CNTL_SPEED |
1213 PHY_CNTL_DPLX);
1214 }
1215 }
1216
1217 if (timeout < 1) {
1218 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1219 }
1220
1221 /* Fail if we detected an auto-negotiate remote fault */
1222 if (status & PHY_STAT_REM_FLT) {
1223 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1224 }
1225
1226 /* Re-Configure the Receive/Phy Control register */
1227 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1228
1229 smc_phy_configure_exit: ;
1230
1231 }
1232 #endif /* !CONFIG_SMC91111_EXT_PHY */
1233
1234
1235 #if SMC_DEBUG > 2
print_packet(byte * buf,int length)1236 static void print_packet( byte * buf, int length )
1237 {
1238 int i;
1239 int remainder;
1240 int lines;
1241
1242 printf("Packet of length %d \n", length );
1243
1244 #if SMC_DEBUG > 3
1245 lines = length / 16;
1246 remainder = length % 16;
1247
1248 for ( i = 0; i < lines ; i ++ ) {
1249 int cur;
1250
1251 for ( cur = 0; cur < 8; cur ++ ) {
1252 byte a, b;
1253
1254 a = *(buf ++ );
1255 b = *(buf ++ );
1256 printf("%02x%02x ", a, b );
1257 }
1258 printf("\n");
1259 }
1260 for ( i = 0; i < remainder/2 ; i++ ) {
1261 byte a, b;
1262
1263 a = *(buf ++ );
1264 b = *(buf ++ );
1265 printf("%02x%02x ", a, b );
1266 }
1267 printf("\n");
1268 #endif
1269 }
1270 #endif
1271
smc91111_initialize(u8 dev_num,int base_addr)1272 int smc91111_initialize(u8 dev_num, int base_addr)
1273 {
1274 struct smc91111_priv *priv;
1275 struct eth_device *dev;
1276 int i;
1277
1278 priv = malloc(sizeof(*priv));
1279 if (!priv)
1280 return 0;
1281 dev = malloc(sizeof(*dev));
1282 if (!dev) {
1283 free(priv);
1284 return 0;
1285 }
1286
1287 memset(dev, 0, sizeof(*dev));
1288 priv->dev_num = dev_num;
1289 dev->priv = priv;
1290 dev->iobase = base_addr;
1291
1292 swap_to(ETHERNET);
1293 SMC_SELECT_BANK(dev, 1);
1294 for (i = 0; i < 6; ++i)
1295 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1296 swap_to(FLASH);
1297
1298 dev->init = smc_init;
1299 dev->halt = smc_halt;
1300 dev->send = smc_send;
1301 dev->recv = smc_rcv;
1302 dev->write_hwaddr = smc_write_hwaddr;
1303 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1304
1305 eth_register(dev);
1306 return 0;
1307 }
1308