1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2016-2018 Socionext inc.
5 */
6
7 #include <clk.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <fdt_support.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <miiphy.h>
14 #include <net.h>
15 #include <regmap.h>
16 #include <reset.h>
17 #include <syscon.h>
18 #include <asm/cache.h>
19 #include <asm/global_data.h>
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/iopoll.h>
26
27 #define AVE_GRST_DELAY_MSEC 40
28 #define AVE_MIN_XMITSIZE 60
29 #define AVE_SEND_TIMEOUT_COUNT 1000
30 #define AVE_MDIO_TIMEOUT_USEC 10000
31 #define AVE_HALT_TIMEOUT_USEC 10000
32
33 /* General Register Group */
34 #define AVE_IDR 0x000 /* ID */
35 #define AVE_VR 0x004 /* Version */
36 #define AVE_GRR 0x008 /* Global Reset */
37 #define AVE_CFGR 0x00c /* Configuration */
38
39 /* Interrupt Register Group */
40 #define AVE_GIMR 0x100 /* Global Interrupt Mask */
41 #define AVE_GISR 0x104 /* Global Interrupt Status */
42
43 /* MAC Register Group */
44 #define AVE_TXCR 0x200 /* TX Setup */
45 #define AVE_RXCR 0x204 /* RX Setup */
46 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
47 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
48 #define AVE_MDIOCTR 0x214 /* MDIO Control */
49 #define AVE_MDIOAR 0x218 /* MDIO Address */
50 #define AVE_MDIOWDR 0x21c /* MDIO Data */
51 #define AVE_MDIOSR 0x220 /* MDIO Status */
52 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
53
54 /* Descriptor Control Register Group */
55 #define AVE_DESCC 0x300 /* Descriptor Control */
56 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
57 #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
58 #define AVE_IIRQC 0x34c /* Interval IRQ Control */
59
60 /* 64bit descriptor memory */
61 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
62 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
63 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
64
65 /* 32bit descriptor memory */
66 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
67 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
68 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
69
70 /* RMII Bridge Register Group */
71 #define AVE_RSTCTRL 0x8028 /* Reset control */
72 #define AVE_RSTCTRL_RMIIRST BIT(16)
73 #define AVE_LINKSEL 0x8034 /* Link speed setting */
74 #define AVE_LINKSEL_100M BIT(0)
75
76 /* AVE_GRR */
77 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
78 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
79
80 /* AVE_CFGR */
81 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
82
83 /* AVE_GISR (common with GIMR) */
84 #define AVE_GIMR_CLR 0
85 #define AVE_GISR_CLR GENMASK(31, 0)
86
87 /* AVE_TXCR */
88 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
89 #define AVE_TXCR_TXSPD_1G BIT(17)
90 #define AVE_TXCR_TXSPD_100 BIT(16)
91
92 /* AVE_RXCR */
93 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
94 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
95 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
96
97 /* AVE_MDIOCTR */
98 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
99 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
100
101 /* AVE_MDIOSR */
102 #define AVE_MDIOSR_STS BIT(0) /* access status */
103
104 /* AVE_DESCC */
105 #define AVE_DESCC_RXDSTPSTS BIT(20)
106 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
107 #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
108 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
109
110 /* AVE_TXDC/RXDC */
111 #define AVE_DESC_SIZE(priv, num) \
112 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
113 AVE_DESC_SIZE_32))
114
115 /* Command status for descriptor */
116 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
117 #define AVE_STS_OK BIT(27) /* Normal transmit */
118 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
119 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
120 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
121 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
122
123 #define AVE_DESC_OFS_CMDSTS 0
124 #define AVE_DESC_OFS_ADDRL 4
125 #define AVE_DESC_OFS_ADDRU 8
126
127 /* Parameter for ethernet frame */
128 #define AVE_RXCR_MTU 1518
129
130 /* SG */
131 #define SG_ETPINMODE 0x540
132 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
133 #define SG_ETPINMODE_RMII(ins) BIT(ins)
134
135 #define AVE_MAX_CLKS 4
136 #define AVE_MAX_RSTS 2
137
138 enum desc_id {
139 AVE_DESCID_TX,
140 AVE_DESCID_RX,
141 };
142
143 struct ave_private {
144 phys_addr_t iobase;
145 unsigned int nclks;
146 struct clk clk[AVE_MAX_CLKS];
147 unsigned int nrsts;
148 struct reset_ctl rst[AVE_MAX_RSTS];
149 struct regmap *regmap;
150 unsigned int regmap_arg;
151
152 struct mii_dev *bus;
153 struct phy_device *phydev;
154 int phy_mode;
155 int max_speed;
156
157 int rx_pos;
158 int rx_siz;
159 int rx_off;
160 int tx_num;
161
162 u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
163 void *tx_adj_buf;
164
165 const struct ave_soc_data *data;
166 };
167
168 struct ave_soc_data {
169 bool is_desc_64bit;
170 const char *clock_names[AVE_MAX_CLKS];
171 const char *reset_names[AVE_MAX_RSTS];
172 int (*get_pinmode)(struct ave_private *priv);
173 };
174
ave_desc_read(struct ave_private * priv,enum desc_id id,int entry,int offset)175 static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
176 int offset)
177 {
178 int desc_size;
179 u32 addr;
180
181 if (priv->data->is_desc_64bit) {
182 desc_size = AVE_DESC_SIZE_64;
183 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
184 } else {
185 desc_size = AVE_DESC_SIZE_32;
186 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
187 }
188
189 addr += entry * desc_size + offset;
190
191 return readl(priv->iobase + addr);
192 }
193
ave_desc_read_cmdsts(struct ave_private * priv,enum desc_id id,int entry)194 static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
195 int entry)
196 {
197 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
198 }
199
ave_desc_write(struct ave_private * priv,enum desc_id id,int entry,int offset,u32 val)200 static void ave_desc_write(struct ave_private *priv, enum desc_id id,
201 int entry, int offset, u32 val)
202 {
203 int desc_size;
204 u32 addr;
205
206 if (priv->data->is_desc_64bit) {
207 desc_size = AVE_DESC_SIZE_64;
208 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
209 } else {
210 desc_size = AVE_DESC_SIZE_32;
211 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
212 }
213
214 addr += entry * desc_size + offset;
215 writel(val, priv->iobase + addr);
216 }
217
ave_desc_write_cmdsts(struct ave_private * priv,enum desc_id id,int entry,u32 val)218 static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
219 int entry, u32 val)
220 {
221 ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
222 }
223
ave_desc_write_addr(struct ave_private * priv,enum desc_id id,int entry,uintptr_t paddr)224 static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
225 int entry, uintptr_t paddr)
226 {
227 ave_desc_write(priv, id, entry,
228 AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
229 if (priv->data->is_desc_64bit)
230 ave_desc_write(priv, id, entry,
231 AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
232 }
233
ave_cache_invalidate(uintptr_t vaddr,int len)234 static void ave_cache_invalidate(uintptr_t vaddr, int len)
235 {
236 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
237 roundup(vaddr + len, ARCH_DMA_MINALIGN));
238 }
239
ave_cache_flush(uintptr_t vaddr,int len)240 static void ave_cache_flush(uintptr_t vaddr, int len)
241 {
242 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
243 roundup(vaddr + len, ARCH_DMA_MINALIGN));
244 }
245
ave_mdiobus_read(struct mii_dev * bus,int phyid,int devad,int regnum)246 static int ave_mdiobus_read(struct mii_dev *bus,
247 int phyid, int devad, int regnum)
248 {
249 struct ave_private *priv = bus->priv;
250 u32 mdioctl, mdiosr;
251 int ret;
252
253 /* write address */
254 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
255
256 /* read request */
257 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
258 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
259
260 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
261 !(mdiosr & AVE_MDIOSR_STS),
262 AVE_MDIO_TIMEOUT_USEC);
263 if (ret) {
264 pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
265 priv->phydev->dev->name, phyid, regnum);
266 return ret;
267 }
268
269 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
270 }
271
ave_mdiobus_write(struct mii_dev * bus,int phyid,int devad,int regnum,u16 val)272 static int ave_mdiobus_write(struct mii_dev *bus,
273 int phyid, int devad, int regnum, u16 val)
274 {
275 struct ave_private *priv = bus->priv;
276 u32 mdioctl, mdiosr;
277 int ret;
278
279 /* write address */
280 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
281
282 /* write data */
283 writel(val, priv->iobase + AVE_MDIOWDR);
284
285 /* write request */
286 mdioctl = readl(priv->iobase + AVE_MDIOCTR);
287 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
288 priv->iobase + AVE_MDIOCTR);
289
290 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
291 !(mdiosr & AVE_MDIOSR_STS),
292 AVE_MDIO_TIMEOUT_USEC);
293 if (ret)
294 pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
295 priv->phydev->dev->name, phyid, regnum);
296
297 return ret;
298 }
299
ave_adjust_link(struct ave_private * priv)300 static int ave_adjust_link(struct ave_private *priv)
301 {
302 struct phy_device *phydev = priv->phydev;
303 struct eth_pdata *pdata = dev_get_plat(phydev->dev);
304 u32 val, txcr, rxcr, rxcr_org;
305 u16 rmt_adv = 0, lcl_adv = 0;
306 u8 cap;
307
308 /* set RGMII speed */
309 val = readl(priv->iobase + AVE_TXCR);
310 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
311
312 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
313 val |= AVE_TXCR_TXSPD_1G;
314 else if (phydev->speed == SPEED_100)
315 val |= AVE_TXCR_TXSPD_100;
316
317 writel(val, priv->iobase + AVE_TXCR);
318
319 /* set RMII speed (100M/10M only) */
320 if (!phy_interface_is_rgmii(phydev)) {
321 val = readl(priv->iobase + AVE_LINKSEL);
322 if (phydev->speed == SPEED_10)
323 val &= ~AVE_LINKSEL_100M;
324 else
325 val |= AVE_LINKSEL_100M;
326 writel(val, priv->iobase + AVE_LINKSEL);
327 }
328
329 /* check current RXCR/TXCR */
330 rxcr = readl(priv->iobase + AVE_RXCR);
331 txcr = readl(priv->iobase + AVE_TXCR);
332 rxcr_org = rxcr;
333
334 if (phydev->duplex) {
335 rxcr |= AVE_RXCR_FDUPEN;
336
337 if (phydev->pause)
338 rmt_adv |= LPA_PAUSE_CAP;
339 if (phydev->asym_pause)
340 rmt_adv |= LPA_PAUSE_ASYM;
341 if (phydev->advertising & ADVERTISED_Pause)
342 lcl_adv |= ADVERTISE_PAUSE_CAP;
343 if (phydev->advertising & ADVERTISED_Asym_Pause)
344 lcl_adv |= ADVERTISE_PAUSE_ASYM;
345
346 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
347 if (cap & FLOW_CTRL_TX)
348 txcr |= AVE_TXCR_FLOCTR;
349 else
350 txcr &= ~AVE_TXCR_FLOCTR;
351 if (cap & FLOW_CTRL_RX)
352 rxcr |= AVE_RXCR_FLOCTR;
353 else
354 rxcr &= ~AVE_RXCR_FLOCTR;
355 } else {
356 rxcr &= ~AVE_RXCR_FDUPEN;
357 rxcr &= ~AVE_RXCR_FLOCTR;
358 txcr &= ~AVE_TXCR_FLOCTR;
359 }
360
361 if (rxcr_org != rxcr) {
362 /* disable Rx mac */
363 writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
364 /* change and enable TX/Rx mac */
365 writel(txcr, priv->iobase + AVE_TXCR);
366 writel(rxcr, priv->iobase + AVE_RXCR);
367 }
368
369 pr_notice("%s: phy:%s speed:%d mac:%pM\n",
370 phydev->dev->name, phydev->drv->name, phydev->speed,
371 pdata->enetaddr);
372
373 return phydev->link;
374 }
375
ave_mdiobus_init(struct ave_private * priv,const char * name)376 static int ave_mdiobus_init(struct ave_private *priv, const char *name)
377 {
378 struct mii_dev *bus = mdio_alloc();
379
380 if (!bus)
381 return -ENOMEM;
382
383 bus->read = ave_mdiobus_read;
384 bus->write = ave_mdiobus_write;
385 snprintf(bus->name, sizeof(bus->name), "%s", name);
386 bus->priv = priv;
387
388 return mdio_register(bus);
389 }
390
ave_phy_init(struct ave_private * priv,void * dev)391 static int ave_phy_init(struct ave_private *priv, void *dev)
392 {
393 struct phy_device *phydev;
394 int mask = GENMASK(31, 0), ret;
395
396 phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
397 if (!phydev)
398 return -ENODEV;
399
400 phy_connect_dev(phydev, dev);
401
402 phydev->supported &= PHY_GBIT_FEATURES;
403 if (priv->max_speed) {
404 ret = phy_set_supported(phydev, priv->max_speed);
405 if (ret)
406 return ret;
407 }
408 phydev->advertising = phydev->supported;
409
410 priv->phydev = phydev;
411 phy_config(phydev);
412
413 return 0;
414 }
415
ave_stop(struct udevice * dev)416 static void ave_stop(struct udevice *dev)
417 {
418 struct ave_private *priv = dev_get_priv(dev);
419 u32 val;
420 int ret;
421
422 val = readl(priv->iobase + AVE_GRR);
423 if (val)
424 return;
425
426 val = readl(priv->iobase + AVE_RXCR);
427 val &= ~AVE_RXCR_RXEN;
428 writel(val, priv->iobase + AVE_RXCR);
429
430 writel(0, priv->iobase + AVE_DESCC);
431 ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
432 AVE_HALT_TIMEOUT_USEC);
433 if (ret)
434 pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
435
436 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
437
438 phy_shutdown(priv->phydev);
439 }
440
ave_reset(struct ave_private * priv)441 static void ave_reset(struct ave_private *priv)
442 {
443 u32 val;
444
445 /* reset RMII register */
446 val = readl(priv->iobase + AVE_RSTCTRL);
447 val &= ~AVE_RSTCTRL_RMIIRST;
448 writel(val, priv->iobase + AVE_RSTCTRL);
449
450 /* assert reset */
451 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
452 mdelay(AVE_GRST_DELAY_MSEC);
453
454 /* 1st, negate PHY reset only */
455 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
456 mdelay(AVE_GRST_DELAY_MSEC);
457
458 /* negate reset */
459 writel(0, priv->iobase + AVE_GRR);
460 mdelay(AVE_GRST_DELAY_MSEC);
461
462 /* negate RMII register */
463 val = readl(priv->iobase + AVE_RSTCTRL);
464 val |= AVE_RSTCTRL_RMIIRST;
465 writel(val, priv->iobase + AVE_RSTCTRL);
466 }
467
ave_start(struct udevice * dev)468 static int ave_start(struct udevice *dev)
469 {
470 struct ave_private *priv = dev_get_priv(dev);
471 uintptr_t paddr;
472 u32 val;
473 int i;
474
475 ave_reset(priv);
476
477 priv->rx_pos = 0;
478 priv->rx_off = 2; /* RX data has 2byte offsets */
479 priv->tx_num = 0;
480 priv->tx_adj_buf =
481 (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
482 PKTALIGN);
483 priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
484
485 val = 0;
486 if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
487 val |= AVE_CFGR_MII;
488 writel(val, priv->iobase + AVE_CFGR);
489
490 /* use one descriptor for Tx */
491 writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
492 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
493 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
494
495 /* use PKTBUFSRX descriptors for Rx */
496 writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
497 for (i = 0; i < PKTBUFSRX; i++) {
498 paddr = (uintptr_t)net_rx_packets[i];
499 ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
500 ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
501 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
502 }
503
504 writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
505 writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
506
507 writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
508 priv->iobase + AVE_RXCR);
509 writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
510
511 phy_startup(priv->phydev);
512 ave_adjust_link(priv);
513
514 return 0;
515 }
516
ave_write_hwaddr(struct udevice * dev)517 static int ave_write_hwaddr(struct udevice *dev)
518 {
519 struct ave_private *priv = dev_get_priv(dev);
520 struct eth_pdata *pdata = dev_get_plat(dev);
521 u8 *mac = pdata->enetaddr;
522
523 writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
524 priv->iobase + AVE_RXMAC1R);
525 writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
526
527 return 0;
528 }
529
ave_send(struct udevice * dev,void * packet,int length)530 static int ave_send(struct udevice *dev, void *packet, int length)
531 {
532 struct ave_private *priv = dev_get_priv(dev);
533 u32 val;
534 void *ptr = packet;
535 int count;
536
537 /* adjust alignment for descriptor */
538 if ((uintptr_t)ptr & 0x3) {
539 memcpy(priv->tx_adj_buf, (const void *)ptr, length);
540 ptr = priv->tx_adj_buf;
541 }
542
543 /* padding for minimum length */
544 if (length < AVE_MIN_XMITSIZE) {
545 memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
546 length = AVE_MIN_XMITSIZE;
547 }
548
549 /* check ownership and wait for previous xmit done */
550 count = AVE_SEND_TIMEOUT_COUNT;
551 do {
552 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
553 } while ((val & AVE_STS_OWN) && --count);
554 if (!count)
555 return -ETIMEDOUT;
556
557 ave_cache_flush((uintptr_t)ptr, length);
558 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
559
560 val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
561 (length & AVE_STS_PKTLEN_TX_MASK);
562 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
563 priv->tx_num++;
564
565 count = AVE_SEND_TIMEOUT_COUNT;
566 do {
567 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
568 } while ((val & AVE_STS_OWN) && --count);
569 if (!count)
570 return -ETIMEDOUT;
571
572 if (!(val & AVE_STS_OK))
573 pr_warn("%s: bad send packet status:%08x\n",
574 priv->phydev->dev->name, le32_to_cpu(val));
575
576 return 0;
577 }
578
ave_recv(struct udevice * dev,int flags,uchar ** packetp)579 static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
580 {
581 struct ave_private *priv = dev_get_priv(dev);
582 uchar *ptr;
583 int length = 0;
584 u32 cmdsts;
585
586 while (1) {
587 cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
588 priv->rx_pos);
589 if (!(cmdsts & AVE_STS_OWN))
590 /* hardware ownership, no received packets */
591 return -EAGAIN;
592
593 ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
594 if (cmdsts & AVE_STS_OK)
595 break;
596
597 pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
598 priv->phydev->dev->name, priv->rx_pos,
599 le32_to_cpu(cmdsts), ptr);
600 }
601
602 length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
603
604 /* invalidate after DMA is done */
605 ave_cache_invalidate((uintptr_t)ptr, length);
606 *packetp = ptr;
607
608 return length;
609 }
610
ave_free_packet(struct udevice * dev,uchar * packet,int length)611 static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
612 {
613 struct ave_private *priv = dev_get_priv(dev);
614
615 ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
616 priv->rx_siz + priv->rx_off);
617
618 ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
619 priv->rx_pos, priv->rx_siz);
620
621 if (++priv->rx_pos >= PKTBUFSRX)
622 priv->rx_pos = 0;
623
624 return 0;
625 }
626
ave_pro4_get_pinmode(struct ave_private * priv)627 static int ave_pro4_get_pinmode(struct ave_private *priv)
628 {
629 u32 reg, mask, val = 0;
630
631 if (priv->regmap_arg > 0)
632 return -EINVAL;
633
634 mask = SG_ETPINMODE_RMII(0);
635
636 switch (priv->phy_mode) {
637 case PHY_INTERFACE_MODE_RMII:
638 val = SG_ETPINMODE_RMII(0);
639 break;
640 case PHY_INTERFACE_MODE_MII:
641 case PHY_INTERFACE_MODE_RGMII:
642 break;
643 default:
644 return -EINVAL;
645 }
646
647 regmap_read(priv->regmap, SG_ETPINMODE, ®);
648 reg &= ~mask;
649 reg |= val;
650 regmap_write(priv->regmap, SG_ETPINMODE, reg);
651
652 return 0;
653 }
654
ave_ld11_get_pinmode(struct ave_private * priv)655 static int ave_ld11_get_pinmode(struct ave_private *priv)
656 {
657 u32 reg, mask, val = 0;
658
659 if (priv->regmap_arg > 0)
660 return -EINVAL;
661
662 mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
663
664 switch (priv->phy_mode) {
665 case PHY_INTERFACE_MODE_INTERNAL:
666 break;
667 case PHY_INTERFACE_MODE_RMII:
668 val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
669 break;
670 default:
671 return -EINVAL;
672 }
673
674 regmap_read(priv->regmap, SG_ETPINMODE, ®);
675 reg &= ~mask;
676 reg |= val;
677 regmap_write(priv->regmap, SG_ETPINMODE, reg);
678
679 return 0;
680 }
681
ave_ld20_get_pinmode(struct ave_private * priv)682 static int ave_ld20_get_pinmode(struct ave_private *priv)
683 {
684 u32 reg, mask, val = 0;
685
686 if (priv->regmap_arg > 0)
687 return -EINVAL;
688
689 mask = SG_ETPINMODE_RMII(0);
690
691 switch (priv->phy_mode) {
692 case PHY_INTERFACE_MODE_RMII:
693 val = SG_ETPINMODE_RMII(0);
694 break;
695 case PHY_INTERFACE_MODE_RGMII:
696 break;
697 default:
698 return -EINVAL;
699 }
700
701 regmap_read(priv->regmap, SG_ETPINMODE, ®);
702 reg &= ~mask;
703 reg |= val;
704 regmap_write(priv->regmap, SG_ETPINMODE, reg);
705
706 return 0;
707 }
708
ave_pxs3_get_pinmode(struct ave_private * priv)709 static int ave_pxs3_get_pinmode(struct ave_private *priv)
710 {
711 u32 reg, mask, val = 0;
712
713 if (priv->regmap_arg > 1)
714 return -EINVAL;
715
716 mask = SG_ETPINMODE_RMII(priv->regmap_arg);
717
718 switch (priv->phy_mode) {
719 case PHY_INTERFACE_MODE_RMII:
720 val = SG_ETPINMODE_RMII(priv->regmap_arg);
721 break;
722 case PHY_INTERFACE_MODE_RGMII:
723 break;
724 default:
725 return -EINVAL;
726 }
727
728 regmap_read(priv->regmap, SG_ETPINMODE, ®);
729 reg &= ~mask;
730 reg |= val;
731 regmap_write(priv->regmap, SG_ETPINMODE, reg);
732
733 return 0;
734 }
735
ave_of_to_plat(struct udevice * dev)736 static int ave_of_to_plat(struct udevice *dev)
737 {
738 struct eth_pdata *pdata = dev_get_plat(dev);
739 struct ave_private *priv = dev_get_priv(dev);
740 struct ofnode_phandle_args args;
741 const char *phy_mode;
742 const u32 *valp;
743 int ret, nc, nr;
744 const char *name;
745
746 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
747 if (!priv->data)
748 return -EINVAL;
749
750 pdata->iobase = dev_read_addr(dev);
751 pdata->phy_interface = -1;
752 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
753 NULL);
754 if (phy_mode)
755 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
756 if (pdata->phy_interface == -1) {
757 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
758 return -EINVAL;
759 }
760
761 pdata->max_speed = 0;
762 valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
763 NULL);
764 if (valp)
765 pdata->max_speed = fdt32_to_cpu(*valp);
766
767 for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
768 name = priv->data->clock_names[nc];
769 if (!name)
770 break;
771 ret = clk_get_by_name(dev, name, &priv->clk[nc]);
772 if (ret) {
773 dev_err(dev, "Failed to get clocks property: %d\n",
774 ret);
775 goto out_clk_free;
776 }
777 priv->nclks++;
778 }
779
780 for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
781 name = priv->data->reset_names[nr];
782 if (!name)
783 break;
784 ret = reset_get_by_name(dev, name, &priv->rst[nr]);
785 if (ret) {
786 dev_err(dev, "Failed to get resets property: %d\n",
787 ret);
788 goto out_reset_free;
789 }
790 priv->nrsts++;
791 }
792
793 ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
794 NULL, 1, 0, &args);
795 if (ret) {
796 dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
797 ret);
798 goto out_reset_free;
799 }
800
801 priv->regmap = syscon_node_to_regmap(args.node);
802 if (IS_ERR(priv->regmap)) {
803 ret = PTR_ERR(priv->regmap);
804 dev_err(dev, "can't get syscon: %d\n", ret);
805 goto out_reset_free;
806 }
807
808 if (args.args_count != 1) {
809 ret = -EINVAL;
810 dev_err(dev, "Invalid argument of syscon-phy-mode\n");
811 goto out_reset_free;
812 }
813
814 priv->regmap_arg = args.args[0];
815
816 return 0;
817
818 out_reset_free:
819 while (--nr >= 0)
820 reset_free(&priv->rst[nr]);
821 out_clk_free:
822 while (--nc >= 0)
823 clk_free(&priv->clk[nc]);
824
825 return ret;
826 }
827
ave_probe(struct udevice * dev)828 static int ave_probe(struct udevice *dev)
829 {
830 struct eth_pdata *pdata = dev_get_plat(dev);
831 struct ave_private *priv = dev_get_priv(dev);
832 int ret, nc, nr;
833
834 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
835 if (!priv->data)
836 return -EINVAL;
837
838 priv->iobase = pdata->iobase;
839 priv->phy_mode = pdata->phy_interface;
840 priv->max_speed = pdata->max_speed;
841
842 ret = priv->data->get_pinmode(priv);
843 if (ret) {
844 dev_err(dev, "Invalid phy-mode\n");
845 return -EINVAL;
846 }
847
848 for (nc = 0; nc < priv->nclks; nc++) {
849 ret = clk_enable(&priv->clk[nc]);
850 if (ret) {
851 dev_err(dev, "Failed to enable clk: %d\n", ret);
852 goto out_clk_release;
853 }
854 }
855
856 for (nr = 0; nr < priv->nrsts; nr++) {
857 ret = reset_deassert(&priv->rst[nr]);
858 if (ret) {
859 dev_err(dev, "Failed to deassert reset: %d\n", ret);
860 goto out_reset_release;
861 }
862 }
863
864 ave_reset(priv);
865
866 ret = ave_mdiobus_init(priv, dev->name);
867 if (ret) {
868 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
869 goto out_reset_release;
870 }
871
872 priv->bus = miiphy_get_dev_by_name(dev->name);
873
874 ret = ave_phy_init(priv, dev);
875 if (ret) {
876 dev_err(dev, "Failed to initialize phy: %d\n", ret);
877 goto out_mdiobus_release;
878 }
879
880 return 0;
881
882 out_mdiobus_release:
883 mdio_unregister(priv->bus);
884 mdio_free(priv->bus);
885 out_reset_release:
886 reset_release_all(priv->rst, nr);
887 out_clk_release:
888 clk_release_all(priv->clk, nc);
889
890 return ret;
891 }
892
ave_remove(struct udevice * dev)893 static int ave_remove(struct udevice *dev)
894 {
895 struct ave_private *priv = dev_get_priv(dev);
896
897 free(priv->phydev);
898 mdio_unregister(priv->bus);
899 mdio_free(priv->bus);
900 reset_release_all(priv->rst, priv->nrsts);
901 clk_release_all(priv->clk, priv->nclks);
902
903 return 0;
904 }
905
906 static const struct eth_ops ave_ops = {
907 .start = ave_start,
908 .stop = ave_stop,
909 .send = ave_send,
910 .recv = ave_recv,
911 .free_pkt = ave_free_packet,
912 .write_hwaddr = ave_write_hwaddr,
913 };
914
915 static const struct ave_soc_data ave_pro4_data = {
916 .is_desc_64bit = false,
917 .clock_names = {
918 "gio", "ether", "ether-gb", "ether-phy",
919 },
920 .reset_names = {
921 "gio", "ether",
922 },
923 .get_pinmode = ave_pro4_get_pinmode,
924 };
925
926 static const struct ave_soc_data ave_pxs2_data = {
927 .is_desc_64bit = false,
928 .clock_names = {
929 "ether",
930 },
931 .reset_names = {
932 "ether",
933 },
934 .get_pinmode = ave_pro4_get_pinmode,
935 };
936
937 static const struct ave_soc_data ave_ld11_data = {
938 .is_desc_64bit = false,
939 .clock_names = {
940 "ether",
941 },
942 .reset_names = {
943 "ether",
944 },
945 .get_pinmode = ave_ld11_get_pinmode,
946 };
947
948 static const struct ave_soc_data ave_ld20_data = {
949 .is_desc_64bit = true,
950 .clock_names = {
951 "ether",
952 },
953 .reset_names = {
954 "ether",
955 },
956 .get_pinmode = ave_ld20_get_pinmode,
957 };
958
959 static const struct ave_soc_data ave_pxs3_data = {
960 .is_desc_64bit = false,
961 .clock_names = {
962 "ether",
963 },
964 .reset_names = {
965 "ether",
966 },
967 .get_pinmode = ave_pxs3_get_pinmode,
968 };
969
970 static const struct udevice_id ave_ids[] = {
971 {
972 .compatible = "socionext,uniphier-pro4-ave4",
973 .data = (ulong)&ave_pro4_data,
974 },
975 {
976 .compatible = "socionext,uniphier-pxs2-ave4",
977 .data = (ulong)&ave_pxs2_data,
978 },
979 {
980 .compatible = "socionext,uniphier-ld11-ave4",
981 .data = (ulong)&ave_ld11_data,
982 },
983 {
984 .compatible = "socionext,uniphier-ld20-ave4",
985 .data = (ulong)&ave_ld20_data,
986 },
987 {
988 .compatible = "socionext,uniphier-pxs3-ave4",
989 .data = (ulong)&ave_pxs3_data,
990 },
991 { /* Sentinel */ }
992 };
993
994 U_BOOT_DRIVER(ave) = {
995 .name = "ave",
996 .id = UCLASS_ETH,
997 .of_match = ave_ids,
998 .probe = ave_probe,
999 .remove = ave_remove,
1000 .of_to_plat = ave_of_to_plat,
1001 .ops = &ave_ops,
1002 .priv_auto = sizeof(struct ave_private),
1003 .plat_auto = sizeof(struct eth_pdata),
1004 };
1005