1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <net.h>
14 #include <malloc.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <phy.h>
18 #include <miiphy.h>
19 #include <wait_bit.h>
20 #include <linux/delay.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /* Link setup */
25 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
26 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
27 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
28 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
29
30 /* Interrupt Status/Enable/Mask Registers bit definitions */
31 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
32 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
33
34 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
35 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
36
37 /* Transmitter Configuration (TC) Register bit definitions */
38 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
39
40 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
41
42 /* MDIO Management Configuration (MC) Register bit definitions */
43 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
44
45 /* MDIO Management Control Register (MCR) Register bit definitions */
46 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
47 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
48 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
49 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
50 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
51 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
52 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
53 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
54
55 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
56
57 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
58
59 /* DMA macros */
60 /* Bitmasks of XAXIDMA_CR_OFFSET register */
61 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
62 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
63
64 /* Bitmasks of XAXIDMA_SR_OFFSET register */
65 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
66
67 /* Bitmask for interrupts */
68 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
69 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
70 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
71
72 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
73 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
74 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
75
76 #define DMAALIGN 128
77
78 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
79
80 /* Reflect dma offsets */
81 struct axidma_reg {
82 u32 control; /* DMACR */
83 u32 status; /* DMASR */
84 u32 current; /* CURDESC low 32 bit */
85 u32 current_hi; /* CURDESC high 32 bit */
86 u32 tail; /* TAILDESC low 32 bit */
87 u32 tail_hi; /* TAILDESC high 32 bit */
88 };
89
90 /* Private driver structures */
91 struct axidma_priv {
92 struct axidma_reg *dmatx;
93 struct axidma_reg *dmarx;
94 int phyaddr;
95 struct axi_regs *iobase;
96 phy_interface_t interface;
97 struct phy_device *phydev;
98 struct mii_dev *bus;
99 u8 eth_hasnobuf;
100 int phy_of_handle;
101 };
102
103 /* BD descriptors */
104 struct axidma_bd {
105 u32 next_desc; /* Next descriptor pointer */
106 u32 next_desc_msb;
107 u32 buf_addr; /* Buffer address */
108 u32 buf_addr_msb;
109 u32 reserved3;
110 u32 reserved4;
111 u32 cntrl; /* Control */
112 u32 status; /* Status */
113 u32 app0;
114 u32 app1; /* TX start << 16 | insert */
115 u32 app2; /* TX csum seed */
116 u32 app3;
117 u32 app4;
118 u32 sw_id_offset;
119 u32 reserved5;
120 u32 reserved6;
121 };
122
123 /* Static BDs - driver uses only one BD */
124 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
125 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
126
127 struct axi_regs {
128 u32 reserved[3];
129 u32 is; /* 0xC: Interrupt status */
130 u32 reserved2;
131 u32 ie; /* 0x14: Interrupt enable */
132 u32 reserved3[251];
133 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
134 u32 tc; /* 0x408: Tx Configuration */
135 u32 reserved4;
136 u32 emmc; /* 0x410: EMAC mode configuration */
137 u32 reserved5[59];
138 u32 mdio_mc; /* 0x500: MII Management Config */
139 u32 mdio_mcr; /* 0x504: MII Management Control */
140 u32 mdio_mwd; /* 0x508: MII Management Write Data */
141 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
142 u32 reserved6[124];
143 u32 uaw0; /* 0x700: Unicast address word 0 */
144 u32 uaw1; /* 0x704: Unicast address word 1 */
145 };
146
147 /* Use MII register 1 (MII status register) to detect PHY */
148 #define PHY_DETECT_REG 1
149
150 /*
151 * Mask used to verify certain PHY features (or register contents)
152 * in the register above:
153 * 0x1000: 10Mbps full duplex support
154 * 0x0800: 10Mbps half duplex support
155 * 0x0008: Auto-negotiation support
156 */
157 #define PHY_DETECT_MASK 0x1808
158
mdio_wait(struct axi_regs * regs)159 static inline int mdio_wait(struct axi_regs *regs)
160 {
161 u32 timeout = 200;
162
163 /* Wait till MDIO interface is ready to accept a new transaction. */
164 while (timeout && (!(readl(®s->mdio_mcr)
165 & XAE_MDIO_MCR_READY_MASK))) {
166 timeout--;
167 udelay(1);
168 }
169 if (!timeout) {
170 printf("%s: Timeout\n", __func__);
171 return 1;
172 }
173 return 0;
174 }
175
176 /**
177 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
178 * @bd: pointer to BD descriptor structure
179 * @desc: Address offset of DMA descriptors
180 *
181 * This function writes the value into the corresponding Axi DMA register.
182 */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)183 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
184 {
185 #if defined(CONFIG_PHYS_64BIT)
186 writeq((unsigned long)bd, desc);
187 #else
188 writel((u32)bd, desc);
189 #endif
190 }
191
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)192 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
193 u16 *val)
194 {
195 struct axi_regs *regs = priv->iobase;
196 u32 mdioctrlreg = 0;
197
198 if (mdio_wait(regs))
199 return 1;
200
201 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
202 XAE_MDIO_MCR_PHYAD_MASK) |
203 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
204 & XAE_MDIO_MCR_REGAD_MASK) |
205 XAE_MDIO_MCR_INITIATE_MASK |
206 XAE_MDIO_MCR_OP_READ_MASK;
207
208 writel(mdioctrlreg, ®s->mdio_mcr);
209
210 if (mdio_wait(regs))
211 return 1;
212
213 /* Read data */
214 *val = readl(®s->mdio_mrd);
215 return 0;
216 }
217
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)218 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
219 u32 data)
220 {
221 struct axi_regs *regs = priv->iobase;
222 u32 mdioctrlreg = 0;
223
224 if (mdio_wait(regs))
225 return 1;
226
227 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
228 XAE_MDIO_MCR_PHYAD_MASK) |
229 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
230 & XAE_MDIO_MCR_REGAD_MASK) |
231 XAE_MDIO_MCR_INITIATE_MASK |
232 XAE_MDIO_MCR_OP_WRITE_MASK;
233
234 /* Write data */
235 writel(data, ®s->mdio_mwd);
236
237 writel(mdioctrlreg, ®s->mdio_mcr);
238
239 if (mdio_wait(regs))
240 return 1;
241
242 return 0;
243 }
244
axiemac_phy_init(struct udevice * dev)245 static int axiemac_phy_init(struct udevice *dev)
246 {
247 u16 phyreg;
248 int i;
249 u32 ret;
250 struct axidma_priv *priv = dev_get_priv(dev);
251 struct axi_regs *regs = priv->iobase;
252 struct phy_device *phydev;
253
254 u32 supported = SUPPORTED_10baseT_Half |
255 SUPPORTED_10baseT_Full |
256 SUPPORTED_100baseT_Half |
257 SUPPORTED_100baseT_Full |
258 SUPPORTED_1000baseT_Half |
259 SUPPORTED_1000baseT_Full;
260
261 /* Set default MDIO divisor */
262 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
263
264 if (priv->phyaddr == -1) {
265 /* Detect the PHY address */
266 for (i = 31; i >= 0; i--) {
267 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
268 if (!ret && (phyreg != 0xFFFF) &&
269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
270 /* Found a valid PHY address */
271 priv->phyaddr = i;
272 debug("axiemac: Found valid phy address, %x\n",
273 i);
274 break;
275 }
276 }
277 }
278
279 /* Interface - look at tsec */
280 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
281
282 phydev->supported &= supported;
283 phydev->advertising = phydev->supported;
284 priv->phydev = phydev;
285 if (priv->phy_of_handle)
286 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
287 phy_config(phydev);
288
289 return 0;
290 }
291
292 /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)293 static int setup_phy(struct udevice *dev)
294 {
295 u16 temp;
296 u32 speed, emmc_reg, ret;
297 struct axidma_priv *priv = dev_get_priv(dev);
298 struct axi_regs *regs = priv->iobase;
299 struct phy_device *phydev = priv->phydev;
300
301 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
302 /*
303 * In SGMII cases the isolate bit might set
304 * after DMA and ethernet resets and hence
305 * check and clear if set.
306 */
307 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
308 if (ret)
309 return 0;
310 if (temp & BMCR_ISOLATE) {
311 temp &= ~BMCR_ISOLATE;
312 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
313 if (ret)
314 return 0;
315 }
316 }
317
318 if (phy_startup(phydev)) {
319 printf("axiemac: could not initialize PHY %s\n",
320 phydev->dev->name);
321 return 0;
322 }
323 if (!phydev->link) {
324 printf("%s: No link.\n", phydev->dev->name);
325 return 0;
326 }
327
328 switch (phydev->speed) {
329 case 1000:
330 speed = XAE_EMMC_LINKSPD_1000;
331 break;
332 case 100:
333 speed = XAE_EMMC_LINKSPD_100;
334 break;
335 case 10:
336 speed = XAE_EMMC_LINKSPD_10;
337 break;
338 default:
339 return 0;
340 }
341
342 /* Setup the emac for the phy speed */
343 emmc_reg = readl(®s->emmc);
344 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
345 emmc_reg |= speed;
346
347 /* Write new speed setting out to Axi Ethernet */
348 writel(emmc_reg, ®s->emmc);
349
350 /*
351 * Setting the operating speed of the MAC needs a delay. There
352 * doesn't seem to be register to poll, so please consider this
353 * during your application design.
354 */
355 udelay(1);
356
357 return 1;
358 }
359
360 /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)361 static void axiemac_stop(struct udevice *dev)
362 {
363 struct axidma_priv *priv = dev_get_priv(dev);
364 u32 temp;
365
366 /* Stop the hardware */
367 temp = readl(&priv->dmatx->control);
368 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
369 writel(temp, &priv->dmatx->control);
370
371 temp = readl(&priv->dmarx->control);
372 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
373 writel(temp, &priv->dmarx->control);
374
375 debug("axiemac: Halted\n");
376 }
377
axi_ethernet_init(struct axidma_priv * priv)378 static int axi_ethernet_init(struct axidma_priv *priv)
379 {
380 struct axi_regs *regs = priv->iobase;
381 int err;
382
383 /*
384 * Check the status of the MgtRdy bit in the interrupt status
385 * registers. This must be done to allow the MGT clock to become stable
386 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
387 * will be valid until this bit is valid.
388 * The bit is always a 1 for all other PHY interfaces.
389 * Interrupt status and enable registers are not available in non
390 * processor mode and hence bypass in this mode
391 */
392 if (!priv->eth_hasnobuf) {
393 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
394 true, 200, false);
395 if (err) {
396 printf("%s: Timeout\n", __func__);
397 return 1;
398 }
399
400 /*
401 * Stop the device and reset HW
402 * Disable interrupts
403 */
404 writel(0, ®s->ie);
405 }
406
407 /* Disable the receiver */
408 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
409
410 /*
411 * Stopping the receiver in mid-packet causes a dropped packet
412 * indication from HW. Clear it.
413 */
414 if (!priv->eth_hasnobuf) {
415 /* Set the interrupt status register to clear the interrupt */
416 writel(XAE_INT_RXRJECT_MASK, ®s->is);
417 }
418
419 /* Setup HW */
420 /* Set default MDIO divisor */
421 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
422
423 debug("axiemac: InitHw done\n");
424 return 0;
425 }
426
axiemac_write_hwaddr(struct udevice * dev)427 static int axiemac_write_hwaddr(struct udevice *dev)
428 {
429 struct eth_pdata *pdata = dev_get_plat(dev);
430 struct axidma_priv *priv = dev_get_priv(dev);
431 struct axi_regs *regs = priv->iobase;
432
433 /* Set the MAC address */
434 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
435 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
436 writel(val, ®s->uaw0);
437
438 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
439 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
440 writel(val, ®s->uaw1);
441 return 0;
442 }
443
444 /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)445 static void axi_dma_init(struct axidma_priv *priv)
446 {
447 u32 timeout = 500;
448
449 /* Reset the engine so the hardware starts from a known state */
450 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
451 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
452
453 /* At the initialization time, hardware should finish reset quickly */
454 while (timeout--) {
455 /* Check transmit/receive channel */
456 /* Reset is done when the reset bit is low */
457 if (!((readl(&priv->dmatx->control) |
458 readl(&priv->dmarx->control))
459 & XAXIDMA_CR_RESET_MASK)) {
460 break;
461 }
462 }
463 if (!timeout)
464 printf("%s: Timeout\n", __func__);
465 }
466
axiemac_start(struct udevice * dev)467 static int axiemac_start(struct udevice *dev)
468 {
469 struct axidma_priv *priv = dev_get_priv(dev);
470 struct axi_regs *regs = priv->iobase;
471 u32 temp;
472
473 debug("axiemac: Init started\n");
474 /*
475 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
476 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
477 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
478 * would ensure a reset of AxiEthernet.
479 */
480 axi_dma_init(priv);
481
482 /* Initialize AxiEthernet hardware. */
483 if (axi_ethernet_init(priv))
484 return -1;
485
486 /* Disable all RX interrupts before RxBD space setup */
487 temp = readl(&priv->dmarx->control);
488 temp &= ~XAXIDMA_IRQ_ALL_MASK;
489 writel(temp, &priv->dmarx->control);
490
491 /* Start DMA RX channel. Now it's ready to receive data.*/
492 axienet_dma_write(&rx_bd, &priv->dmarx->current);
493
494 /* Setup the BD. */
495 memset(&rx_bd, 0, sizeof(rx_bd));
496 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
497 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
498 #if defined(CONFIG_PHYS_64BIT)
499 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
500 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
501 #endif
502 rx_bd.cntrl = sizeof(rxframe);
503 /* Flush the last BD so DMA core could see the updates */
504 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
505
506 /* It is necessary to flush rxframe because if you don't do it
507 * then cache can contain uninitialized data */
508 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
509
510 /* Start the hardware */
511 temp = readl(&priv->dmarx->control);
512 temp |= XAXIDMA_CR_RUNSTOP_MASK;
513 writel(temp, &priv->dmarx->control);
514
515 /* Rx BD is ready - start */
516 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
517
518 /* Enable TX */
519 writel(XAE_TC_TX_MASK, ®s->tc);
520 /* Enable RX */
521 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
522
523 /* PHY setup */
524 if (!setup_phy(dev)) {
525 axiemac_stop(dev);
526 return -1;
527 }
528
529 debug("axiemac: Init complete\n");
530 return 0;
531 }
532
axiemac_send(struct udevice * dev,void * ptr,int len)533 static int axiemac_send(struct udevice *dev, void *ptr, int len)
534 {
535 struct axidma_priv *priv = dev_get_priv(dev);
536 u32 timeout;
537
538 if (len > PKTSIZE_ALIGN)
539 len = PKTSIZE_ALIGN;
540
541 /* Flush packet to main memory to be trasfered by DMA */
542 flush_cache((phys_addr_t)ptr, len);
543
544 /* Setup Tx BD */
545 memset(&tx_bd, 0, sizeof(tx_bd));
546 /* At the end of the ring, link the last BD back to the top */
547 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
548 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
549 #if defined(CONFIG_PHYS_64BIT)
550 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
551 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
552 #endif
553 /* Save len */
554 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
555 XAXIDMA_BD_CTRL_TXEOF_MASK;
556
557 /* Flush the last BD so DMA core could see the updates */
558 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
559
560 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
561 u32 temp;
562 axienet_dma_write(&tx_bd, &priv->dmatx->current);
563 /* Start the hardware */
564 temp = readl(&priv->dmatx->control);
565 temp |= XAXIDMA_CR_RUNSTOP_MASK;
566 writel(temp, &priv->dmatx->control);
567 }
568
569 /* Start transfer */
570 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
571
572 /* Wait for transmission to complete */
573 debug("axiemac: Waiting for tx to be done\n");
574 timeout = 200;
575 while (timeout && (!(readl(&priv->dmatx->status) &
576 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
577 timeout--;
578 udelay(1);
579 }
580 if (!timeout) {
581 printf("%s: Timeout\n", __func__);
582 return 1;
583 }
584
585 debug("axiemac: Sending complete\n");
586 return 0;
587 }
588
isrxready(struct axidma_priv * priv)589 static int isrxready(struct axidma_priv *priv)
590 {
591 u32 status;
592
593 /* Read pending interrupts */
594 status = readl(&priv->dmarx->status);
595
596 /* Acknowledge pending interrupts */
597 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
598
599 /*
600 * If Reception done interrupt is asserted, call RX call back function
601 * to handle the processed BDs and then raise the according flag.
602 */
603 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
604 return 1;
605
606 return 0;
607 }
608
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)609 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
610 {
611 u32 length;
612 struct axidma_priv *priv = dev_get_priv(dev);
613 u32 temp;
614
615 /* Wait for an incoming packet */
616 if (!isrxready(priv))
617 return -1;
618
619 debug("axiemac: RX data ready\n");
620
621 /* Disable IRQ for a moment till packet is handled */
622 temp = readl(&priv->dmarx->control);
623 temp &= ~XAXIDMA_IRQ_ALL_MASK;
624 writel(temp, &priv->dmarx->control);
625 if (!priv->eth_hasnobuf)
626 length = rx_bd.app4 & 0xFFFF; /* max length mask */
627 else
628 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
629
630 #ifdef DEBUG
631 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
632 #endif
633
634 *packetp = rxframe;
635 return length;
636 }
637
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)638 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
639 {
640 struct axidma_priv *priv = dev_get_priv(dev);
641
642 #ifdef DEBUG
643 /* It is useful to clear buffer to be sure that it is consistent */
644 memset(rxframe, 0, sizeof(rxframe));
645 #endif
646 /* Setup RxBD */
647 /* Clear the whole buffer and setup it again - all flags are cleared */
648 memset(&rx_bd, 0, sizeof(rx_bd));
649 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
650 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
651 #if defined(CONFIG_PHYS_64BIT)
652 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
653 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
654 #endif
655 rx_bd.cntrl = sizeof(rxframe);
656
657 /* Write bd to HW */
658 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
659
660 /* It is necessary to flush rxframe because if you don't do it
661 * then cache will contain previous packet */
662 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
663
664 /* Rx BD is ready - start again */
665 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
666
667 debug("axiemac: RX completed, framelength = %d\n", length);
668
669 return 0;
670 }
671
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)672 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
673 int devad, int reg)
674 {
675 int ret;
676 u16 value;
677
678 ret = phyread(bus->priv, addr, reg, &value);
679 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
680 value, ret);
681 return value;
682 }
683
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)684 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
685 int reg, u16 value)
686 {
687 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
688 return phywrite(bus->priv, addr, reg, value);
689 }
690
axi_emac_probe(struct udevice * dev)691 static int axi_emac_probe(struct udevice *dev)
692 {
693 struct axidma_priv *priv = dev_get_priv(dev);
694 int ret;
695
696 priv->bus = mdio_alloc();
697 priv->bus->read = axiemac_miiphy_read;
698 priv->bus->write = axiemac_miiphy_write;
699 priv->bus->priv = priv;
700
701 ret = mdio_register_seq(priv->bus, dev_seq(dev));
702 if (ret)
703 return ret;
704
705 axiemac_phy_init(dev);
706
707 return 0;
708 }
709
axi_emac_remove(struct udevice * dev)710 static int axi_emac_remove(struct udevice *dev)
711 {
712 struct axidma_priv *priv = dev_get_priv(dev);
713
714 free(priv->phydev);
715 mdio_unregister(priv->bus);
716 mdio_free(priv->bus);
717
718 return 0;
719 }
720
721 static const struct eth_ops axi_emac_ops = {
722 .start = axiemac_start,
723 .send = axiemac_send,
724 .recv = axiemac_recv,
725 .free_pkt = axiemac_free_pkt,
726 .stop = axiemac_stop,
727 .write_hwaddr = axiemac_write_hwaddr,
728 };
729
axi_emac_of_to_plat(struct udevice * dev)730 static int axi_emac_of_to_plat(struct udevice *dev)
731 {
732 struct eth_pdata *pdata = dev_get_plat(dev);
733 struct axidma_priv *priv = dev_get_priv(dev);
734 int node = dev_of_offset(dev);
735 int offset = 0;
736 const char *phy_mode;
737
738 pdata->iobase = dev_read_addr(dev);
739 priv->iobase = (struct axi_regs *)pdata->iobase;
740
741 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
742 "axistream-connected");
743 if (offset <= 0) {
744 printf("%s: axistream is not found\n", __func__);
745 return -EINVAL;
746 }
747 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
748 offset, "reg");
749 if (!priv->dmatx) {
750 printf("%s: axi_dma register space not found\n", __func__);
751 return -EINVAL;
752 }
753 /* RX channel offset is 0x30 */
754 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
755
756 priv->phyaddr = -1;
757
758 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
759 if (offset > 0) {
760 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
761 priv->phy_of_handle = offset;
762 }
763
764 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
765 if (phy_mode)
766 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
767 if (pdata->phy_interface == -1) {
768 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
769 return -EINVAL;
770 }
771 priv->interface = pdata->phy_interface;
772
773 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
774 "xlnx,eth-hasnobuf");
775
776 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
777 priv->phyaddr, phy_string_for_interface(priv->interface));
778
779 return 0;
780 }
781
782 static const struct udevice_id axi_emac_ids[] = {
783 { .compatible = "xlnx,axi-ethernet-1.00.a" },
784 { }
785 };
786
787 U_BOOT_DRIVER(axi_emac) = {
788 .name = "axi_emac",
789 .id = UCLASS_ETH,
790 .of_match = axi_emac_ids,
791 .of_to_plat = axi_emac_of_to_plat,
792 .probe = axi_emac_probe,
793 .remove = axi_emac_remove,
794 .ops = &axi_emac_ops,
795 .priv_auto = sizeof(struct axidma_priv),
796 .plat_auto = sizeof(struct eth_pdata),
797 };
798