1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 */ 5 6 #ifndef __CVMX_L2C_DEFS_H_ 7 #define __CVMX_L2C_DEFS_H_ 8 9 #define CVMX_L2C_CFG 0x0001180080000000ull 10 #define CVMX_L2C_CTL 0x0001180080800000ull 11 12 /* 13 * Mapping is done starting from 0x11800.80000000 14 * Use _REL for relative mapping 15 */ 16 #define CVMX_L2C_CTL_REL 0x00800000 17 #define CVMX_L2C_BIG_CTL_REL 0x00800030 18 #define CVMX_L2C_TADX_INT_REL(i) (0x00a00028 + (((i) & 7) * 0x40000)) 19 #define CVMX_L2C_MCIX_INT_REL(i) (0x00c00028 + (((i) & 3) * 0x40000)) 20 21 /** 22 * cvmx_l2c_cfg 23 * 24 * Specify the RSL base addresses for the block 25 * 26 * L2C_CFG = L2C Configuration 27 * 28 * Description: 29 */ 30 union cvmx_l2c_cfg { 31 u64 u64; 32 struct cvmx_l2c_cfg_s { 33 u64 reserved_20_63 : 44; 34 u64 bstrun : 1; 35 u64 lbist : 1; 36 u64 xor_bank : 1; 37 u64 dpres1 : 1; 38 u64 dpres0 : 1; 39 u64 dfill_dis : 1; 40 u64 fpexp : 4; 41 u64 fpempty : 1; 42 u64 fpen : 1; 43 u64 idxalias : 1; 44 u64 mwf_crd : 4; 45 u64 rsp_arb_mode : 1; 46 u64 rfb_arb_mode : 1; 47 u64 lrf_arb_mode : 1; 48 } s; 49 }; 50 51 /** 52 * cvmx_l2c_ctl 53 * 54 * L2C_CTL = L2C Control 55 * 56 * 57 * Notes: 58 * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB. 59 * 60 * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE, 61 * and VBFDBE errors for the purposes of testing error handling code. When 62 * one (or both) of these bits are set a PL2 which misses in the L2 will fill 63 * with the appropriate error in the first 2 OWs of the fill. Software can 64 * determine which OW pair gets the error by choosing the desired fill order 65 * (address<6:5>). A PL2 which hits in the L2 will not inject any errors. 66 * Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss 67 * likely (if multiple processors are involved software must be careful to be 68 * sure no other processor or IO device can bring the block into the L2). 69 * 70 * To generate a VBFSBE or VBFDBE, software must first get the cache block 71 * into the cache with an error using a PL2 which misses the L2. Then a 72 * store partial to a portion of the cache block without the error must 73 * change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will 74 * trigger the VBFSBE/VBFDBE error. 75 */ 76 union cvmx_l2c_ctl { 77 u64 u64; 78 struct cvmx_l2c_ctl_s { 79 u64 reserved_29_63 : 35; 80 u64 rdf_fast : 1; 81 u64 disstgl2i : 1; 82 u64 l2dfsbe : 1; 83 u64 l2dfdbe : 1; 84 u64 discclk : 1; 85 u64 maxvab : 4; 86 u64 maxlfb : 4; 87 u64 rsp_arb_mode : 1; 88 u64 xmc_arb_mode : 1; 89 u64 reserved_2_13 : 12; 90 u64 disecc : 1; 91 u64 disidxalias : 1; 92 } s; 93 94 struct cvmx_l2c_ctl_cn73xx { 95 u64 reserved_32_63 : 32; 96 u64 ocla_qos : 3; 97 u64 reserved_28_28 : 1; 98 u64 disstgl2i : 1; 99 u64 reserved_25_26 : 2; 100 u64 discclk : 1; 101 u64 reserved_16_23 : 8; 102 u64 rsp_arb_mode : 1; 103 u64 xmc_arb_mode : 1; 104 u64 rdf_cnt : 8; 105 u64 reserved_4_5 : 2; 106 u64 disldwb : 1; 107 u64 dissblkdty : 1; 108 u64 disecc : 1; 109 u64 disidxalias : 1; 110 } cn73xx; 111 112 struct cvmx_l2c_ctl_cn73xx cn78xx; 113 }; 114 115 /** 116 * cvmx_l2c_big_ctl 117 * 118 * L2C_BIG_CTL = L2C Big memory control register 119 * 120 * 121 * Notes: 122 * (1) BIGRD interrupts can occur during normal operation as the PP's are 123 * allowed to prefetch to non-existent memory locations. Therefore, 124 * BIGRD is for informational purposes only. 125 * 126 * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB, 127 * and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR. 128 * Additionally, L2C_ERR_XMC will be loaded. 129 */ 130 union cvmx_l2c_big_ctl { 131 u64 u64; 132 struct cvmx_l2c_big_ctl_s { 133 u64 reserved_8_63 : 56; 134 u64 maxdram : 4; 135 u64 reserved_0_3 : 4; 136 } s; 137 struct cvmx_l2c_big_ctl_cn61xx { 138 u64 reserved_8_63 : 56; 139 u64 maxdram : 4; 140 u64 reserved_1_3 : 3; 141 u64 disable : 1; 142 } cn61xx; 143 struct cvmx_l2c_big_ctl_cn61xx cn63xx; 144 struct cvmx_l2c_big_ctl_cn61xx cn66xx; 145 struct cvmx_l2c_big_ctl_cn61xx cn68xx; 146 struct cvmx_l2c_big_ctl_cn61xx cn68xxp1; 147 struct cvmx_l2c_big_ctl_cn70xx { 148 u64 reserved_8_63 : 56; 149 u64 maxdram : 4; 150 u64 reserved_1_3 : 3; 151 u64 disbig : 1; 152 } cn70xx; 153 struct cvmx_l2c_big_ctl_cn70xx cn70xxp1; 154 struct cvmx_l2c_big_ctl_cn70xx cn73xx; 155 struct cvmx_l2c_big_ctl_cn70xx cn78xx; 156 struct cvmx_l2c_big_ctl_cn70xx cn78xxp1; 157 struct cvmx_l2c_big_ctl_cn61xx cnf71xx; 158 struct cvmx_l2c_big_ctl_cn70xx cnf75xx; 159 }; 160 161 struct rlevel_byte_data { 162 int delay; 163 int loop_total; 164 int loop_count; 165 int best; 166 u64 bm; 167 int bmerrs; 168 int sqerrs; 169 int bestsq; 170 }; 171 172 #endif 173