1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2015 Glider bvba
6 *
7 * Based on clk-rcar-gen3.c
8 *
9 * Copyright (C) 2015 Renesas Electronics Corp.
10 */
11
12 #include <common.h>
13 #include <clk-uclass.h>
14 #include <dm.h>
15 #include <linux/bitops.h>
16
17 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
18
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
21
22 enum clk_ids {
23 /* Core Clock Outputs exported to DT */
24 LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
25
26 /* External Input Clocks */
27 CLK_EXTAL,
28 CLK_EXTALR,
29
30 /* Internal Core Clocks */
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL2,
35 CLK_PLL3,
36 CLK_PLL4,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_SSPSRC,
45 CLK_RPCSRC,
46 CLK_RINT,
47
48 /* Module Clocks */
49 MOD_CLK_BASE
50 };
51
52 static const struct cpg_core_clk r8a7795_core_clks[] = {
53 /* External Clock Inputs */
54 DEF_INPUT("extal", CLK_EXTAL),
55 DEF_INPUT("extalr", CLK_EXTALR),
56
57 /* Internal Core Clocks */
58 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
59 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
60 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
61 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
64
65 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
66 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
67 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
69 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
73
74 DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
75 CLK_RPCSRC),
76 DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
77 R8A7795_CLK_RPC),
78
79 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
80
81 /* Core Clock Outputs */
82 DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
83 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
84 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
85 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
86 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
87 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
88 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
89 DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
90 DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
91 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
92 DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
93 DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
94 DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
95 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
96 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
97 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
98 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
99 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
100 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
101 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
102 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
103 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
104
105 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
106 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
107 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
108 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
109
110 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
111 DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
112 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
113 DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
114
115 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
116 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
117 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
118 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
119
120 DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
121
122 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
123 };
124
125 static const struct mssr_mod_clk r8a7795_mod_clks[] = {
126 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
127 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
128 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
129 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
130 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
131 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
132 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
133 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
134 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
135 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
136 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
137 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
138 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
139 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
140 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
141 DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
142 DEF_MOD("cmt3", 300, R8A7795_CLK_R),
143 DEF_MOD("cmt2", 301, R8A7795_CLK_R),
144 DEF_MOD("cmt1", 302, R8A7795_CLK_R),
145 DEF_MOD("cmt0", 303, R8A7795_CLK_R),
146 DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
147 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
148 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
149 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
150 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
151 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
152 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
153 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
154 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
155 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
156 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
157 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
158 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
159 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
160 DEF_MOD("rwdt", 402, R8A7795_CLK_R),
161 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
162 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
163 DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
164 DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
165 DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
166 DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
167 DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
168 DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
169 DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
170 DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
171 DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
172 DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
173 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
174 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
175 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
176 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
177 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
178 DEF_MOD("thermal", 522, R8A7795_CLK_CP),
179 DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
180 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
181 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
182 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
183 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
184 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
185 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
186 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
187 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
188 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
189 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
190 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
191 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
192 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
193 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
194 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
195 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
196 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
197 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
198 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
199 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
200 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
201 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
202 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
203 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
204 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
205 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
206 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
207 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
208 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
209 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
210 DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
211 DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
212 DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
213 DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
214 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
215 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
216 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
217 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
218 DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
219 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
220 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
221 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
222 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
223 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
224 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
225 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
226 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
227 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
228 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
229 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
230 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
231 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
232 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
233 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
234 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
235 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
236 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
237 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
238 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
239 DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
240 DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
241 DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
242 DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
243 DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
244 DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
245 DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
246 DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
247 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
248 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
249 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
250 DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
251 DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
252 DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
253 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
254 DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
255 DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
256 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
257 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
258 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
259 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
260 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
261 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
262 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
263 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
264 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
265 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
266 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
267 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
268 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
269 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
270 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
271 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
272 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
273 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
274 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
275 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
276 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
277 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
278 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
279 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
280 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
281 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
282 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
283 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
284 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
285 };
286
287 /*
288 * CPG Clock Data
289 */
290
291 /*
292 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
293 * 14 13 19 17 (MHz)
294 *-------------------------------------------------------------------------
295 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
296 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
297 * 0 0 1 0 Prohibited setting
298 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
299 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
300 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
301 * 0 1 1 0 Prohibited setting
302 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
303 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
304 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
305 * 1 0 1 0 Prohibited setting
306 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
307 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
308 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
309 * 1 1 1 0 Prohibited setting
310 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
311 */
312 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
313 (((md) & BIT(13)) >> 11) | \
314 (((md) & BIT(19)) >> 18) | \
315 (((md) & BIT(17)) >> 17))
316
317 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
318 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
319 { 1, 192, 1, 192, 1, 16, },
320 { 1, 192, 1, 128, 1, 16, },
321 { 0, /* Prohibited setting */ },
322 { 1, 192, 1, 192, 1, 16, },
323 { 1, 160, 1, 160, 1, 19, },
324 { 1, 160, 1, 106, 1, 19, },
325 { 0, /* Prohibited setting */ },
326 { 1, 160, 1, 160, 1, 19, },
327 { 1, 128, 1, 128, 1, 24, },
328 { 1, 128, 1, 84, 1, 24, },
329 { 0, /* Prohibited setting */ },
330 { 1, 128, 1, 128, 1, 24, },
331 { 2, 192, 1, 192, 1, 32, },
332 { 2, 192, 1, 128, 1, 32, },
333 { 0, /* Prohibited setting */ },
334 { 2, 192, 1, 192, 1, 32, },
335 };
336
337 static const struct mstp_stop_table r8a7795_mstp_table[] = {
338 { 0x00210000, 0x0, 0x00210000, 0 },
339 { 0xc3ec13a0, 0x0, 0xc3ec13a0, 0 },
340 { 0x040e2fdc, 0x2000, 0x040e2fdc, 0 },
341 { 0xf4cc7cdf, 0x400, 0xf4cc7cdf, 0 },
342 { 0x80000004, 0x180, 0x80000004, 0 },
343 { 0x40dfff46, 0x0, 0x40dfff46, 0 },
344 { 0xc5e8ccce, 0x0, 0xc5e8ccce, 0 },
345 { 0x39ffdf3f, 0x0, 0x39ffdf3f, 0 },
346 { 0x01f09ff6, 0x0, 0x01f09ff6, 0 },
347 { 0xfddfdffe, 0x0, 0xfddfdffe, 0 },
348 { 0xfffeffe0, 0x0, 0xfffeffe0, 0 },
349 { 0x00000000, 0x0, 0x00000000, 0 },
350 };
351
r8a7795_get_pll_config(const u32 cpg_mode)352 static const void *r8a7795_get_pll_config(const u32 cpg_mode)
353 {
354 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
355 }
356
357 static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
358 .core_clk = r8a7795_core_clks,
359 .core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
360 .mod_clk = r8a7795_mod_clks,
361 .mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
362 .mstp_table = r8a7795_mstp_table,
363 .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
364 .reset_node = "renesas,r8a7795-rst",
365 .reset_modemr_offset = CPG_RST_MODEMR,
366 .extalr_node = "extalr",
367 .mod_clk_base = MOD_CLK_BASE,
368 .clk_extal_id = CLK_EXTAL,
369 .clk_extalr_id = CLK_EXTALR,
370 .get_pll_config = r8a7795_get_pll_config,
371 };
372
373 static const struct udevice_id r8a7795_clk_ids[] = {
374 {
375 .compatible = "renesas,r8a7795-cpg-mssr",
376 .data = (ulong)&r8a7795_cpg_mssr_info
377 },
378 { }
379 };
380
381 U_BOOT_DRIVER(clk_r8a7795) = {
382 .name = "clk_r8a7795",
383 .id = UCLASS_CLK,
384 .of_match = r8a7795_clk_ids,
385 .priv_auto = sizeof(struct gen3_clk_priv),
386 .ops = &gen3_clk_ops,
387 .probe = gen3_clk_probe,
388 .remove = gen3_clk_remove,
389 };
390