1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW 7777
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8/*
9 * This setup is using a SCH-30841 card with AQR412 10G quad PHY.
10 *
11 * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
12 * Bottom port is port 0.
13 * Note that this is only usable for:
14 *  - QDS boards WITHOUT lane B rework,
15 *  - AQR412 card WITHOUT lane A -> lane C rework
16 *
17 * The following DTS assumes DIP SW5[1-3] = 000b.
18 */
19&slot1 {
20#include "fsl-sch-30841.dtsi"
21};
22
23&mscc_felix {
24	status = "okay";
25};
26
27&mscc_felix_port0 {
28	status = "okay";
29	phy-mode = "sgmii-2500";
30	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
31};
32
33&mscc_felix_port1 {
34	status = "okay";
35	phy-mode = "sgmii-2500";
36	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
37};
38
39&mscc_felix_port2 {
40	status = "okay";
41	phy-mode = "sgmii-2500";
42	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
43};
44
45&mscc_felix_port3 {
46	status = "okay";
47	phy-mode = "sgmii-2500";
48	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
49};
50