1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-am642.dtsi" 9#include "k3-am64-evm-ddr4-1600MTs.dtsi" 10#include "k3-am64-ddr.dtsi" 11 12/ { 13 chosen { 14 stdout-path = "serial2:115200n8"; 15 tick-timer = &timer1; 16 }; 17 18 aliases { 19 remoteproc0 = &sysctrler; 20 remoteproc1 = &a53_0; 21 }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* 2G RAM */ 26 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 27 28 }; 29 30 a53_0: a53@0 { 31 compatible = "ti,am654-rproc"; 32 reg = <0x00 0x00a90000 0x00 0x10>; 33 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, 34 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; 35 resets = <&k3_reset 135 0>; 36 clocks = <&k3_clks 61 0>; 37 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; 38 assigned-clock-parents = <&k3_clks 61 2>; 39 assigned-clock-rates = <200000000>, <1000000000>; 40 ti,sci = <&dmsc>; 41 ti,sci-proc-id = <32>; 42 ti,sci-host-id = <10>; 43 u-boot,dm-spl; 44 }; 45 46 reserved-memory { 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 51 secure_ddr: optee@9e800000 { 52 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 53 alignment = <0x1000>; 54 no-map; 55 }; 56 }; 57 58 clk_200mhz: dummy-clock-200mhz { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <200000000>; 62 u-boot,dm-spl; 63 }; 64 65 vtt_supply: vtt-supply { 66 compatible = "regulator-gpio"; 67 regulator-name = "vtt"; 68 regulator-min-microvolt = <0>; 69 regulator-max-microvolt = <3300000>; 70 gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 71 states = <0 0x0 3300000 0x1>; 72 u-boot,dm-spl; 73 }; 74}; 75 76&cbass_main { 77 sysctrler: sysctrler { 78 compatible = "ti,am654-system-controller"; 79 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; 80 mbox-names = "tx", "rx"; 81 u-boot,dm-spl; 82 }; 83}; 84 85&main_pmx0 { 86 u-boot,dm-spl; 87 main_uart0_pins_default: main-uart0-pins-default { 88 u-boot,dm-spl; 89 pinctrl-single,pins = < 90 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 91 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 92 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 93 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 94 >; 95 }; 96 97 main_uart1_pins_default: main-uart1-pins-default { 98 u-boot,dm-spl; 99 pinctrl-single,pins = < 100 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 101 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 102 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 103 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 104 >; 105 }; 106 107 main_mmc0_pins_default: main-mmc0-pins-default { 108 u-boot,dm-spl; 109 pinctrl-single,pins = < 110 AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ 111 AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ 112 AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ 113 AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ 114 AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ 115 AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ 116 AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ 117 AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ 118 AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ 119 AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ 120 AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ 121 >; 122 }; 123 124 main_mmc1_pins_default: main-mmc1-pins-default { 125 u-boot,dm-spl; 126 pinctrl-single,pins = < 127 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 128 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 129 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 130 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 131 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 132 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 133 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 134 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ 135 >; 136 }; 137 138 ddr_vtt_pins_default: ddr-vtt-pins-default { 139 u-boot,dm-spl; 140 pinctrl-single,pins = < 141 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ 142 >; 143 }; 144}; 145 146&dmsc { 147 mboxes= <&secure_proxy_main 0>, 148 <&secure_proxy_main 1>, 149 <&secure_proxy_main 0>; 150 mbox-names = "rx", "tx", "notify"; 151 ti,host-id = <35>; 152 ti,secure-host; 153}; 154 155&main_uart0 { 156 /delete-property/ power-domains; 157 /delete-property/ clocks; 158 /delete-property/ clock-names; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&main_uart0_pins_default>; 161 status = "okay"; 162}; 163 164&main_uart1 { 165 u-boot,dm-spl; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&main_uart1_pins_default>; 168}; 169 170&memorycontroller { 171 vtt-supply = <&vtt_supply>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&ddr_vtt_pins_default>; 174}; 175 176&sdhci0 { 177 /delete-property/ power-domains; 178 clocks = <&clk_200mhz>; 179 clock-names = "clk_xin"; 180 ti,driver-strength-ohm = <50>; 181 disable-wp; 182 pinctrl-0 = <&main_mmc0_pins_default>; 183}; 184 185&sdhci1 { 186 /delete-property/ power-domains; 187 clocks = <&clk_200mhz>; 188 clock-names = "clk_xin"; 189 ti,driver-strength-ohm = <50>; 190 disable-wp; 191 pinctrl-0 = <&main_mmc1_pins_default>; 192}; 193 194&main_gpio0 { 195 u-boot,dm-spl; 196 /delete-property/ power-domains; 197}; 198 199/* EEPROM might be read before SYSFW is available */ 200&main_i2c0 { 201 /delete-property/ power-domains; 202}; 203 204#include "k3-am642-evm-u-boot.dtsi" 205