1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Mingming Lee <mingming.lee@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/clock/mt8518-clk.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	compatible = "mediatek,mt8518";
15	interrupt-parent = <&sysirq>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19
20
21	topckgen: clock-controller@10000000 {
22		compatible = "mediatek,mt8518-topckgen";
23		reg = <0x10000000 0x1000>;
24		#clock-cells = <1>;
25	};
26
27	gic: interrupt-controller@0c000000 {
28		 compatible = "arm,gic-v3";
29		#interrupt-cells = <3>;
30		interrupt-parent = <&gic>;
31		interrupt-controller;
32		reg = <0xc000000 0x40000>,	/* GICD */
33			  <0xc100000 0x200000>; /* GICR */
34		interrupts = <GIC_PPI 9
35			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
36	};
37
38	sysirq: interrupt-controller@10200a80 {
39		compatible = "mediatek,sysirq";
40		interrupt-controller;
41		#interrupt-cells = <3>;
42		interrupt-parent = <&gic>;
43		reg = <0x10200a80 0x50>;
44	};
45
46	timer0: apxgpt@10008000 {
47		compatible = "mediatek,timer";
48		reg = <0x10008000 0x1000>;
49		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
50		clocks = <&topckgen CLK_TOP_CLK26M_D2>,
51			 <&topckgen CLK_TOP_CLK32K>,
52			 <&topckgen CLK_TOP_APXGPT>;
53		clock-names = "clk13m",
54			 "clk32k",
55			 "bus";
56	};
57
58	watchdog0: watchdog@10007000 {
59		compatible = "mediatek,wdt";
60		reg = <0x10007000 0x1000>;
61		interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
62		#reset-cells = <1>;
63		status = "disabled";
64		timeout-sec = <60>;
65		reset-on-timeout;
66	};
67
68	pinctrl: pinctrl@10005000 {
69		compatible = "mediatek,mt8518-pinctrl";
70		reg = <0x10005000 0x1000>;
71		gpio: gpio-controller {
72			gpio-controller;
73			#gpio-cells = <2>;
74		};
75	};
76
77	usb0: usb@11100000 {
78		compatible = "mediatek,mt8518-musb";
79		reg = <0x11100000 0x1000>;
80		reg-names = "control";
81		clocks = <&topckgen CLK_TOP_USB20_48M>,
82			 <&topckgen CLK_TOP_USBIF>,
83			 <&topckgen CLK_TOP_USB>;
84		clock-names = "usbpll", "usbmcu", "usb";
85		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
86		interrupt-names = "mc";
87		status = "okay";
88	};
89
90	mmc0: mmc@11120000 {
91		compatible = "mediatek,mt8516-mmc";
92		reg = <0x11120000 0x1000>;
93		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
94		clocks = <&topckgen CLK_TOP_MSDC0>,
95			<&topckgen CLK_TOP_MSDC0>,
96			<&topckgen CLK_TOP_MSDC0_B>;
97		clock-names = "source", "hclk", "source_cg";
98		status = "disabled";
99	};
100
101	uart0: serial@11005000 {
102		compatible = "mediatek,hsuart";
103		reg = <0x11005000 0x1000>;
104		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
105		clocks = <&topckgen CLK_TOP_UART0_SEL>,
106			<&topckgen CLK_TOP_UART0>;
107		clock-names = "baud", "bus";
108		status = "disabled";
109	};
110
111};
112