1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/omap.h>
14
15/ {
16	compatible = "ti,omap3430", "ti,omap3";
17	interrupt-parent = <&intc>;
18	#address-cells = <1>;
19	#size-cells = <1>;
20	chosen { };
21
22	aliases {
23		i2c0 = &i2c1;
24		i2c1 = &i2c2;
25		i2c2 = &i2c3;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			compatible = "arm,cortex-a8";
37			device_type = "cpu";
38			reg = <0x0>;
39
40			clocks = <&dpll1_ck>;
41			clock-names = "cpu";
42
43			clock-latency = <300000>; /* From omap-cpufreq driver */
44		};
45	};
46
47	pmu@54000000 {
48		compatible = "arm,cortex-a8-pmu";
49		reg = <0x54000000 0x800000>;
50		interrupts = <3>;
51		ti,hwmods = "debugss";
52	};
53
54	/*
55	 * The soc node represents the soc top level view. It is used for IPs
56	 * that are not memory mapped in the MPU view or for the MPU itself.
57	 */
58	soc {
59		compatible = "ti,omap-infra";
60		mpu {
61			compatible = "ti,omap3-mpu";
62			ti,hwmods = "mpu";
63		};
64
65		iva: iva {
66			compatible = "ti,iva2.2";
67			ti,hwmods = "iva";
68
69			dsp {
70				compatible = "ti,omap3-c64";
71			};
72		};
73	};
74
75	/*
76	 * XXX: Use a flat representation of the OMAP3 interconnect.
77	 * The real OMAP interconnect network is quite complex.
78	 * Since it will not bring real advantage to represent that in DT for
79	 * the moment, just use a fake OCP bus entry to represent the whole bus
80	 * hierarchy.
81	 */
82	ocp@68000000 {
83		compatible = "ti,omap3-l3-smx", "simple-bus";
84		reg = <0x68000000 0x10000>;
85		interrupts = <9 10>;
86		#address-cells = <1>;
87		#size-cells = <1>;
88		ranges;
89		ti,hwmods = "l3_main";
90
91		l4_core: l4@48000000 {
92			compatible = "ti,omap3-l4-core", "simple-bus";
93			#address-cells = <1>;
94			#size-cells = <1>;
95			ranges = <0 0x48000000 0x1000000>;
96
97			scm: scm@2000 {
98				compatible = "ti,omap3-scm", "simple-bus";
99				reg = <0x2000 0x2000>;
100				#address-cells = <1>;
101				#size-cells = <1>;
102				ranges = <0 0x2000 0x2000>;
103
104				omap3_pmx_core: pinmux@30 {
105					compatible = "ti,omap3-padconf",
106						     "pinctrl-single";
107					reg = <0x30 0x238>;
108					#address-cells = <1>;
109					#size-cells = <0>;
110					#pinctrl-cells = <1>;
111					#interrupt-cells = <1>;
112					interrupt-controller;
113					pinctrl-single,register-width = <16>;
114					pinctrl-single,function-mask = <0xff1f>;
115				};
116
117				scm_conf: scm_conf@270 {
118					compatible = "syscon", "simple-bus";
119					reg = <0x270 0x330>;
120					#address-cells = <1>;
121					#size-cells = <1>;
122					ranges = <0 0x270 0x330>;
123
124					pbias_regulator: pbias_regulator@2b0 {
125						compatible = "ti,pbias-omap3", "ti,pbias-omap";
126						reg = <0x2b0 0x4>;
127						syscon = <&scm_conf>;
128						pbias_mmc_reg: pbias_mmc_omap2430 {
129							regulator-name = "pbias_mmc_omap2430";
130							regulator-min-microvolt = <1800000>;
131							regulator-max-microvolt = <3000000>;
132						};
133					};
134
135					scm_clocks: clocks {
136						#address-cells = <1>;
137						#size-cells = <0>;
138					};
139				};
140
141				scm_clockdomains: clockdomains {
142				};
143
144				omap3_pmx_wkup: pinmux@a00 {
145					compatible = "ti,omap3-padconf",
146						     "pinctrl-single";
147					reg = <0xa00 0x5c>;
148					#address-cells = <1>;
149					#size-cells = <0>;
150					#pinctrl-cells = <1>;
151					#interrupt-cells = <1>;
152					interrupt-controller;
153					pinctrl-single,register-width = <16>;
154					pinctrl-single,function-mask = <0xff1f>;
155				};
156			};
157		};
158
159		aes: aes@480c5000 {
160			compatible = "ti,omap3-aes";
161			ti,hwmods = "aes";
162			reg = <0x480c5000 0x50>;
163			interrupts = <0>;
164			dmas = <&sdma 65 &sdma 66>;
165			dma-names = "tx", "rx";
166		};
167
168		prm: prm@48306000 {
169			compatible = "ti,omap3-prm";
170			reg = <0x48306000 0x4000>;
171			interrupts = <11>;
172
173			prm_clocks: clocks {
174				#address-cells = <1>;
175				#size-cells = <0>;
176			};
177
178			prm_clockdomains: clockdomains {
179			};
180		};
181
182		cm: cm@48004000 {
183			compatible = "ti,omap3-cm";
184			reg = <0x48004000 0x4000>;
185
186			cm_clocks: clocks {
187				#address-cells = <1>;
188				#size-cells = <0>;
189			};
190
191			cm_clockdomains: clockdomains {
192			};
193		};
194
195		counter32k: counter@48320000 {
196			compatible = "ti,omap-counter32k";
197			reg = <0x48320000 0x20>;
198			ti,hwmods = "counter_32k";
199		};
200
201		intc: interrupt-controller@48200000 {
202			compatible = "ti,omap3-intc";
203			interrupt-controller;
204			#interrupt-cells = <1>;
205			reg = <0x48200000 0x1000>;
206		};
207
208		sdma: dma-controller@48056000 {
209			compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
210			reg = <0x48056000 0x1000>;
211			interrupts = <12>,
212				     <13>,
213				     <14>,
214				     <15>;
215			#dma-cells = <1>;
216			dma-channels = <32>;
217			dma-requests = <96>;
218			ti,hwmods = "dma";
219		};
220
221		gpio1: gpio@48310000 {
222			compatible = "ti,omap3-gpio";
223			reg = <0x48310000 0x200>;
224			interrupts = <29>;
225			ti,hwmods = "gpio1";
226			ti,gpio-always-on;
227			gpio-controller;
228			#gpio-cells = <2>;
229			interrupt-controller;
230			#interrupt-cells = <2>;
231		};
232
233		gpio2: gpio@49050000 {
234			compatible = "ti,omap3-gpio";
235			reg = <0x49050000 0x200>;
236			interrupts = <30>;
237			ti,hwmods = "gpio2";
238			gpio-controller;
239			#gpio-cells = <2>;
240			interrupt-controller;
241			#interrupt-cells = <2>;
242		};
243
244		gpio3: gpio@49052000 {
245			compatible = "ti,omap3-gpio";
246			reg = <0x49052000 0x200>;
247			interrupts = <31>;
248			ti,hwmods = "gpio3";
249			gpio-controller;
250			#gpio-cells = <2>;
251			interrupt-controller;
252			#interrupt-cells = <2>;
253		};
254
255		gpio4: gpio@49054000 {
256			compatible = "ti,omap3-gpio";
257			reg = <0x49054000 0x200>;
258			interrupts = <32>;
259			ti,hwmods = "gpio4";
260			gpio-controller;
261			#gpio-cells = <2>;
262			interrupt-controller;
263			#interrupt-cells = <2>;
264		};
265
266		gpio5: gpio@49056000 {
267			compatible = "ti,omap3-gpio";
268			reg = <0x49056000 0x200>;
269			interrupts = <33>;
270			ti,hwmods = "gpio5";
271			gpio-controller;
272			#gpio-cells = <2>;
273			interrupt-controller;
274			#interrupt-cells = <2>;
275		};
276
277		gpio6: gpio@49058000 {
278			compatible = "ti,omap3-gpio";
279			reg = <0x49058000 0x200>;
280			interrupts = <34>;
281			ti,hwmods = "gpio6";
282			gpio-controller;
283			#gpio-cells = <2>;
284			interrupt-controller;
285			#interrupt-cells = <2>;
286		};
287
288		uart1: serial@4806a000 {
289			compatible = "ti,omap3-uart";
290			reg = <0x4806a000 0x2000>;
291			interrupts-extended = <&intc 72>;
292			dmas = <&sdma 49 &sdma 50>;
293			dma-names = "tx", "rx";
294			ti,hwmods = "uart1";
295			clock-frequency = <48000000>;
296		};
297
298		uart2: serial@4806c000 {
299			compatible = "ti,omap3-uart";
300			reg = <0x4806c000 0x400>;
301			interrupts-extended = <&intc 73>;
302			dmas = <&sdma 51 &sdma 52>;
303			dma-names = "tx", "rx";
304			ti,hwmods = "uart2";
305			clock-frequency = <48000000>;
306		};
307
308		uart3: serial@49020000 {
309			compatible = "ti,omap3-uart";
310			reg = <0x49020000 0x400>;
311			interrupts-extended = <&intc 74>;
312			dmas = <&sdma 53 &sdma 54>;
313			dma-names = "tx", "rx";
314			ti,hwmods = "uart3";
315			clock-frequency = <48000000>;
316		};
317
318		i2c1: i2c@48070000 {
319			compatible = "ti,omap3-i2c";
320			reg = <0x48070000 0x80>;
321			interrupts = <56>;
322			dmas = <&sdma 27 &sdma 28>;
323			dma-names = "tx", "rx";
324			#address-cells = <1>;
325			#size-cells = <0>;
326			ti,hwmods = "i2c1";
327		};
328
329		i2c2: i2c@48072000 {
330			compatible = "ti,omap3-i2c";
331			reg = <0x48072000 0x80>;
332			interrupts = <57>;
333			dmas = <&sdma 29 &sdma 30>;
334			dma-names = "tx", "rx";
335			#address-cells = <1>;
336			#size-cells = <0>;
337			ti,hwmods = "i2c2";
338		};
339
340		i2c3: i2c@48060000 {
341			compatible = "ti,omap3-i2c";
342			reg = <0x48060000 0x80>;
343			interrupts = <61>;
344			dmas = <&sdma 25 &sdma 26>;
345			dma-names = "tx", "rx";
346			#address-cells = <1>;
347			#size-cells = <0>;
348			ti,hwmods = "i2c3";
349		};
350
351		mailbox: mailbox@48094000 {
352			compatible = "ti,omap3-mailbox";
353			ti,hwmods = "mailbox";
354			reg = <0x48094000 0x200>;
355			interrupts = <26>;
356			#mbox-cells = <1>;
357			ti,mbox-num-users = <2>;
358			ti,mbox-num-fifos = <2>;
359			mbox_dsp: dsp {
360				ti,mbox-tx = <0 0 0>;
361				ti,mbox-rx = <1 0 0>;
362			};
363		};
364
365		mcspi1: spi@48098000 {
366			compatible = "ti,omap2-mcspi";
367			reg = <0x48098000 0x100>;
368			interrupts = <65>;
369			#address-cells = <1>;
370			#size-cells = <0>;
371			ti,hwmods = "mcspi1";
372			ti,spi-num-cs = <4>;
373			dmas = <&sdma 35>,
374			       <&sdma 36>,
375			       <&sdma 37>,
376			       <&sdma 38>,
377			       <&sdma 39>,
378			       <&sdma 40>,
379			       <&sdma 41>,
380			       <&sdma 42>;
381			dma-names = "tx0", "rx0", "tx1", "rx1",
382				    "tx2", "rx2", "tx3", "rx3";
383		};
384
385		mcspi2: spi@4809a000 {
386			compatible = "ti,omap2-mcspi";
387			reg = <0x4809a000 0x100>;
388			interrupts = <66>;
389			#address-cells = <1>;
390			#size-cells = <0>;
391			ti,hwmods = "mcspi2";
392			ti,spi-num-cs = <2>;
393			dmas = <&sdma 43>,
394			       <&sdma 44>,
395			       <&sdma 45>,
396			       <&sdma 46>;
397			dma-names = "tx0", "rx0", "tx1", "rx1";
398		};
399
400		mcspi3: spi@480b8000 {
401			compatible = "ti,omap2-mcspi";
402			reg = <0x480b8000 0x100>;
403			interrupts = <91>;
404			#address-cells = <1>;
405			#size-cells = <0>;
406			ti,hwmods = "mcspi3";
407			ti,spi-num-cs = <2>;
408			dmas = <&sdma 15>,
409			       <&sdma 16>,
410			       <&sdma 23>,
411			       <&sdma 24>;
412			dma-names = "tx0", "rx0", "tx1", "rx1";
413		};
414
415		mcspi4: spi@480ba000 {
416			compatible = "ti,omap2-mcspi";
417			reg = <0x480ba000 0x100>;
418			interrupts = <48>;
419			#address-cells = <1>;
420			#size-cells = <0>;
421			ti,hwmods = "mcspi4";
422			ti,spi-num-cs = <1>;
423			dmas = <&sdma 70>, <&sdma 71>;
424			dma-names = "tx0", "rx0";
425		};
426
427		hdqw1w: 1w@480b2000 {
428			compatible = "ti,omap3-1w";
429			reg = <0x480b2000 0x1000>;
430			interrupts = <58>;
431			ti,hwmods = "hdq1w";
432		};
433
434		mmc1: mmc@4809c000 {
435			compatible = "ti,omap3-hsmmc";
436			reg = <0x4809c000 0x200>;
437			interrupts = <83>;
438			ti,hwmods = "mmc1";
439			ti,dual-volt;
440			dmas = <&sdma 61>, <&sdma 62>;
441			dma-names = "tx", "rx";
442			pbias-supply = <&pbias_mmc_reg>;
443		};
444
445		mmc2: mmc@480b4000 {
446			compatible = "ti,omap3-hsmmc";
447			reg = <0x480b4000 0x200>;
448			interrupts = <86>;
449			ti,hwmods = "mmc2";
450			dmas = <&sdma 47>, <&sdma 48>;
451			dma-names = "tx", "rx";
452		};
453
454		mmc3: mmc@480ad000 {
455			compatible = "ti,omap3-hsmmc";
456			reg = <0x480ad000 0x200>;
457			interrupts = <94>;
458			ti,hwmods = "mmc3";
459			dmas = <&sdma 77>, <&sdma 78>;
460			dma-names = "tx", "rx";
461		};
462
463		mmu_isp: mmu@480bd400 {
464			#iommu-cells = <0>;
465			compatible = "ti,omap2-iommu";
466			reg = <0x480bd400 0x80>;
467			interrupts = <24>;
468			ti,hwmods = "mmu_isp";
469			ti,#tlb-entries = <8>;
470		};
471
472		mmu_iva: mmu@5d000000 {
473			#iommu-cells = <0>;
474			compatible = "ti,omap2-iommu";
475			reg = <0x5d000000 0x80>;
476			interrupts = <28>;
477			ti,hwmods = "mmu_iva";
478			status = "disabled";
479		};
480
481		wdt2: wdt@48314000 {
482			compatible = "ti,omap3-wdt";
483			reg = <0x48314000 0x80>;
484			ti,hwmods = "wd_timer2";
485		};
486
487		mcbsp1: mcbsp@48074000 {
488			compatible = "ti,omap3-mcbsp";
489			reg = <0x48074000 0xff>;
490			reg-names = "mpu";
491			interrupts = <16>, /* OCP compliant interrupt */
492				     <59>, /* TX interrupt */
493				     <60>; /* RX interrupt */
494			interrupt-names = "common", "tx", "rx";
495			ti,buffer-size = <128>;
496			ti,hwmods = "mcbsp1";
497			dmas = <&sdma 31>,
498			       <&sdma 32>;
499			dma-names = "tx", "rx";
500			clocks = <&mcbsp1_fck>;
501			clock-names = "fck";
502			status = "disabled";
503		};
504
505		mcbsp2: mcbsp@49022000 {
506			compatible = "ti,omap3-mcbsp";
507			reg = <0x49022000 0xff>,
508			      <0x49028000 0xff>;
509			reg-names = "mpu", "sidetone";
510			interrupts = <17>, /* OCP compliant interrupt */
511				     <62>, /* TX interrupt */
512				     <63>, /* RX interrupt */
513				     <4>;  /* Sidetone */
514			interrupt-names = "common", "tx", "rx", "sidetone";
515			ti,buffer-size = <1280>;
516			ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
517			dmas = <&sdma 33>,
518			       <&sdma 34>;
519			dma-names = "tx", "rx";
520			clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
521			clock-names = "fck", "ick";
522			status = "disabled";
523		};
524
525		mcbsp3: mcbsp@49024000 {
526			compatible = "ti,omap3-mcbsp";
527			reg = <0x49024000 0xff>,
528			      <0x4902a000 0xff>;
529			reg-names = "mpu", "sidetone";
530			interrupts = <22>, /* OCP compliant interrupt */
531				     <89>, /* TX interrupt */
532				     <90>, /* RX interrupt */
533				     <5>;  /* Sidetone */
534			interrupt-names = "common", "tx", "rx", "sidetone";
535			ti,buffer-size = <128>;
536			ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
537			dmas = <&sdma 17>,
538			       <&sdma 18>;
539			dma-names = "tx", "rx";
540			clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
541			clock-names = "fck", "ick";
542			status = "disabled";
543		};
544
545		mcbsp4: mcbsp@49026000 {
546			compatible = "ti,omap3-mcbsp";
547			reg = <0x49026000 0xff>;
548			reg-names = "mpu";
549			interrupts = <23>, /* OCP compliant interrupt */
550				     <54>, /* TX interrupt */
551				     <55>; /* RX interrupt */
552			interrupt-names = "common", "tx", "rx";
553			ti,buffer-size = <128>;
554			ti,hwmods = "mcbsp4";
555			dmas = <&sdma 19>,
556			       <&sdma 20>;
557			dma-names = "tx", "rx";
558			clocks = <&mcbsp4_fck>;
559			clock-names = "fck";
560			#sound-dai-cells = <0>;
561			status = "disabled";
562		};
563
564		mcbsp5: mcbsp@48096000 {
565			compatible = "ti,omap3-mcbsp";
566			reg = <0x48096000 0xff>;
567			reg-names = "mpu";
568			interrupts = <27>, /* OCP compliant interrupt */
569				     <81>, /* TX interrupt */
570				     <82>; /* RX interrupt */
571			interrupt-names = "common", "tx", "rx";
572			ti,buffer-size = <128>;
573			ti,hwmods = "mcbsp5";
574			dmas = <&sdma 21>,
575			       <&sdma 22>;
576			dma-names = "tx", "rx";
577			clocks = <&mcbsp5_fck>;
578			clock-names = "fck";
579			status = "disabled";
580		};
581
582		sham: sham@480c3000 {
583			compatible = "ti,omap3-sham";
584			ti,hwmods = "sham";
585			reg = <0x480c3000 0x64>;
586			interrupts = <49>;
587			dmas = <&sdma 69>;
588			dma-names = "rx";
589		};
590
591		timer1: timer@48318000 {
592			compatible = "ti,omap3430-timer";
593			reg = <0x48318000 0x400>;
594			interrupts = <37>;
595			ti,hwmods = "timer1";
596			ti,timer-alwon;
597		};
598
599		timer2: timer@49032000 {
600			compatible = "ti,omap3430-timer";
601			reg = <0x49032000 0x400>;
602			interrupts = <38>;
603			ti,hwmods = "timer2";
604		};
605
606		timer3: timer@49034000 {
607			compatible = "ti,omap3430-timer";
608			reg = <0x49034000 0x400>;
609			interrupts = <39>;
610			ti,hwmods = "timer3";
611		};
612
613		timer4: timer@49036000 {
614			compatible = "ti,omap3430-timer";
615			reg = <0x49036000 0x400>;
616			interrupts = <40>;
617			ti,hwmods = "timer4";
618		};
619
620		timer5: timer@49038000 {
621			compatible = "ti,omap3430-timer";
622			reg = <0x49038000 0x400>;
623			interrupts = <41>;
624			ti,hwmods = "timer5";
625			ti,timer-dsp;
626		};
627
628		timer6: timer@4903a000 {
629			compatible = "ti,omap3430-timer";
630			reg = <0x4903a000 0x400>;
631			interrupts = <42>;
632			ti,hwmods = "timer6";
633			ti,timer-dsp;
634		};
635
636		timer7: timer@4903c000 {
637			compatible = "ti,omap3430-timer";
638			reg = <0x4903c000 0x400>;
639			interrupts = <43>;
640			ti,hwmods = "timer7";
641			ti,timer-dsp;
642		};
643
644		timer8: timer@4903e000 {
645			compatible = "ti,omap3430-timer";
646			reg = <0x4903e000 0x400>;
647			interrupts = <44>;
648			ti,hwmods = "timer8";
649			ti,timer-pwm;
650			ti,timer-dsp;
651		};
652
653		timer9: timer@49040000 {
654			compatible = "ti,omap3430-timer";
655			reg = <0x49040000 0x400>;
656			interrupts = <45>;
657			ti,hwmods = "timer9";
658			ti,timer-pwm;
659		};
660
661		timer10: timer@48086000 {
662			compatible = "ti,omap3430-timer";
663			reg = <0x48086000 0x400>;
664			interrupts = <46>;
665			ti,hwmods = "timer10";
666			ti,timer-pwm;
667		};
668
669		timer11: timer@48088000 {
670			compatible = "ti,omap3430-timer";
671			reg = <0x48088000 0x400>;
672			interrupts = <47>;
673			ti,hwmods = "timer11";
674			ti,timer-pwm;
675		};
676
677		timer12: timer@48304000 {
678			compatible = "ti,omap3430-timer";
679			reg = <0x48304000 0x400>;
680			interrupts = <95>;
681			ti,hwmods = "timer12";
682			ti,timer-alwon;
683			ti,timer-secure;
684		};
685
686		usbhstll: usbhstll@48062000 {
687			compatible = "ti,usbhs-tll";
688			reg = <0x48062000 0x1000>;
689			interrupts = <78>;
690			ti,hwmods = "usb_tll_hs";
691		};
692
693		usbhshost: usbhshost@48064000 {
694			compatible = "ti,usbhs-host";
695			reg = <0x48064000 0x400>;
696			ti,hwmods = "usb_host_hs";
697			#address-cells = <1>;
698			#size-cells = <1>;
699			ranges;
700
701			usbhsohci: ohci@48064400 {
702				compatible = "ti,ohci-omap3";
703				reg = <0x48064400 0x400>;
704				interrupts = <76>;
705				remote-wakeup-connected;
706			};
707
708			usbhsehci: ehci@48064800 {
709				compatible = "ti,ehci-omap";
710				reg = <0x48064800 0x400>;
711				interrupts = <77>;
712			};
713		};
714
715		gpmc: gpmc@6e000000 {
716			compatible = "ti,omap3430-gpmc";
717			ti,hwmods = "gpmc";
718			reg = <0x6e000000 0x02d0>;
719			interrupts = <20>;
720			dmas = <&sdma 4>;
721			dma-names = "rxtx";
722			gpmc,num-cs = <8>;
723			gpmc,num-waitpins = <4>;
724			#address-cells = <2>;
725			#size-cells = <1>;
726			interrupt-controller;
727			#interrupt-cells = <2>;
728			gpio-controller;
729			#gpio-cells = <2>;
730		};
731
732		usb_otg_hs: usb_otg_hs@480ab000 {
733			compatible = "ti,omap3-musb";
734			reg = <0x480ab000 0x1000>;
735			interrupts = <92>, <93>;
736			interrupt-names = "mc", "dma";
737			ti,hwmods = "usb_otg_hs";
738			multipoint = <1>;
739			num-eps = <16>;
740			ram-bits = <12>;
741		};
742
743		dss: dss@48050000 {
744			compatible = "ti,omap3-dss";
745			reg = <0x48050000 0x200>;
746			status = "disabled";
747			ti,hwmods = "dss_core";
748			clocks = <&dss1_alwon_fck>;
749			clock-names = "fck";
750			#address-cells = <1>;
751			#size-cells = <1>;
752			ranges;
753
754			dispc@48050400 {
755				compatible = "ti,omap3-dispc";
756				reg = <0x48050400 0x400>;
757				interrupts = <25>;
758				ti,hwmods = "dss_dispc";
759				clocks = <&dss1_alwon_fck>;
760				clock-names = "fck";
761			};
762
763			dsi: encoder@4804fc00 {
764				compatible = "ti,omap3-dsi";
765				reg = <0x4804fc00 0x200>,
766				      <0x4804fe00 0x40>,
767				      <0x4804ff00 0x20>;
768				reg-names = "proto", "phy", "pll";
769				interrupts = <25>;
770				status = "disabled";
771				ti,hwmods = "dss_dsi1";
772				clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
773				clock-names = "fck", "sys_clk";
774			};
775
776			rfbi: encoder@48050800 {
777				compatible = "ti,omap3-rfbi";
778				reg = <0x48050800 0x100>;
779				status = "disabled";
780				ti,hwmods = "dss_rfbi";
781				clocks = <&dss1_alwon_fck>, <&dss_ick>;
782				clock-names = "fck", "ick";
783			};
784
785			venc: encoder@48050c00 {
786				compatible = "ti,omap3-venc";
787				reg = <0x48050c00 0x100>;
788				status = "disabled";
789				ti,hwmods = "dss_venc";
790				clocks = <&dss_tv_fck>;
791				clock-names = "fck";
792			};
793		};
794
795		ssi: ssi-controller@48058000 {
796			compatible = "ti,omap3-ssi";
797			ti,hwmods = "ssi";
798
799			status = "disabled";
800
801			reg = <0x48058000 0x1000>,
802			      <0x48059000 0x1000>;
803			reg-names = "sys",
804				    "gdd";
805
806			interrupts = <71>;
807			interrupt-names = "gdd_mpu";
808
809			#address-cells = <1>;
810			#size-cells = <1>;
811			ranges;
812
813			ssi_port1: ssi-port@4805a000 {
814				compatible = "ti,omap3-ssi-port";
815
816				reg = <0x4805a000 0x800>,
817				      <0x4805a800 0x800>;
818				reg-names = "tx",
819					    "rx";
820
821				interrupts = <67>,
822					     <68>;
823			};
824
825			ssi_port2: ssi-port@4805b000 {
826				compatible = "ti,omap3-ssi-port";
827
828				reg = <0x4805b000 0x800>,
829				      <0x4805b800 0x800>;
830				reg-names = "tx",
831					    "rx";
832
833				interrupts = <69>,
834					     <70>;
835			};
836		};
837	};
838};
839
840/include/ "omap3xxx-clocks.dtsi"
841